Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23032

1

T1

25

T2

24

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3650

1

T3

1

T6

2

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20960

1

T4

1

T5

9

T6

1

auto[1]

5722

1

T1

25

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T4	1		T259	21		T341	1
values[0]	104	1			T188	26		T249	3		T88	10
values[1]	704	1			T6	1		T149	1		T15	9
values[2]	2826	1			T1	25		T2	24		T10	3
values[3]	502	1			T6	1		T180	4		T243	3
values[4]	660	1			T47	14		T41	6		T157	20
values[5]	645	1			T153	8		T146	23		T36	27
values[6]	679	1			T11	2		T146	13		T165	15
values[7]	610	1			T155	13		T40	13		T55	4
values[8]	664	1			T5	9		T149	1		T39	6
values[9]	1452	1			T3	1		T13	1		T149	1
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	893	1			T6	1		T149	1		T15	20
values[1]	2792	1			T1	25		T2	24		T10	3
values[2]	597	1			T6	1		T180	4		T182	20
values[3]	638	1			T47	14		T153	8		T41	6
values[4]	676	1			T146	23		T224	14		T36	38
values[5]	613	1			T11	2		T146	13		T165	15
values[6]	681	1			T5	9		T149	1		T39	6
values[7]	585	1			T3	1		T265	12		T47	20
values[8]	1090	1			T4	1		T13	1		T149	1
values[9]	268	1			T166	15		T275	9		T278	13
minimum	17849	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T156	1		T37	11		T159	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	1		T149	1		T15	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T1	25		T2	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T25	8		T180	1		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T182	12		T147	3		T251	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	1		T180	1		T43	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T214	10		T152	9		T87	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T47	14		T153	1		T41	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	14		T16	2		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T224	1		T36	16		T182	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T165	1		T170	16		T181	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T146	2		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T149	1		T39	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T188	13		T42	4		T242	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T47	20		T151	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T265	1		T35	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T4	1		T149	1		T47	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T13	1		T27	8		T46	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T275	9		T104	11		T342	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T166	12		T278	13		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17660	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T222	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T156	12		T37	13		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T15	10		T164	16		T188	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T2	21		T44	15		T29	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T25	8		T180	15		T292	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T182	8		T251	8		T304	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T180	3		T43	2		T271	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T214	2		T152	10		T177	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T153	7		T41	2		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	9		T16	6		T156	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T224	13		T36	22		T182	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T165	14		T181	6		T277	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	1		T146	11		T250	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	8		T39	1		T40	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T188	14		T42	1		T86	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T181	4		T51	5		T89	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T265	11		T35	8		T145	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T35	9		T157	15		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T46	2		T146	15		T224	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T104	11		T176	13		T343	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T166	3		T344	5		T305	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T222	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T4	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T259	11		T341	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T249	1		T88	10		T304	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T188	14		T345	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T30	1		T156	1		T37	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	1		T149	1		T15	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T1	25		T2	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	5		T25	8		T164	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T243	1		T182	12		T147	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	1		T180	1		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T214	10		T152	9		T87	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T47	14		T41	4		T157	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T146	14		T16	2		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T153	1		T36	15		T158	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T165	1		T170	16		T181	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	1		T146	2		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T40	7		T55	3		T170	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T155	13		T188	13		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T149	1		T39	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T265	1		T145	17		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T149	1		T47	17		T35	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	436	1			T3	1		T13	1		T27	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T259	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T249	2		T304	7		T316	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T188	12		T346	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T156	12		T37	13		T159	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	4		T180	15		T152	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T2	21		T44	15		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	6		T25	8		T164	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T243	2		T182	8		T251	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T180	3		T293	9		T245	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T214	2		T152	10		T177	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T41	2		T157	9		T271	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T146	9		T16	6		T156	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T153	7		T36	12		T158	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T165	14		T181	6		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	1		T146	11		T224	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T40	6		T55	1		T89	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T188	14		T45	2		T271	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	8		T39	1		T51	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T265	11		T145	14		T224	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T35	9		T157	15		T250	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T46	2		T35	8		T146	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T156	13		T37	14		T159	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T6	1		T149	1		T15	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T1	2		T2	24		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T25	9		T180	16		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T182	9		T147	2		T251	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	1		T180	4		T43	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T214	3		T152	11		T87	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T47	1		T153	8		T41	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T146	10		T16	8		T156	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T224	14		T36	24		T182	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T165	15		T170	1		T181	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	2		T146	12		T250	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	9		T149	1		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T188	15		T42	4		T242	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	1		T151	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T265	12		T35	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T4	1		T149	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T13	1		T27	1		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T275	1		T104	12		T342	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T166	4		T278	1		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17824	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T222	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T37	10		T159	6		T85	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	2		T164	15		T188	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T1	23		T12	26		T164	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T25	7		T292	4		T293	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T182	11		T147	1		T251	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T43	1		T245	11		T162	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T214	9		T152	8		T87	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T47	13		T41	2		T157	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	13		T309	6		T220	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T36	14		T182	9		T218	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T170	15		T181	8		T277	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T146	1		T242	9		T17	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	2		T40	1		T55	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T188	12		T42	1		T242	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T47	19		T181	7		T51	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	12		T155	12		T145	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T47	16		T35	2		T157	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T27	7		T46	6		T146	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T275	8		T104	10		T342	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T166	11		T278	12		T114	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T304	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T222	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T4	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T259	11		T341	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T249	3		T88	1		T304	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T188	13		T345	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T30	1		T156	13		T37	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T149	1		T15	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T1	2		T2	24		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	10		T25	9		T164	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T243	3		T182	9		T147	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	1		T180	4		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T214	3		T152	11		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T47	1		T41	4		T157	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	10		T16	8		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T153	8		T36	13		T158	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T165	15		T170	1		T181	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	2		T146	12		T224	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	12		T55	2		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T155	1		T188	15		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	9		T149	1		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T265	12		T145	15		T224	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T149	1		T47	1		T35	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	427	1			T3	1		T13	1		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T259	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T88	9		T304	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T188	13		T346	17		T347	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T37	10		T159	6		T85	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T15	1		T152	7		T244	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T1	23		T12	26		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	1		T25	7		T164	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T182	11		T147	1		T251	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T293	10		T245	11		T162	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T214	9		T152	8		T87	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	13		T41	2		T157	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T146	13		T220	6		T320	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T36	14		T17	5		T218	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T170	15		T181	8		T277	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T146	1		T242	9		T182	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T40	1		T55	2		T170	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T155	12		T188	12		T242	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T39	2		T47	19		T51	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T145	16		T42	1		T218	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T47	16		T35	2		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T27	7		T46	6		T35	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2