Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23023

1

T1

25

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3659

1

T4

1

T6

1

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20957

1

T4

1

T5

9

T6

1

auto[1]

5725

1

T1

25

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	214	1			T15	11		T55	4		T170	7
values[0]	29	1			T21	13		T173	12		T348	1
values[1]	616	1			T265	12		T164	32		T146	13
values[2]	700	1			T15	9		T39	6		T47	51
values[3]	722	1			T149	2		T30	1		T46	9
values[4]	640	1			T6	1		T13	1		T30	1
values[5]	2852	1			T1	25		T2	24		T10	3
values[6]	494	1			T3	1		T5	9		T149	1
values[7]	745	1			T150	1		T250	10		T42	4
values[8]	777	1			T6	1		T11	2		T25	16
values[9]	1080	1			T4	1		T27	8		T35	12
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	549	1			T15	9		T47	20		T146	13
values[1]	800	1			T39	6		T47	31		T35	21
values[2]	685	1			T13	1		T149	2		T30	1
values[3]	2908	1			T1	25		T2	24		T6	1
values[4]	478	1			T30	1		T224	14		T219	1
values[5]	603	1			T3	1		T5	9		T149	1
values[6]	725	1			T25	16		T165	15		T150	1
values[7]	780	1			T6	1		T11	2		T180	4
values[8]	918	1			T4	1		T15	11		T27	8
values[9]	212	1			T170	7		T88	10		T251	20
minimum	18024	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T47	20		T42	1		T258	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T15	5		T146	2		T152	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T166	12		T157	13		T242	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T39	5		T47	31		T35	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T153	1		T180	1		T146	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T149	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1541	1			T1	25		T2	3		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	1		T224	1		T257	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T30	1		T224	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T249	1		T43	1		T45	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T5	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T164	3		T36	1		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T25	8		T165	1		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T150	1		T42	3		T85	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T180	1		T36	15		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	1		T11	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	5		T27	8		T55	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T4	1		T35	3		T40	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T170	7		T330	1		T298	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T88	10		T251	12		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17691	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T265	1		T164	16		T309	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T258	2		T160	9		T316	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T15	4		T146	11		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T166	3		T157	15		T214	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T39	1		T35	8		T181	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T153	7		T180	5		T146	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	2		T16	6		T157	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T2	21		T44	15		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T224	15		T266	14		T332	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T224	13		T259	10		T205	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T249	2		T45	2		T245	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	8		T180	15		T250	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T164	4		T36	10		T89	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T25	8		T165	14		T250	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T42	1		T85	11		T304	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T180	3		T36	12		T188	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	1		T145	11		T41	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	6		T55	1		T181	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T35	9		T40	6		T145	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T298	5		T195	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T251	8		T277	2		T269	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T265	11		T164	16		T309	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T15	5		T55	3		T170	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T271	1		T171	1		T309	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T173	1		T337	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T21	5		T348	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T42	1		T258	3		T336	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T265	1		T164	16		T146	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T47	20		T166	12		T157	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T15	5		T39	5		T47	31
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T153	1		T180	1		T146	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T149	2		T30	1		T46	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	1		T146	14		T170	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	1		T30	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T1	25		T2	3		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	1		T45	2		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	1		T5	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T164	3		T36	1		T249	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T250	1		T182	10		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T150	1		T42	3		T85	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T25	8		T180	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	1		T11	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T27	8		T188	14		T181	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T4	1		T35	3		T40	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T15	6		T55	1		T252	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T271	10		T309	2		T269	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T173	11		T337	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T21	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T258	2		T316	17		T203	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T265	11		T164	16		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T166	3		T157	15		T214	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	4		T39	1		T35	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T153	7		T180	5		T146	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	2		T157	9		T254	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T146	9		T17	4		T271	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T224	15		T16	6		T152	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T2	21		T44	15		T29	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T45	2		T270	2		T332	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T5	8		T180	15		T250	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T164	4		T36	10		T249	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T250	9		T182	9		T158	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T42	1		T85	11		T161	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T25	8		T180	3		T165	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	1		T145	11		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T188	12		T181	10		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T35	9		T40	6		T145	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T47	1		T42	1		T258	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	8		T146	12		T152	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T166	4		T157	16		T242	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T39	4		T47	2		T35	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T153	8		T180	6		T146	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	1		T149	2		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T1	2		T2	24		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T30	1		T224	16		T257	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T30	1		T224	14		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T249	3		T43	1		T45	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T5	9		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T164	5		T36	11		T89	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T25	9		T165	15		T250	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T150	1		T42	3		T85	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T180	4		T36	13		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T11	2		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T15	10		T27	1		T55	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T4	1		T35	10		T40	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T170	1		T330	1		T298	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T88	1		T251	9		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17866	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T265	12		T164	17		T309	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T47	19		T258	1		T349	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T15	1		T146	1		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T166	11		T157	12		T242	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T39	2		T47	29		T35	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T146	18		T17	5		T159	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T46	6		T155	12		T157	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T1	23		T12	26		T261	35
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T332	10		T281	21		T280	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T259	10		T205	7		T99	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T245	11		T315	15		T307	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T218	16		T260	5		T276	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T164	2		T177	16		T179	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	7		T182	9		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T42	1		T85	12		T304	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	14		T188	13		T242	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T145	11		T41	2		T51	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	1		T27	7		T55	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T35	2		T40	1		T145	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T170	6		T59	1		T195	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T88	9		T251	11		T277	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T121	1		T279	15		T321	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T164	15		T309	6		T21	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T15	10		T55	2		T170	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T271	11		T171	1		T309	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T173	12		T337	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T21	10		T348	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T42	1		T258	4		T336	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T265	12		T164	17		T146	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T47	1		T166	4		T157	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	8		T39	4		T47	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T153	8		T180	6		T146	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T149	2		T30	1		T46	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T146	10		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T30	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T1	2		T2	24		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	1		T45	4		T270	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T5	9		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T164	5		T36	11		T249	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T250	10		T182	10		T158	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T150	1		T42	3		T85	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	9		T180	4		T165	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	1		T11	2		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T27	1		T188	13		T181	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T4	1		T35	10		T40	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T15	1		T55	2		T170	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T269	13		T280	11		T339	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T21	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T258	1		T121	1		T349	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T164	15		T146	1		T152	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T47	19		T166	11		T157	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T15	1		T39	2		T47	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T146	18		T159	15		T147	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T46	6		T155	12		T157	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T146	13		T170	14		T17	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T152	13		T244	13		T293	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	23		T12	26		T261	35
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T332	10		T291	20		T315	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T218	16		T260	5		T162	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T164	2		T177	16		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T182	9		T177	11		T260	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T42	1		T85	12		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T25	7		T36	14		T242	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T145	11		T41	2		T51	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T27	7		T188	13		T181	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T35	2		T40	1		T145	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2