Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21123

1

T3

1

T5

9

T6

1

auto[ADC_CTRL_FILTER_COND_OUT]

5559

1

T1

25

T2

24

T4

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20647

1

T4

1

T5

9

T6

2

auto[1]

6035

1

T1

25

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	399	1			T6	1		T25	16		T46	9
values[0]	41	1			T159	9		T298	6		T299	6
values[1]	758	1			T149	1		T47	14		T35	21
values[2]	735	1			T149	1		T30	1		T146	23
values[3]	576	1			T3	1		T154	1		T169	1
values[4]	623	1			T4	1		T5	9		T6	1
values[5]	543	1			T153	8		T150	1		T166	15
values[6]	728	1			T30	1		T55	4		T41	6
values[7]	572	1			T149	1		T146	34		T165	15
values[8]	702	1			T15	11		T27	8		T30	1
values[9]	3192	1			T1	25		T2	24		T10	3
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	740	1			T149	1		T35	21		T263	13
values[1]	2898	1			T1	25		T2	24		T3	1
values[2]	656	1			T4	1		T154	1		T166	1
values[3]	575	1			T5	9		T6	1		T13	1
values[4]	532	1			T153	8		T55	4		T170	7
values[5]	699	1			T30	1		T146	34		T41	6
values[6]	668	1			T149	1		T27	8		T35	12
values[7]	543	1			T15	11		T30	1		T39	6
values[8]	1014	1			T6	1		T11	2		T15	9
values[9]	265	1			T180	16		T145	31		T151	1
minimum	18092	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T169	1		T350	1		T259	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T149	1		T35	13		T263	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T149	1		T146	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1566	1			T1	25		T2	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T169	1		T250	1		T242	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	1		T154	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	1		T6	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T170	15		T51	6		T271	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T153	1		T55	3		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T170	7		T43	4		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T224	1		T216	1		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	1		T146	19		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T149	1		T27	8		T146	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	3		T165	1		T188	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	5		T30	1		T164	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	5		T40	7		T177	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T15	5		T46	7		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	1		T11	1		T25	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T180	1		T151	1		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T145	17		T181	8		T18	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17774	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T180	1		T151	1		T159	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T259	10		T160	9		T316	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T35	8		T263	6		T89	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T146	9		T224	13		T36	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	971	1			T2	21		T44	15		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T250	8		T244	1		T160	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T16	6		T157	9		T17	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	8		T145	11		T166	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T51	5		T271	10		T266	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	7		T55	1		T85	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T43	2		T86	6		T89	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T224	15		T152	7		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T146	15		T41	2		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T146	11		T42	1		T177	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T35	9		T165	14		T188	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	6		T164	4		T180	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T39	1		T40	6		T177	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T15	4		T46	2		T265	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	1		T25	8		T164	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T180	15		T243	2		T252	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T145	14		T181	4		T18	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T180	3		T349	1		T351	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T46	7		T265	1		T180	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	1		T25	8		T145	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T298	1		T299	6		T352	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T159	9		T353	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T47	14		T169	1		T244	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T149	1		T35	13		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T149	1		T146	14		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T30	1		T16	2		T260	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	1		T169	1		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T154	1		T157	11		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	1		T6	1		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	1		T166	1		T170	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T153	1		T150	1		T166	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	4		T51	6		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T55	3		T224	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	1		T41	4		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T149	1		T42	3		T218	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T146	19		T165	1		T250	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T15	5		T27	8		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	5		T35	3		T40	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T15	5		T47	20		T180	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1695	1			T1	25		T2	3		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T46	2		T265	11		T180	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T25	8		T145	14		T181	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T298	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T244	12		T259	10		T160	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T35	8		T180	3		T263	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T146	9		T224	13		T36	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T16	6		T260	8		T245	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T250	8		T244	1		T148	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T157	9		T158	3		T17	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	8		T145	11		T157	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T259	10		T266	11		T289	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T153	7		T166	3		T85	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	2		T51	5		T89	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T55	1		T224	15		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T41	2		T156	12		T37	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T42	1		T177	10		T260	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T146	15		T165	14		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	6		T164	4		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T39	1		T35	9		T40	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	4		T180	5		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1054	1			T2	21		T11	1		T44	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T169	1		T350	1		T259	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T149	1		T35	9		T263	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	1		T149	1		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1298	1			T1	2		T2	24		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T169	1		T250	9		T242	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	1		T154	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	9		T6	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T170	1		T51	6		T271	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T153	8		T55	2		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T170	1		T43	5		T86	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T224	16		T216	1		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T30	1		T146	16		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T149	1		T27	1		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T35	10		T165	15		T188	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	10		T30	1		T164	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T39	4		T40	12		T177	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T15	8		T46	3		T265	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	1		T11	2		T25	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T180	16		T151	1		T243	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T145	15		T181	5		T18	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17879	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T180	4		T151	1		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T259	10		T276	17		T320	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T35	12		T263	6		T245	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T146	13		T36	14		T188	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1239	1			T1	23		T12	26		T261	35
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T242	4		T301	16		T302	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T157	10		T17	5		T259	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T155	12		T145	11		T166	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T170	14		T51	5		T162	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T55	2		T85	7		T292	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T170	6		T43	1		T260	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T152	7		T88	9		T260	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T146	18		T41	2		T37	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T27	7		T146	1		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T35	2		T188	12		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T164	2		T242	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T39	2		T40	1		T177	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	1		T46	6		T47	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T25	7		T47	16		T164	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T105	14		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T145	16		T181	7		T205	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T47	13		T244	13		T299	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T159	8		T349	1		T313	21

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T46	3		T265	12		T180	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	1		T25	9		T145	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T298	6		T299	5		T352	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T159	1		T353	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T47	1		T169	1		T244	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T149	1		T35	9		T180	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T149	1		T146	10		T224	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T30	1		T16	8		T260	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	1		T169	1		T250	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T154	1		T157	10		T158	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	9		T6	1		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	1		T166	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T153	8		T150	1		T166	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T43	5		T51	6		T89	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T55	2		T224	16		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T30	1		T41	4		T156	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T149	1		T42	3		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T146	16		T165	15		T250	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T15	10		T27	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T39	4		T35	10		T40	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T15	8		T47	1		T180	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1385	1			T1	2		T2	24		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T46	6		T152	13		T85	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T25	7		T145	16		T170	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T299	1		T268	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T159	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	13		T244	13		T259	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	12		T263	6		T269	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T146	13		T36	14		T188	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T260	7		T245	11		T267	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T242	4		T148	7		T172	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T157	10		T17	5		T284	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T155	12		T145	11		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T170	14		T259	10		T162	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T166	11		T85	7		T292	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T43	1		T51	5		T260	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T55	2		T152	7		T277	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T41	2		T37	10		T170	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T42	1		T218	7		T88	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T146	18		T242	3		T147	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T15	1		T27	7		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	2		T35	2		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	1		T47	19		T214	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1364	1			T1	23		T12	26		T47	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2