Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23220

1

T1

25

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3462

1

T5

9

T6

2

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20527

1

T6

1

T7

14

T8

231

auto[1]

6155

1

T1

25

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	239	1			T25	16		T153	8		T155	13
values[0]	64	1			T188	27		T183	1		T274	13
values[1]	756	1			T6	1		T46	9		T35	21
values[2]	578	1			T5	9		T39	6		T265	12
values[3]	591	1			T15	9		T30	1		T164	7
values[4]	891	1			T4	1		T149	3		T30	1
values[5]	466	1			T6	1		T11	2		T13	1
values[6]	553	1			T166	15		T36	11		T156	13
values[7]	889	1			T3	1		T47	17		T35	12
values[8]	696	1			T27	8		T30	1		T47	20
values[9]	3146	1			T1	25		T2	24		T10	3
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	807	1			T39	6		T265	12		T35	21
values[1]	483	1			T5	9		T15	9		T145	23
values[2]	774	1			T149	1		T30	1		T164	7
values[3]	750	1			T4	1		T11	2		T149	2
values[4]	520	1			T13	1		T180	16		T150	1
values[5]	658	1			T6	1		T166	15		T36	11
values[6]	3091	1			T1	25		T2	24		T3	1
values[7]	658	1			T30	1		T151	1		T169	1
values[8]	866	1			T15	11		T25	16		T47	14
values[9]	75	1			T153	8		T180	4		T241	1
minimum	18000	1			T6	1		T7	14		T8	231

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T39	5		T35	13		T40	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T265	1		T224	1		T37	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T15	5		T165	1		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	1		T145	12		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T30	1		T164	3		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T149	1		T154	1		T157	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	1		T11	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T149	1		T30	1		T146	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T180	1		T158	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	1		T150	1		T188	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T166	12		T170	7		T242	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	1		T36	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T1	25		T2	3		T3	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T27	8		T47	20		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T152	14		T249	1		T266	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	1		T151	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T15	5		T55	3		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T25	8		T47	14		T155	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T153	1		T241	1		T281	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T180	1		T17	2		T220	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17703	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T6	1		T326	1		T316	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T39	1		T35	8		T40	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T265	11		T224	13		T37	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T15	4		T165	14		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	8		T145	11		T41	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T164	4		T224	15		T181	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T157	9		T158	5		T159	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	1		T180	5		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T146	11		T181	6		T85	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T180	15		T158	3		T271	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T188	12		T45	2		T260	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T166	3		T51	5		T177	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	10		T156	12		T181	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T2	21		T44	15		T29	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T35	9		T164	16		T263	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T152	14		T249	2		T266	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T292	4		T245	10		T270	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	6		T55	1		T250	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T25	8		T182	8		T214	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T153	7		T281	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T180	3		T272	9		T187	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	2		T15	9		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T316	16		T107	9		T300	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T153	1		T241	1		T242	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T25	8		T155	13		T242	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T188	13		T183	1		T274	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T300	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T46	7		T35	13		T40	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T224	1		T37	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T39	5		T165	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T265	1		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	5		T30	1		T164	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T157	11		T158	1		T159	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T4	1		T149	1		T181	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T149	2		T30	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	1		T180	2		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	1		T13	1		T146	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T166	12		T170	7		T242	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T36	1		T156	1		T170	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	1		T47	17		T36	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	3		T166	1		T263	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	14		T16	2		T250	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T27	8		T30	1		T47	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1722	1			T1	25		T2	3		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T47	14		T180	1		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T153	7		T89	15		T281	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T25	8		T214	2		T354	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T188	14		T274	4		T355	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T300	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T46	2		T35	8		T40	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T224	13		T37	13		T157	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T39	1		T165	14		T243	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	8		T265	11		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T15	4		T164	4		T224	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T157	9		T158	5		T159	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T181	4		T85	12		T252	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T181	6		T85	9		T260	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T11	1		T180	20		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T146	11		T188	12		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T166	3		T51	5		T177	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T36	10		T156	12		T45	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T36	12		T159	12		T85	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T35	9		T263	6		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	9		T16	6		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T164	16		T43	2		T292	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T2	21		T44	15		T15	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T180	3		T182	8		T152	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	4		T35	9		T40	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T265	12		T224	14		T37	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	8		T165	15		T243	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	9		T145	12		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T30	1		T164	5		T224	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T149	1		T154	1		T157	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	1		T11	2		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T149	1		T30	1		T146	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T180	16		T158	4		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	1		T150	1		T188	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T166	4		T170	1		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T36	11		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T1	2		T2	24		T3	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T27	1		T47	1		T35	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T152	15		T249	3		T266	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	1		T151	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T15	10		T55	2		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T25	9		T47	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T153	8		T241	1		T281	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T180	4		T17	2		T220	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17885	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T6	1		T326	1		T316	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T39	2		T35	12		T40	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T37	10		T157	12		T332	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T15	1		T218	16		T220	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T145	11		T41	2		T17	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T164	2		T181	7		T267	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T157	10		T159	6		T275	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T42	1		T85	10		T148	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T146	1		T181	8		T218	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T277	8		T278	12		T101	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T188	13		T260	3		T114	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T166	11		T170	6		T242	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T170	15		T181	15		T182	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T1	23		T12	26		T47	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T27	7		T47	19		T35	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	13		T280	11		T313	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T88	9		T292	4		T245	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	1		T55	2		T242	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T25	7		T47	13		T155	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T281	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T220	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T46	6		T188	12		T274	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T107	10		T300	5		T222	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T153	8		T241	1		T242	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T25	9		T155	1		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T188	15		T183	1		T274	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T300	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T46	3		T35	9		T40	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T6	1		T224	14		T37	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	4		T165	15		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	9		T265	12		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	8		T30	1		T164	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T157	10		T158	6		T159	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	1		T149	1		T181	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T149	2		T30	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	2		T180	22		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T13	1		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T166	4		T170	1		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T36	11		T156	13		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T3	1		T47	1		T36	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T35	10		T166	1		T263	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	10		T16	8		T250	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T27	1		T30	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T1	2		T2	24		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T47	1		T180	4		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T242	4		T281	13		T294	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T25	7		T155	12		T242	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T188	12		T274	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T300	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T46	6		T35	12		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T37	10		T157	12		T332	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T39	2		T218	16		T299	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T145	11		T41	2		T17	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T15	1		T164	2		T220	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T157	10		T159	6		T275	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T181	7		T85	10		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T181	8		T85	7		T260	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T42	1		T277	8		T278	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T146	1		T188	13		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T166	11		T170	6		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T170	15		T267	15		T284	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	16		T36	14		T159	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T35	2		T263	6		T181	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	13		T152	13		T278	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T27	7		T47	19		T164	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T1	23		T12	26		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	13		T182	11		T152	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2