Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23002

1

T1

25

T2

24

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3680

1

T3

1

T6

2

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20977

1

T4

1

T5

9

T6

1

auto[1]

5705

1

T1

25

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	296	1			T13	1		T166	15		T219	1
values[0]	42	1			T188	26		T304	9		T288	1
values[1]	734	1			T6	1		T149	1		T15	20
values[2]	2853	1			T1	25		T2	24		T10	3
values[3]	493	1			T6	1		T180	4		T182	20
values[4]	673	1			T47	14		T41	6		T157	20
values[5]	655	1			T153	8		T146	23		T224	14
values[6]	686	1			T11	2		T146	13		T165	15
values[7]	560	1			T149	1		T155	13		T40	13
values[8]	691	1			T5	9		T39	6		T265	12
values[9]	1186	1			T3	1		T4	1		T149	1
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	698	1			T6	1		T149	1		T15	20
values[1]	2770	1			T1	25		T2	24		T6	1
values[2]	592	1			T180	4		T182	20		T43	6
values[3]	602	1			T47	14		T41	6		T157	20
values[4]	740	1			T153	8		T146	23		T224	14
values[5]	596	1			T11	2		T146	13		T165	15
values[6]	705	1			T5	9		T149	1		T39	6
values[7]	557	1			T3	1		T47	20		T35	21
values[8]	1150	1			T4	1		T13	1		T149	1
values[9]	203	1			T275	9		T278	13		T344	6
minimum	18069	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T30	1		T156	1		T159	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	1		T149	1		T15	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T1	25		T2	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	1		T25	8		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T182	12		T147	3		T251	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T180	1		T43	4		T271	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T214	10		T152	9		T87	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T47	14		T41	4		T157	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T146	14		T16	2		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T153	1		T224	1		T36	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T165	1		T170	16		T181	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	1		T146	2		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	1		T149	1		T39	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T265	1		T155	13		T188	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T47	20		T151	1		T181	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	1		T35	13		T145	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T4	1		T149	1		T47	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T13	1		T27	8		T46	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T275	9		T104	11		T176	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T278	13		T344	1		T305	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17698	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T30	1		T152	8		T277	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T156	12		T159	2		T249	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	10		T164	16		T188	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T2	21		T44	15		T29	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	8		T180	15		T292	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T182	8		T251	8		T304	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T180	3		T43	2		T271	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T214	2		T152	10		T177	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T41	2		T157	9		T158	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	9		T16	6		T156	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T153	7		T224	13		T36	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T165	14		T181	6		T270	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	1		T146	11		T250	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	8		T39	1		T40	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T265	11		T188	14		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T181	4		T51	5		T89	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T35	8		T145	14		T224	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T35	9		T157	15		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T46	2		T146	15		T166	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T104	11		T176	13		T343	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T344	5		T305	12		T101	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T152	7		T277	2		T269	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T85	8		T207	1		T99	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	1		T166	12		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T304	2		T288	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T188	14		T345	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T30	1		T156	1		T37	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	1		T149	1		T15	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T1	25		T2	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T25	8		T164	16		T180	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T182	12		T147	3		T251	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T180	1		T293	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T214	10		T152	9		T87	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T47	14		T41	4		T157	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T146	14		T16	2		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T153	1		T224	1		T36	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T165	1		T170	16		T181	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	1		T146	2		T250	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T149	1		T40	7		T55	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T155	13		T188	13		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	1		T39	5		T47	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T265	1		T145	17		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T4	1		T149	1		T47	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T3	1		T27	8		T46	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T85	9		T104	11		T295	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T166	3		T332	12		T344	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T304	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T188	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T156	12		T37	13		T159	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	10		T152	7		T244	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T2	21		T44	15		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T25	8		T164	16		T180	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T182	8		T251	8		T298	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T180	3		T293	9		T245	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T214	2		T152	10		T177	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T41	2		T157	9		T271	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T146	9		T16	6		T156	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T153	7		T224	13		T36	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	14		T181	6		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	1		T146	11		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T40	6		T55	1		T89	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T188	14		T45	2		T271	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	8		T39	1		T51	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T265	11		T145	14		T224	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T35	9		T157	15		T250	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T46	2		T35	8		T146	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	1		T156	13		T159	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	1		T149	1		T15	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T1	2		T2	24		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	1		T25	9		T180	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T182	9		T147	2		T251	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T180	4		T43	5		T271	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T214	3		T152	11		T87	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T47	1		T41	4		T157	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T146	10		T16	8		T156	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T153	8		T224	14		T36	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T165	15		T170	1		T181	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	2		T146	12		T250	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	9		T149	1		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T265	12		T155	1		T188	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T47	1		T151	1		T181	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T35	9		T145	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T4	1		T149	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T13	1		T27	1		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T275	1		T104	12		T176	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T278	1		T344	6		T305	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17858	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T30	1		T152	8		T277	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T159	6		T85	12		T88	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	2		T164	15		T188	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T1	23		T12	26		T164	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T25	7		T292	4		T293	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T182	11		T147	1		T251	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T43	1		T245	11		T162	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T214	9		T152	8		T87	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T47	13		T41	2		T157	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T146	13		T309	6		T220	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T36	14		T182	9		T17	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T170	15		T181	8		T267	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T146	1		T242	9		T301	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	2		T40	1		T55	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T155	12		T188	12		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T47	19		T181	7		T51	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T35	12		T145	16		T218	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T47	16		T35	2		T157	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T27	7		T46	6		T146	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T275	8		T104	10		T176	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T278	12		T305	12		T283	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T37	10		T221	11		T311	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T152	7		T277	2		T269	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T85	10		T207	1		T99	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T13	1		T166	4		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T304	8		T288	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T188	13		T345	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T30	1		T156	13		T37	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	1		T149	1		T15	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T1	2		T2	24		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T25	9		T164	17		T180	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T182	9		T147	2		T251	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	1		T180	4		T293	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T214	3		T152	11		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T47	1		T41	4		T157	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T146	10		T16	8		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T153	8		T224	14		T36	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T165	15		T170	1		T181	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	2		T146	12		T250	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T149	1		T40	12		T55	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T155	1		T188	15		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	9		T39	4		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T265	12		T145	15		T224	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T4	1		T149	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T3	1		T27	1		T46	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T85	7		T99	13		T104	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T166	11		T332	10		T278	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T304	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T188	13		T347	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	10		T159	6		T85	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T15	2		T152	7		T244	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T1	23		T12	26		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T25	7		T164	15		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T182	11		T147	1		T251	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T293	10		T245	11		T162	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T214	9		T152	8		T87	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T47	13		T41	2		T157	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T146	13		T220	6		T320	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	14		T17	5		T218	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T170	15		T181	8		T277	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T146	1		T242	9		T182	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T40	1		T55	2		T170	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T155	12		T188	12		T242	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	2		T47	19		T51	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T145	16		T42	1		T218	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T47	16		T35	2		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T27	7		T46	6		T35	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2