Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T39	4		T46	3		T35	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T6	1		T265	12		T37	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	8		T165	15		T243	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	9		T145	12		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	1		T164	5		T224	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T149	1		T154	1		T157	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	1		T149	1		T180	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	1		T149	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	2		T180	16		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T150	1		T188	13		T45	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T166	4		T170	1		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T166	1		T36	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T1	2		T2	24		T3	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	1		T47	1		T35	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T169	1		T152	15		T266	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	1		T151	1		T88	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T15	10		T250	9		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	9		T47	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T153	8		T55	2		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T180	4		T17	2		T267	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T224	14		T268	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T39	2		T46	6		T35	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T37	10		T157	12		T170	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T15	1		T218	16		T220	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	11		T41	2		T17	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T164	2		T181	7		T267	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T157	10		T275	8		T269	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T85	10		T148	7		T276	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T146	1		T181	8		T218	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T42	1		T277	8		T278	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T188	13		T260	3		T279	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T166	11		T170	6		T242	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T170	15		T181	15		T182	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T1	23		T12	26		T47	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T27	7		T47	19		T35	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T152	13		T269	13		T280	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T88	9		T245	11		T21	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	1		T242	4		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T25	7		T47	13		T155	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T55	2		T20	1		T281	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T220	10		T282	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T268	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T155	1		T220	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T188	15		T162	1		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	3		T35	9		T40	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	1		T224	14		T37	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	4		T165	15		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	9		T265	12		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	8		T30	1		T164	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T157	10		T159	3		T273	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T149	1		T180	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T149	2		T30	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	2		T180	16		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T13	1		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T166	4		T170	1		T85	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	11		T156	13		T181	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	1		T47	1		T146	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T35	10		T166	1		T263	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	8		T152	15		T249	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T27	1		T30	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T1	2		T2	24		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T25	9		T47	1		T180	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T155	12		T220	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T188	12		T162	8		T274	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T46	6		T35	12		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T37	10		T157	12		T170	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T39	2		T218	16		T283	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T145	11		T41	2		T147	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T164	2		T181	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T157	10		T159	6		T259	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T42	1		T85	10		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T181	8		T85	7		T260	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T242	3		T277	8		T278	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T146	1		T188	13		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T166	11		T170	6		T85	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T181	15		T51	5		T284	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T47	16		T146	13		T36	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T35	2		T263	6		T170	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T152	13		T269	13		T278	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	7		T47	19		T164	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T1	23		T12	26		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T25	7		T47	13		T242	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2