Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21113

1

T3

1

T5

9

T6

1

auto[ADC_CTRL_FILTER_COND_OUT]

5569

1

T1

25

T2

24

T4

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20729

1

T4

1

T5

9

T6

2

auto[1]

5953

1

T1

25

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	46	1			T25	16		T151	1		T170	16
values[0]	40	1			T159	9		T298	6		T299	6
values[1]	775	1			T149	1		T47	14		T180	4
values[2]	687	1			T149	1		T30	1		T35	21
values[3]	566	1			T3	1		T154	1		T169	1
values[4]	677	1			T4	1		T5	9		T6	1
values[5]	562	1			T153	8		T150	1		T166	15
values[6]	728	1			T30	1		T55	4		T41	6
values[7]	580	1			T27	8		T146	34		T165	15
values[8]	660	1			T149	1		T15	11		T30	1
values[9]	3548	1			T1	25		T2	24		T6	1
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1046	1			T149	1		T47	14		T35	21
values[1]	2893	1			T1	25		T2	24		T3	1
values[2]	624	1			T4	1		T154	1		T166	1
values[3]	558	1			T5	9		T6	1		T13	1
values[4]	620	1			T153	8		T55	4		T41	6
values[5]	630	1			T30	1		T146	34		T224	16
values[6]	674	1			T149	1		T15	11		T27	8
values[7]	578	1			T30	1		T164	7		T180	6
values[8]	796	1			T6	1		T11	2		T15	9
values[9]	450	1			T265	12		T164	32		T180	16
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T47	14		T169	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T149	1		T35	13		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T149	1		T146	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1570	1			T1	25		T2	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T169	1		T250	1		T242	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	1		T154	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T6	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T170	15		T51	6		T271	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T153	1		T55	3		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T41	4		T170	7		T43	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T224	1		T216	1		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T30	1		T146	19		T37	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T149	1		T15	5		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	5		T35	3		T146	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T30	1		T164	3		T180	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T229	1		T275	9		T277	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T15	5		T46	7		T47	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T11	1		T25	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T265	1		T180	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T164	16		T145	17		T181	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T158	5		T244	12		T259	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	8		T180	3		T263	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	9		T36	12		T156	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	998	1			T2	21		T44	15		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T250	8		T244	1		T160	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T16	6		T157	9		T17	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	8		T145	11		T166	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T51	5		T271	10		T260	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T153	7		T55	1		T292	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	2		T43	2		T89	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T224	15		T152	7		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T146	15		T37	13		T250	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	6		T42	1		T177	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T39	1		T35	9		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T164	4		T180	5		T40	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T229	13		T277	2		T198	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	4		T46	2		T243	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T25	8		T36	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T265	11		T180	15		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T164	16		T145	14		T181	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T151	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T25	8		T170	16		T300	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T298	1		T299	6		T268	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T159	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T47	14		T169	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T149	1		T180	1		T263	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T149	1		T146	14		T36	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T30	1		T35	13		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	1		T169	1		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T154	1		T157	11		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T6	1		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	1		T166	1		T170	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T153	1		T150	1		T166	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T43	4		T51	6		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T55	3		T224	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T30	1		T41	4		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T27	8		T42	3		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T146	19		T165	1		T250	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T149	1		T15	5		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T39	5		T35	3		T146	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T15	5		T46	7		T265	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1820	1			T1	25		T2	3		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T25	8		T300	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T298	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T158	5		T244	12		T259	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T180	3		T263	6		T89	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	9		T36	12		T156	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T35	8		T224	13		T16	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T250	8		T244	1		T148	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T157	9		T158	3		T17	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	8		T145	11		T157	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T259	10		T266	11		T289	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T153	7		T166	3		T85	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T43	2		T51	5		T89	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	1		T224	15		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T41	2		T156	12		T37	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T42	1		T152	7		T177	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T146	15		T165	14		T250	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	6		T164	4		T180	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T39	1		T35	9		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T15	4		T46	2		T265	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1177	1			T2	21		T11	1		T44	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T47	1		T169	1		T158	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T149	1		T35	9		T180	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T149	1		T146	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1319	1			T1	2		T2	24		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T169	1		T250	9		T242	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	1		T154	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	9		T6	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T170	1		T51	6		T271	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T153	8		T55	2		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T41	4		T170	1		T43	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T224	16		T216	1		T152	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	1		T146	16		T37	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T149	1		T15	10		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T39	4		T35	10		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T30	1		T164	5		T180	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T229	14		T275	1		T277	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	8		T46	3		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	1		T11	2		T25	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T265	12		T180	16		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T164	17		T145	15		T181	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T47	13		T244	13		T259	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T35	12		T263	6		T159	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T146	13		T36	14		T188	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1249	1			T1	23		T12	26		T261	35
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T242	4		T301	16		T302	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T157	10		T17	5		T259	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T155	12		T145	11		T166	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T170	14		T51	5		T260	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T55	2		T292	4		T290	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	2		T170	6		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T152	7		T88	9		T260	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T146	18		T37	10		T152	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	1		T27	7		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T39	2		T35	2		T146	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T164	2		T40	1		T242	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T275	8		T277	2		T220	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	1		T46	6		T47	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	7		T47	16		T170	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T105	14		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T164	15		T145	16		T181	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T151	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T25	9		T170	1		T300	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T298	6		T299	5		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T159	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T47	1		T169	1		T158	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T149	1		T180	4		T263	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T149	1		T146	10		T36	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T30	1		T35	9		T224	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T169	1		T250	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T154	1		T157	10		T158	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	9		T6	1		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	1		T166	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T153	8		T150	1		T166	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	5		T51	6		T89	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T55	2		T224	16		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	1		T41	4		T156	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	1		T42	3		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T146	16		T165	15		T250	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T149	1		T15	10		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T39	4		T35	10		T146	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T15	8		T46	3		T265	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1528	1			T1	2		T2	24		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T25	7		T170	15		T300	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T299	1		T268	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T159	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T47	13		T244	13		T259	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T263	6		T269	12		T278	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T146	13		T36	14		T188	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T35	12		T260	7		T245	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T242	4		T148	7		T172	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T157	10		T17	5		T284	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T155	12		T145	11		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T170	14		T259	10		T162	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T166	11		T85	7		T179	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T43	1		T51	5		T260	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T55	2		T292	4		T277	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T41	2		T37	10		T170	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T27	7		T42	1		T152	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T146	18		T242	3		T147	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T15	1		T164	2		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T39	2		T35	2		T146	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	1		T46	6		T47	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1469	1			T1	23		T12	26		T47	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2