Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22989

1

T1

25

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3693

1

T6

2

T11

2

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20530

1

T4

1

T5

9

T6

2

auto[1]

6152

1

T1

25

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T172	13		T185	6		-	-
values[0]	29	1			T188	27		T303	2		-	-
values[1]	700	1			T6	1		T39	6		T180	6
values[2]	739	1			T35	21		T164	32		T55	4
values[3]	652	1			T30	1		T180	4		T151	1
values[4]	603	1			T149	1		T27	8		T47	14
values[5]	779	1			T6	1		T13	1		T30	1
values[6]	725	1			T4	1		T5	9		T25	16
values[7]	445	1			T15	9		T30	1		T265	12
values[8]	2837	1			T1	25		T2	24		T10	3
values[9]	1341	1			T3	1		T149	2		T15	11
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	750	1			T6	1		T39	6		T180	6
values[1]	847	1			T30	1		T35	21		T40	13
values[2]	611	1			T47	14		T164	32		T180	4
values[3]	647	1			T149	1		T27	8		T164	7
values[4]	854	1			T4	1		T6	1		T13	1
values[5]	618	1			T47	37		T146	47		T169	1
values[6]	2703	1			T1	25		T2	24		T5	9
values[7]	694	1			T180	16		T145	23		T241	1
values[8]	935	1			T3	1		T11	2		T149	1
values[9]	205	1			T149	1		T15	11		T46	9
minimum	17818	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T36	15		T152	14		T249	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T39	5		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T30	1		T35	13		T55	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T40	7		T250	1		T218	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T164	16		T180	1		T182	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T47	14		T181	16		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T149	1		T164	3		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T27	8		T166	12		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	1		T30	1		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T6	1		T13	1		T25	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T146	2		T242	4		T304	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T47	37		T146	19		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T1	25		T2	3		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T15	5		T30	1		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T241	1		T242	5		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T180	1		T145	12		T257	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	1		T35	3		T263	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T11	1		T149	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T149	1		T46	7		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T15	5		T17	2		T161	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T172	1		T114	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	12		T152	14		T249	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T39	1		T180	5		T224	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T35	8		T55	1		T157	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T40	6		T250	9		T85	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T164	16		T180	3		T182	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T181	18		T89	15		T177	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T164	4		T224	15		T181	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T166	3		T214	2		T271	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T156	16		T157	15		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T25	8		T146	9		T165	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T146	11		T304	14		T161	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	15		T158	18		T292	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T2	21		T5	8		T44	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	4		T265	11		T37	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T243	3		T270	12		T281	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T180	15		T145	11		T188	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T35	9		T263	6		T16	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	1		T153	7		T145	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T46	2		T269	11		T163	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T15	6		T246	2		T175	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T114	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T185	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T172	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T188	13		T303	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T36	15		T249	1		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	1		T39	5		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T35	13		T164	16		T55	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T170	16		T218	25		T85	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	1		T180	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T250	1		T181	16		T88	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T149	1		T164	3		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T27	8		T47	14		T146	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T30	1		T155	13		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	1		T13	1		T47	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	1		T5	1		T146	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T25	8		T47	17		T146	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T242	4		T270	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	5		T30	1		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T1	25		T2	3		T10	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T145	12		T37	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T3	1		T149	1		T46	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T149	1		T15	5		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T185	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T188	14		T303	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T36	12		T249	2		T43	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T39	1		T180	5		T40	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T35	8		T164	16		T55	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T85	11		T89	14		T293	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T180	3		T157	9		T182	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T250	9		T181	18		T89	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T164	4		T156	12		T157	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T146	9		T165	14		T166	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T224	15		T252	16		T304	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T36	10		T214	2		T159	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	8		T146	11		T156	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T25	8		T146	15		T292	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T270	2		T198	11		T305	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	4		T265	11		T180	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T2	21		T44	15		T29	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T145	11		T37	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T46	2		T263	6		T16	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T15	6		T153	7		T145	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T36	13		T152	15		T249	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	1		T39	4		T180	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T30	1		T35	9		T55	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T40	12		T250	10		T218	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T164	17		T180	4		T182	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T47	1		T181	19		T89	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T149	1		T164	5		T224	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	1		T166	4		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	1		T30	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	1		T13	1		T25	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T146	12		T242	1		T304	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T47	2		T146	16		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T1	2		T2	24		T5	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	8		T30	1		T265	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T241	1		T242	1		T243	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T180	16		T145	12		T257	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T35	10		T263	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T11	2		T149	1		T153	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T149	1		T46	3		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T15	10		T17	2		T161	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T172	1		T114	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T36	14		T152	13		T148	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	2		T188	12		T170	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T35	12		T55	2		T157	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T40	1		T218	23		T85	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T164	15		T182	9		T254	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	13		T181	15		T177	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T164	2		T181	8		T162	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T27	7		T166	11		T214	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T155	12		T157	12		T242	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T25	7		T146	13		T170	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T146	1		T242	3		T304	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	35		T146	18		T292	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T1	23		T12	26		T261	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	1		T37	10		T306	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T242	4		T278	15		T281	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T145	11		T188	13		T17	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T35	2		T263	6		T170	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T145	16		T42	1		T182	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T46	6		T269	13		T190	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T15	1		T107	3		T175	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T114	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T185	6		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T172	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T188	15		T303	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T36	13		T249	3		T43	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T39	4		T180	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	9		T164	17		T55	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T170	1		T218	2		T85	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T30	1		T180	4		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T250	10		T181	19		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T149	1		T164	5		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T27	1		T47	1		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T30	1		T155	1		T224	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	1		T13	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	1		T5	9		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T25	9		T47	1		T146	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T242	1		T270	3		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	8		T30	1		T265	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T1	2		T2	24		T10	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	2		T145	12		T37	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T3	1		T149	1		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	428	1			T149	1		T15	10		T153	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T172	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T188	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T36	14		T43	1		T148	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	2		T40	1		T87	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T35	12		T164	15		T55	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T170	15		T218	23		T85	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T157	10		T182	9		T254	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T181	15		T88	9		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T164	2		T157	12		T181	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T27	7		T47	13		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T155	12		T242	9		T304	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T47	19		T170	14		T214	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T146	1		T152	8		T275	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T25	7		T47	16		T146	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T242	3		T189	9		T305	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	1		T306	4		T307	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T1	23		T12	26		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T145	11		T37	10		T188	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T46	6		T263	6		T170	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T15	1		T145	16		T42	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2