Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23051

1

T1

25

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3631

1

T6

2

T11

2

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20497

1

T3

1

T4

1

T5

9

auto[1]

6185

1

T1

25

T2

24

T10

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	331	1			T149	1		T153	8		T170	7
values[0]	2	1			T303	2		-	-		-	-
values[1]	727	1			T6	1		T39	6		T180	6
values[2]	744	1			T35	21		T164	32		T55	4
values[3]	592	1			T30	1		T180	4		T151	1
values[4]	597	1			T149	1		T47	14		T164	7
values[5]	861	1			T6	1		T13	1		T27	8
values[6]	744	1			T4	1		T5	9		T25	16
values[7]	414	1			T15	9		T30	1		T265	12
values[8]	2854	1			T1	25		T2	24		T10	3
values[9]	1003	1			T3	1		T149	1		T15	11
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	772	1			T6	1		T35	21		T180	6
values[1]	693	1			T30	1		T164	32		T55	4
values[2]	594	1			T47	14		T180	4		T157	20
values[3]	704	1			T149	1		T27	8		T164	7
values[4]	774	1			T4	1		T6	1		T13	1
values[5]	651	1			T5	9		T47	37		T146	47
values[6]	2681	1			T1	25		T2	24		T10	3
values[7]	681	1			T11	2		T180	16		T145	23
values[8]	1041	1			T3	1		T149	2		T46	9
values[9]	123	1			T15	11		T150	1		T166	1
minimum	17968	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T35	13		T36	15		T249	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T180	1		T40	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T30	1		T164	16		T55	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T218	25		T88	10		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T157	11		T158	1		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T47	14		T180	1		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T149	1		T164	3		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	8		T146	14		T166	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	1		T30	1		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T13	1		T25	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T5	1		T146	2		T242	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T47	37		T146	19		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T1	25		T2	3		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T15	5		T30	1		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T41	4		T241	1		T188	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T180	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T3	1		T149	1		T46	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T149	1		T153	1		T145	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T150	1		T269	14		T161	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T15	5		T166	1		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17679	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T39	5		T224	1		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	8		T36	12		T249	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T180	5		T40	6		T85	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T164	16		T55	1		T152	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T89	14		T244	1		T293	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T157	9		T158	3		T254	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T180	3		T250	9		T181	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T164	4		T224	15		T157	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T146	9		T166	3		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T156	16		T152	10		T252	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T25	8		T165	14		T36	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T5	8		T146	11		T270	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T146	15		T158	18		T292	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T2	21		T44	15		T29	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T15	4		T265	11		T37	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T41	2		T188	12		T243	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	1		T180	15		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T46	2		T35	9		T263	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T153	7		T145	14		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T269	11		T163	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T15	6		T246	2		T308	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T39	1		T224	13		T188	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T149	1		T170	7		T301	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T153	1		T42	3		T181	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T303	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T36	15		T249	1		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	1		T39	5		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T35	13		T164	16		T55	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T170	16		T218	25		T85	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T30	1		T151	1		T157	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T180	1		T250	1		T181	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T149	1		T164	3		T157	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T47	14		T146	14		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T30	1		T155	13		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T6	1		T13	1		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	1		T5	1		T146	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T25	8		T47	37		T146	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T242	4		T229	1		T275	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	5		T30	1		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T1	25		T2	3		T10	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	1		T180	1		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	1		T46	7		T35	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T149	1		T15	5		T145	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T269	11		T163	13		T185	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T153	7		T42	1		T181	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T303	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T36	12		T249	2		T148	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T39	1		T180	5		T40	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	8		T164	16		T55	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T85	11		T89	14		T293	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T157	9		T158	3		T309	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T180	3		T250	9		T181	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T164	4		T157	15		T181	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T146	9		T271	10		T259	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T224	15		T156	12		T252	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T165	14		T166	3		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	8		T146	11		T156	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	8		T146	15		T292	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T229	13		T270	2		T198	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T15	4		T265	11		T158	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T2	21		T44	15		T29	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T180	15		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T46	2		T35	9		T263	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	6		T145	14		T182	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T35	9		T36	13		T249	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	1		T180	6		T40	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T30	1		T164	17		T55	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T218	2		T88	1		T89	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T157	10		T158	4		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T47	1		T180	4		T250	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T149	1		T164	5		T224	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	1		T146	10		T166	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	1		T30	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	1		T13	1		T25	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	9		T146	12		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T47	2		T146	16		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T1	2		T2	24		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	8		T30	1		T265	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T41	4		T241	1		T188	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	2		T180	16		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T3	1		T149	1		T46	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T149	1		T153	8		T145	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T150	1		T269	12		T161	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T15	10		T166	1		T246	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17848	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T39	4		T224	14		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T35	12		T36	14		T148	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	1		T170	15		T85	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T164	15		T55	2		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T218	23		T88	9		T293	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T157	10		T254	11		T310	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T47	13		T181	15		T182	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T164	2		T157	12		T181	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T27	7		T146	13		T166	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T155	12		T242	9		T152	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T25	7		T170	14		T159	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T146	1		T242	3		T304	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T47	35		T146	18		T292	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T1	23		T12	26		T261	35
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T15	1		T37	10		T306	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T41	2		T188	13		T242	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T145	11		T17	5		T218	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T46	6		T35	2		T263	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T145	16		T42	1		T181	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T269	13		T190	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T15	1		T221	11		T107	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T300	5		T311	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T39	2		T188	12		T220	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T149	1		T170	1		T301	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T153	8		T42	3		T181	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T303	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	13		T249	3		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	1		T39	4		T180	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T35	9		T164	17		T55	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T170	1		T218	2		T85	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T30	1		T151	1		T157	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T180	4		T250	10		T181	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T149	1		T164	5		T157	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T47	1		T146	10		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T30	1		T155	1		T224	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	1		T13	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	1		T5	9		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T25	9		T47	2		T146	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T242	1		T229	14		T275	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	8		T30	1		T265	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T1	2		T2	24		T10	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	2		T180	16		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	1		T46	3		T35	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T149	1		T15	10		T145	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T170	6		T301	16		T269	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T42	1		T181	7		T152	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T36	14		T148	7		T179	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	2		T40	1		T188	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	12		T164	15		T55	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T170	15		T218	23		T85	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T157	10		T281	8		T90	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T181	15		T182	9		T88	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T164	2		T157	12		T181	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T47	13		T146	13		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T155	12		T242	9		T290	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T27	7		T166	11		T170	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T146	1		T152	8		T304	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T25	7		T47	35		T146	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T242	3		T275	8		T189	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T15	1		T306	4		T307	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T1	23		T12	26		T261	35
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T145	11		T37	10		T218	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T46	6		T35	2		T263	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T15	1		T145	16		T182	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2