Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23508

1

T1

25

T2

24

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3174

1

T5

9

T6

1

T149

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20594

1

T3

1

T4

1

T7

14

auto[1]

6088

1

T1

25

T2

24

T5

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	303	1			T263	13		T169	1		T218	8
values[0]	2	1			T30	1		T312	1		-	-
values[1]	694	1			T13	1		T35	21		T154	1
values[2]	775	1			T3	1		T149	1		T30	1
values[3]	790	1			T4	1		T47	31		T164	32
values[4]	2736	1			T1	25		T2	24		T6	2
values[5]	713	1			T11	2		T149	1		T47	20
values[6]	696	1			T149	1		T15	9		T40	13
values[7]	592	1			T30	1		T150	1		T250	9
values[8]	642	1			T15	11		T25	16		T55	4
values[9]	926	1			T5	9		T27	8		T39	6
minimum	17813	1			T7	14		T8	231		T9	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	659	1			T265	12		T154	1		T146	13
values[1]	930	1			T3	1		T149	1		T30	1
values[2]	617	1			T4	1		T6	1		T47	17
values[3]	2723	1			T1	25		T2	24		T6	1
values[4]	781	1			T149	1		T40	13		T165	15
values[5]	632	1			T149	1		T15	9		T30	1
values[6]	602	1			T145	23		T150	1		T224	14
values[7]	692	1			T15	11		T25	16		T27	8
values[8]	851	1			T5	9		T39	6		T153	8
values[9]	157	1			T155	13		T263	13		T287	1
minimum	18038	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T265	1		T154	1		T214	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T146	2		T188	14		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	1		T149	1		T35	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T30	1		T47	14		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	1		T6	1		T164	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T47	17		T180	1		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T1	25		T2	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T46	7		T146	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T40	7		T16	2		T170	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T149	1		T165	1		T170	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T149	1		T30	1		T41	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	5		T182	10		T254	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T145	12		T224	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T150	1		T250	1		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T25	8		T27	8		T181	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	5		T55	3		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T39	5		T169	1		T257	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T5	1		T153	1		T180	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T155	13		T263	7		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T18	1		T288	1		T207	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17726	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T30	1		T35	13		T147	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T265	11		T214	2		T271	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T146	11		T188	12		T250	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T35	9		T166	3		T37	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T180	5		T145	14		T156	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T164	16		T188	14		T181	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T180	15		T157	15		T251	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T2	21		T11	1		T44	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T46	2		T146	9		T36	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	6		T16	6		T152	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T165	14		T266	14		T270	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T41	2		T86	6		T292	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	4		T182	9		T254	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T145	11		T224	13		T158	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T250	8		T243	3		T85	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T25	8		T181	18		T271	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	6		T55	1		T224	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	1		T51	5		T89	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	8		T153	7		T180	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T263	6		T89	14		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T18	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T35	8		T304	7		T110	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T263	7		T169	1		T218	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T288	1		T207	1		T313	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T312	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T30	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	1		T154	1		T146	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T35	13		T146	2		T188	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	1		T149	1		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T30	1		T180	1		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	1		T164	16		T181	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T47	31		T180	1		T145	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1535	1			T1	25		T2	3		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T6	1		T46	7		T146	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	1		T47	20		T170	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T149	1		T17	7		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T149	1		T40	7		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	5		T165	1		T170	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	1		T152	9		T159	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T150	1		T250	1		T85	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T25	8		T145	12		T224	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T15	5		T55	3		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T27	8		T39	5		T155	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	1		T153	1		T180	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17656	1			T7	14		T8	229		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T263	6		T89	14		T177	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T305	12		T314	9		T237	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T146	15		T271	9		T260	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T35	8		T146	11		T188	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T265	11		T35	9		T166	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T180	5		T250	9		T181	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T164	16		T181	6		T270	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T180	15		T145	14		T156	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T2	21		T44	15		T29	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T46	2		T146	9		T36	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	1		T152	14		T249	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	4		T266	14		T289	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	6		T41	2		T16	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	4		T165	14		T182	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T152	10		T159	12		T293	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T250	8		T85	12		T244	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	8		T145	11		T224	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	6		T55	1		T243	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T39	1		T51	5		T89	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	8		T153	7		T180	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T265	12		T154	1		T214	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T146	12		T188	13		T250	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	1		T149	1		T35	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T30	1		T47	1		T180	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	1		T6	1		T164	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T47	1		T180	16		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T1	2		T2	24		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	1		T46	3		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T40	12		T16	8		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T149	1		T165	15		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T149	1		T30	1		T41	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	8		T182	10		T254	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	12		T224	14		T158	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T150	1		T250	9		T243	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T25	9		T27	1		T181	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	10		T55	2		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T39	4		T169	1		T257	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	9		T153	8		T180	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T155	1		T263	7		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T18	7		T288	1		T207	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17861	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T30	1		T35	9		T147	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T214	9		T260	7		T276	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T146	1		T188	13		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T35	2		T166	11		T37	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T47	13		T145	16		T181	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T164	15		T188	12		T181	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T47	16		T157	12		T242	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T1	23		T12	26		T47	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T46	6		T146	13		T36	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	1		T170	6		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T170	14		T220	6		T189	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T41	2		T292	4		T277	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	1		T182	9		T254	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T145	11		T152	8		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T85	10		T294	12		T295	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T25	7		T27	7		T181	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T15	1		T55	2		T260	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T39	2		T218	7		T51	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T157	10		T242	9		T152	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T155	12		T263	6		T177	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T146	18		T242	4		T218	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T35	12		T147	1		T301	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T263	7		T169	1		T218	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T288	1		T207	1		T313	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T312	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T30	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	1		T154	1		T146	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T35	9		T146	12		T188	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	1		T149	1		T265	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T30	1		T180	6		T250	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	1		T164	17		T181	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T47	2		T180	16		T145	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	2		T2	24		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	1		T46	3		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	2		T47	1		T170	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T149	1		T17	6		T266	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T149	1		T40	12		T41	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	8		T165	15		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T30	1		T152	11		T159	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T150	1		T250	9		T85	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T25	9		T145	12		T224	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	10		T55	2		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T27	1		T39	4		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	9		T153	8		T180	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T7	14		T8	231		T9	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T263	6		T218	7		T177	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T313	8		T305	12		T221	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T146	18		T242	4		T218	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T35	12		T146	1		T188	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T35	2		T166	11		T37	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T181	7		T182	11		T159	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T164	15		T181	8		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T47	29		T145	16		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T1	23		T12	26		T164	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T46	6		T146	13		T36	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T47	19		T170	21		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T17	5		T220	16		T281	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T40	1		T41	2		T292	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	1		T170	14		T182	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T152	8		T159	9		T293	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T85	10		T297	10		T23	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T25	7		T145	11		T181	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T15	1		T55	2		T260	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T27	7		T39	2		T155	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T157	10		T242	9		T152	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2