Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23046

1

T1

25

T2

24

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

3636

1

T3

1

T4

1

T5

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20459

1

T3

1

T5

9

T6

1

auto[1]

6223

1

T1

25

T2

24

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	469	1			T8	3		T9	3		T15	10
values[0]	103	1			T267	16		T284	10		T315	10
values[1]	477	1			T6	1		T15	9		T30	1
values[2]	2964	1			T1	25		T2	24		T4	1
values[3]	741	1			T5	9		T6	1		T154	1
values[4]	487	1			T155	13		T146	57		T16	8
values[5]	790	1			T35	12		T153	8		T224	30
values[6]	717	1			T3	1		T27	8		T46	9
values[7]	681	1			T265	12		T47	20		T35	21
values[8]	779	1			T13	1		T25	16		T30	1
values[9]	1095	1			T11	2		T149	3		T15	11
minimum	17379	1			T7	14		T8	228		T9	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	745	1			T6	1		T15	9		T30	1
values[1]	3037	1			T1	25		T2	24		T4	1
values[2]	611	1			T6	1		T154	1		T146	34
values[3]	559	1			T35	12		T155	13		T146	23
values[4]	834	1			T46	9		T153	8		T145	31
values[5]	628	1			T3	1		T27	8		T47	20
values[6]	614	1			T25	16		T30	1		T265	12
values[7]	887	1			T13	1		T165	15		T36	27
values[8]	744	1			T11	2		T149	2		T15	11
values[9]	190	1			T149	1		T17	2		T218	8
minimum	17833	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	1		T30	1		T164	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T15	5		T47	31		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T1	25		T2	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T4	1		T5	1		T40	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	1		T154	1		T146	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	2		T37	11		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T257	1		T156	1		T157	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T35	3		T155	13		T146	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T46	7		T224	1		T181	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T153	1		T145	17		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T27	8		T47	20		T152	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T151	1		T242	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T30	1		T35	13		T180	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T25	8		T265	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T165	1		T170	15		T158	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T13	1		T36	15		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T149	2		T15	5		T55	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	1		T30	1		T39	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T149	1		T17	2		T218	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T260	6		T304	11		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17672	1			T7	14		T8	229		T9	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T164	20		T180	3		T166	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	4		T180	5		T263	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T2	21		T44	15		T29	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	8		T40	6		T269	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T146	15		T188	14		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T16	6		T37	13		T89	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T156	12		T157	9		T179	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	9		T146	9		T224	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T46	2		T224	15		T181	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T153	7		T145	14		T156	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T152	14		T229	13		T309	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T177	10		T205	4		T173	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	8		T180	15		T271	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T25	8		T265	11		T188	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T165	14		T158	8		T85	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T36	12		T152	10		T159	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	6		T55	1		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	1		T39	1		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T45	2		T187	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T260	6		T304	14		T316	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	2		T15	9		T35	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	435	1			T8	3		T9	3		T15	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T304	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T267	16		T315	5		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T284	10		T317	13		T318	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T6	1		T30	1		T164	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T15	5		T47	14		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T1	25		T2	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	1		T47	17		T40	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	1		T154	1		T188	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	1		T37	11		T181	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T146	19		T156	1		T157	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T155	13		T146	14		T16	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T224	1		T257	1		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T35	3		T153	1		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T27	8		T46	7		T152	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	1		T145	17		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T47	20		T35	13		T180	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T265	1		T169	1		T243	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T30	1		T165	1		T170	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	1		T25	8		T242	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T149	3		T15	5		T55	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T11	1		T30	1		T39	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17222	1			T7	14		T8	226		T9	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T250	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T304	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T315	5		T174	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T317	7		T318	16		T319	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T164	20		T180	3		T166	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	4		T180	5		T263	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T2	21		T44	15		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T40	6		T85	11		T89	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T188	14		T182	8		T43	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	8		T37	13		T181	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T146	15		T156	12		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T146	9		T16	6		T243	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T224	15		T270	12		T304	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T35	9		T153	7		T224	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	2		T152	21		T18	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T145	14		T156	4		T188	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T35	8		T180	15		T271	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T265	11		T243	2		T214	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T165	14		T271	10		T160	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T25	8		T159	12		T292	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T15	6		T55	1		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T11	1		T39	1		T145	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	1		T30	1		T164	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T15	8		T47	2		T180	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T1	2		T2	24		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	1		T5	9		T40	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	1		T154	1		T146	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	8		T37	14		T89	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T257	1		T156	13		T157	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T35	10		T155	1		T146	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T46	3		T224	16		T181	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T153	8		T145	15		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T27	1		T47	1		T152	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T151	1		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	1		T35	9		T180	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T25	9		T265	12		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T165	15		T170	1		T158	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T13	1		T36	13		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T149	2		T15	10		T55	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	2		T30	1		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T149	1		T17	2		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T260	7		T304	15		T316	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17819	1			T7	14		T8	231		T9	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T164	17		T166	11		T182	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	1		T47	29		T263	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T1	23		T12	26		T261	35
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T40	1		T88	9		T301	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T146	18		T188	12		T43	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T37	10		T259	10		T110	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T157	10		T179	15		T304	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T35	2		T155	12		T146	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T46	6		T181	15		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T145	16		T42	1		T242	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T27	7		T47	19		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T242	4		T177	11		T205	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T35	12		T170	6		T244	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T25	7		T188	13		T214	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T170	14		T85	7		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T36	14		T242	3		T152	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	1		T55	2		T146	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T39	2		T145	11		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T218	7		T297	18		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T260	5		T304	10		T320	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T321	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	444	1			T8	3		T9	3		T15	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T304	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T267	1		T315	6		T174	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T284	1		T317	8		T318	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T30	1		T164	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	8		T47	1		T180	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T1	2		T2	24		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	1		T47	1		T40	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	1		T154	1		T188	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	9		T37	14		T181	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	16		T156	13		T157	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T155	1		T146	10		T16	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T224	16		T257	1		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T35	10		T153	8		T224	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T27	1		T46	3		T152	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T145	15		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T47	1		T35	9		T180	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T265	12		T169	1		T243	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T30	1		T165	15		T170	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	1		T25	9		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T149	3		T15	10		T55	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T11	2		T30	1		T39	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17379	1			T7	14		T8	228		T9	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T304	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T267	15		T315	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T284	9		T317	12		T319	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T164	17		T166	11		T276	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T15	1		T47	13		T263	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T1	23		T12	26		T261	35
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	16		T40	1		T218	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T188	12		T182	11		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	10		T181	7		T301	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T146	18		T157	10		T181	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T155	12		T146	13		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T304	1		T281	8		T280	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	2		T42	1		T17	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T27	7		T46	6		T152	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T145	16		T188	13		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T47	19		T35	12		T244	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T214	9		T147	1		T177	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T170	20		T253	10		T110	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T25	7		T242	3		T218	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	1		T55	2		T146	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T39	2		T145	11		T41	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2