Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26682

1

T1

25

T2

24

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23046

1

T1

25

T2

24

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3636

1

T3

1

T5

9

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20604

1

T3

1

T6

1

T7

14

auto[1]

6078

1

T1

25

T2

24

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

25

T2

3

T3

1

auto[1]

3982

1

T2

21

T5

8

T8

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	597	1			T8	3		T9	3		T11	2
values[0]	26	1			T267	16		T315	10		-	-
values[1]	584	1			T6	1		T15	9		T30	1
values[2]	2966	1			T1	25		T2	24		T4	1
values[3]	664	1			T5	9		T6	1		T154	1
values[4]	496	1			T155	13		T146	57		T16	8
values[5]	864	1			T35	12		T153	8		T224	30
values[6]	608	1			T3	1		T27	8		T46	9
values[7]	772	1			T25	16		T265	12		T47	20
values[8]	750	1			T13	1		T30	1		T165	15
values[9]	976	1			T149	3		T15	11		T30	1
minimum	17379	1			T7	14		T8	228		T9	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	555	1			T6	1		T15	9		T30	1
values[1]	3001	1			T1	25		T2	24		T4	1
values[2]	635	1			T6	1		T154	1		T146	34
values[3]	592	1			T35	12		T155	13		T146	23
values[4]	839	1			T46	9		T153	8		T145	31
values[5]	635	1			T3	1		T27	8		T180	16
values[6]	621	1			T25	16		T30	1		T265	12
values[7]	847	1			T13	1		T165	15		T36	27
values[8]	797	1			T11	2		T149	3		T15	11
values[9]	148	1			T36	11		T218	8		T246	11
minimum	18012	1			T7	14		T8	231		T9	120

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

4041

1

T1

23

T12

26

T15

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	1		T164	16		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	5		T30	1		T47	31
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T1	25		T2	3		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T5	1		T40	7		T181	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T216	1		T43	4		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	1		T154	1		T146	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T146	14		T16	2		T257	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T35	3		T155	13		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T46	7		T153	1		T145	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T224	1		T156	1		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T27	8		T180	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T242	5		T152	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T25	8		T30	1		T47	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T265	1		T35	13		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T165	1		T36	15		T170	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T169	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T149	3		T15	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T39	5		T55	3		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T36	1		T246	9		T322	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T218	8		T316	1		T320	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17702	1			T7	14		T8	229		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T166	12		T101	3		T317	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T164	16		T182	9		T244	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T15	4		T180	5		T263	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T2	21		T44	15		T29	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	8		T40	6		T181	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	2		T89	11		T260	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T146	15		T37	13		T188	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T146	9		T16	6		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T35	9		T224	13		T243	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T46	2		T153	7		T145	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T224	15		T156	4		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T180	15		T177	10		T161	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T152	14		T86	6		T177	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T25	8		T271	2		T160	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T265	11		T35	8		T188	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T165	14		T36	12		T158	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T158	3		T159	12		T251	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	1		T15	6		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T39	1		T55	1		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T36	10		T246	2		T187	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T316	17		T320	7		T104	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	2		T15	9		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T166	3		T101	1		T317	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	475	1			T8	3		T9	3		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T55	3		T145	12		T41	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T267	16		T315	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	1		T164	19		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	5		T30	1		T47	31
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T1	25		T2	3		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T40	7		T181	9		T218	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T216	1		T43	4		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T6	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T146	14		T16	2		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T155	13		T146	19		T37	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T153	1		T257	1		T181	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T35	3		T224	2		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	8		T46	7		T145	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T156	1		T242	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T25	8		T47	20		T180	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T265	1		T35	13		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	1		T165	1		T170	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	1		T218	17		T159	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T149	3		T15	5		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T39	5		T151	1		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17222	1			T7	14		T8	226		T9	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T11	1		T146	11		T250	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T55	1		T145	11		T41	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T315	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T164	20		T180	3		T244	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	4		T180	5		T166	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T2	21		T44	15		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	6		T181	6		T85	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T43	2		T89	11		T260	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	8		T188	14		T181	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T146	9		T16	6		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T146	15		T37	13		T243	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T153	7		T181	18		T293	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T35	9		T224	28		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T46	2		T145	14		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T156	4		T152	14		T18	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T25	8		T180	15		T177	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T265	11		T35	8		T188	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T165	14		T271	10		T292	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T159	12		T245	10		T266	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	6		T36	22		T250	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T39	1		T158	16		T45	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T15	9		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	1		T164	17		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	8		T30	1		T47	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T1	2		T2	24		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	9		T40	12		T181	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T216	1		T43	5		T89	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T154	1		T146	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T146	10		T16	8		T257	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T35	10		T155	1		T224	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T46	3		T153	8		T145	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T224	16		T156	5		T42	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T27	1		T180	16		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	1		T242	1		T152	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T25	9		T30	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T265	12		T35	9		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T165	15		T36	13		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T169	1		T158	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	2		T149	3		T15	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T39	4		T55	2		T145	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T36	11		T246	3		T322	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T218	1		T316	18		T320	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17890	1			T7	14		T8	231		T9	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T166	4		T101	3		T317	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T164	15		T182	9		T276	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T15	1		T47	29		T263	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T1	23		T12	26		T261	35
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T40	1		T181	8		T182	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T43	1		T260	10		T259	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T146	18		T37	10		T188	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T146	13		T157	10		T159	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T35	2		T155	12		T17	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T46	6		T145	16		T181	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T42	1		T242	9		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T27	7		T87	12		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T242	4		T152	13		T177	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T25	7		T47	19		T170	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T35	12		T188	13		T214	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	14		T170	14		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T218	16		T159	9		T251	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	1		T146	1		T85	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T39	2		T55	2		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T246	8		T194	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T218	7		T320	2		T297	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T164	2		T267	15		T184	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T166	11		T101	1		T317	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	478	1			T8	3		T9	3		T11	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T55	2		T145	12		T41	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T267	1		T315	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	1		T164	22		T180	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	8		T30	1		T47	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T1	2		T2	24		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	12		T181	7		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T216	1		T43	5		T89	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	9		T6	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T146	10		T16	8		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T155	1		T146	16		T37	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	8		T257	1		T181	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T35	10		T224	30		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T27	1		T46	3		T145	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	1		T156	5		T242	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T25	9		T47	1		T180	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T265	12		T35	9		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T30	1		T165	15		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	1		T218	1		T159	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T149	3		T15	10		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T39	4		T151	1		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17379	1			T7	14		T8	228		T9	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T146	1		T104	10		T268	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T55	2		T145	11		T41	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T267	15		T315	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T164	17		T276	17		T267	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	1		T47	29		T166	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T1	23		T12	26		T261	35
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	1		T181	8		T218	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T43	1		T260	10		T259	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T188	12		T181	7		T182	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T146	13		T157	10		T85	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T155	12		T146	18		T37	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T181	15		T159	8		T293	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T35	2		T42	1		T17	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T27	7		T46	6		T145	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T242	13		T152	13		T177	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T25	7		T47	19		T170	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T35	12		T188	13		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T170	14		T242	3		T292	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T218	16		T159	9		T245	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	1		T36	14		T152	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T39	2		T170	15		T218	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22641

1

T1

2

T2

24

T3

1

auto[1]

auto[0]

4041

1

T1

23

T12

26

T15

2