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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.19


Total test records in report: 919
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T798 /workspace/coverage/default/33.adc_ctrl_filters_polled.1297030506 Aug 02 05:24:00 PM PDT 24 Aug 02 05:29:58 PM PDT 24 484185636304 ps
T799 /workspace/coverage/default/26.adc_ctrl_stress_all.1638416247 Aug 02 05:23:31 PM PDT 24 Aug 02 05:49:14 PM PDT 24 385419300389 ps
T800 /workspace/coverage/default/18.adc_ctrl_alert_test.523704786 Aug 02 05:23:11 PM PDT 24 Aug 02 05:23:11 PM PDT 24 335276597 ps
T801 /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2970345451 Aug 02 05:22:50 PM PDT 24 Aug 02 05:25:51 PM PDT 24 328639691923 ps
T60 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.867627627 Aug 02 05:21:51 PM PDT 24 Aug 02 05:21:52 PM PDT 24 420774285 ps
T91 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2594563076 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:36 PM PDT 24 438288280 ps
T124 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3285563404 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:28 PM PDT 24 718851144 ps
T802 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.404716626 Aug 02 05:21:57 PM PDT 24 Aug 02 05:21:58 PM PDT 24 488937832 ps
T56 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3053724158 Aug 02 05:21:30 PM PDT 24 Aug 02 05:21:37 PM PDT 24 7650425331 ps
T803 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3236329825 Aug 02 05:22:03 PM PDT 24 Aug 02 05:22:04 PM PDT 24 499005773 ps
T804 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2247935557 Aug 02 05:22:00 PM PDT 24 Aug 02 05:22:02 PM PDT 24 496464503 ps
T65 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.240201818 Aug 02 05:21:41 PM PDT 24 Aug 02 05:21:43 PM PDT 24 348161399 ps
T805 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3068718801 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:35 PM PDT 24 398325958 ps
T92 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3148112131 Aug 02 05:21:41 PM PDT 24 Aug 02 05:21:43 PM PDT 24 599011411 ps
T52 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.417097922 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:54 PM PDT 24 4705430710 ps
T806 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2859515757 Aug 02 05:21:43 PM PDT 24 Aug 02 05:21:44 PM PDT 24 455937032 ps
T57 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1874321477 Aug 02 05:21:54 PM PDT 24 Aug 02 05:21:58 PM PDT 24 4873025471 ps
T807 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1897473022 Aug 02 05:22:00 PM PDT 24 Aug 02 05:22:01 PM PDT 24 365628622 ps
T808 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2082791250 Aug 02 05:21:53 PM PDT 24 Aug 02 05:21:54 PM PDT 24 326051190 ps
T68 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3495642066 Aug 02 05:21:42 PM PDT 24 Aug 02 05:21:44 PM PDT 24 562177426 ps
T75 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2017311009 Aug 02 05:21:42 PM PDT 24 Aug 02 05:21:43 PM PDT 24 809096837 ps
T809 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.309349597 Aug 02 05:21:56 PM PDT 24 Aug 02 05:21:57 PM PDT 24 363292045 ps
T58 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3749041494 Aug 02 05:21:44 PM PDT 24 Aug 02 05:21:51 PM PDT 24 4511662093 ps
T138 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2803930000 Aug 02 05:21:44 PM PDT 24 Aug 02 05:21:45 PM PDT 24 416836697 ps
T74 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3480884819 Aug 02 05:21:53 PM PDT 24 Aug 02 05:21:55 PM PDT 24 537648826 ps
T139 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1973068979 Aug 02 05:21:50 PM PDT 24 Aug 02 05:21:54 PM PDT 24 2357826981 ps
T810 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.258980490 Aug 02 05:21:58 PM PDT 24 Aug 02 05:21:59 PM PDT 24 327919162 ps
T811 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3026595559 Aug 02 05:21:57 PM PDT 24 Aug 02 05:21:58 PM PDT 24 517084127 ps
T61 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1563290659 Aug 02 05:21:51 PM PDT 24 Aug 02 05:21:55 PM PDT 24 4637100543 ps
T812 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.855331479 Aug 02 05:21:58 PM PDT 24 Aug 02 05:22:00 PM PDT 24 385345184 ps
T140 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1867469123 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:36 PM PDT 24 359075527 ps
T71 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3710637895 Aug 02 05:21:38 PM PDT 24 Aug 02 05:21:40 PM PDT 24 368039461 ps
T125 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3000423151 Aug 02 05:21:50 PM PDT 24 Aug 02 05:21:51 PM PDT 24 720335606 ps
T66 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.403981293 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:30 PM PDT 24 468241952 ps
T53 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2943438874 Aug 02 05:21:43 PM PDT 24 Aug 02 05:21:54 PM PDT 24 2698192769 ps
T813 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3776673972 Aug 02 05:21:57 PM PDT 24 Aug 02 05:21:58 PM PDT 24 480178547 ps
T54 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.579324890 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:41 PM PDT 24 3390793409 ps
T72 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1030823940 Aug 02 05:21:42 PM PDT 24 Aug 02 05:22:01 PM PDT 24 8442283664 ps
T141 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3724641626 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:42 PM PDT 24 2371726872 ps
T142 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3838478473 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:36 PM PDT 24 2588405584 ps
T143 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4247386949 Aug 02 05:21:40 PM PDT 24 Aug 02 05:21:42 PM PDT 24 326422439 ps
T67 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3604565020 Aug 02 05:21:28 PM PDT 24 Aug 02 05:21:31 PM PDT 24 394960288 ps
T814 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4266226752 Aug 02 05:21:58 PM PDT 24 Aug 02 05:22:00 PM PDT 24 344548099 ps
T73 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.924686038 Aug 02 05:21:28 PM PDT 24 Aug 02 05:21:32 PM PDT 24 645705571 ps
T815 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4198705552 Aug 02 05:21:42 PM PDT 24 Aug 02 05:21:43 PM PDT 24 425199577 ps
T144 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1022583935 Aug 02 05:21:40 PM PDT 24 Aug 02 05:21:45 PM PDT 24 3866313917 ps
T77 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2822584571 Aug 02 05:21:33 PM PDT 24 Aug 02 05:21:39 PM PDT 24 4404830024 ps
T70 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1084299464 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:36 PM PDT 24 394584966 ps
T76 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.243726330 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:34 PM PDT 24 590525751 ps
T816 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2443997098 Aug 02 05:21:51 PM PDT 24 Aug 02 05:21:57 PM PDT 24 4216216699 ps
T817 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1643243196 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:29 PM PDT 24 674646974 ps
T126 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2884360479 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:35 PM PDT 24 849825511 ps
T818 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3869573568 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:35 PM PDT 24 4018749681 ps
T819 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.262023934 Aug 02 05:21:53 PM PDT 24 Aug 02 05:21:54 PM PDT 24 507271005 ps
T820 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.670530520 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:42 PM PDT 24 4379021119 ps
T821 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.313091892 Aug 02 05:21:59 PM PDT 24 Aug 02 05:22:00 PM PDT 24 466678343 ps
T822 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2920832151 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:41 PM PDT 24 435326356 ps
T823 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1208741231 Aug 02 05:21:31 PM PDT 24 Aug 02 05:21:32 PM PDT 24 315757200 ps
T127 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4247081210 Aug 02 05:21:54 PM PDT 24 Aug 02 05:21:55 PM PDT 24 335523941 ps
T128 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2889615125 Aug 02 05:21:30 PM PDT 24 Aug 02 05:21:32 PM PDT 24 413195864 ps
T824 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1758484788 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:45 PM PDT 24 5104000554 ps
T825 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2702158184 Aug 02 05:21:28 PM PDT 24 Aug 02 05:21:32 PM PDT 24 593149881 ps
T826 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3257634427 Aug 02 05:21:51 PM PDT 24 Aug 02 05:21:52 PM PDT 24 529043558 ps
T827 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1650020462 Aug 02 05:21:58 PM PDT 24 Aug 02 05:21:59 PM PDT 24 353220452 ps
T357 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1782220156 Aug 02 05:21:38 PM PDT 24 Aug 02 05:22:02 PM PDT 24 9321865159 ps
T358 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1955815447 Aug 02 05:21:51 PM PDT 24 Aug 02 05:22:04 PM PDT 24 8782387557 ps
T828 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1535624613 Aug 02 05:21:52 PM PDT 24 Aug 02 05:21:53 PM PDT 24 535683547 ps
T829 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3294752521 Aug 02 05:22:00 PM PDT 24 Aug 02 05:22:01 PM PDT 24 410599739 ps
T830 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4071446649 Aug 02 05:21:45 PM PDT 24 Aug 02 05:21:46 PM PDT 24 526236586 ps
T831 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1272131976 Aug 02 05:21:33 PM PDT 24 Aug 02 05:21:53 PM PDT 24 8079131090 ps
T129 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.931179981 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:40 PM PDT 24 352940547 ps
T832 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2700996381 Aug 02 05:21:59 PM PDT 24 Aug 02 05:22:00 PM PDT 24 349544872 ps
T833 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2985490666 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:41 PM PDT 24 363607653 ps
T834 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2122472154 Aug 02 05:21:25 PM PDT 24 Aug 02 05:21:27 PM PDT 24 571414604 ps
T835 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2041516979 Aug 02 05:21:51 PM PDT 24 Aug 02 05:22:01 PM PDT 24 5310034604 ps
T836 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.429803500 Aug 02 05:21:58 PM PDT 24 Aug 02 05:21:59 PM PDT 24 357841004 ps
T837 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.657802424 Aug 02 05:21:57 PM PDT 24 Aug 02 05:21:59 PM PDT 24 412124534 ps
T838 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2726040285 Aug 02 05:21:33 PM PDT 24 Aug 02 05:21:34 PM PDT 24 522544777 ps
T839 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.887662907 Aug 02 05:21:57 PM PDT 24 Aug 02 05:21:58 PM PDT 24 311859180 ps
T840 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3877548104 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:33 PM PDT 24 467744866 ps
T841 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3660926537 Aug 02 05:21:56 PM PDT 24 Aug 02 05:21:58 PM PDT 24 498214547 ps
T130 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.162189104 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:35 PM PDT 24 456199059 ps
T842 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.847745520 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:42 PM PDT 24 366991601 ps
T843 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2153793973 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:34 PM PDT 24 828380774 ps
T844 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2603813101 Aug 02 05:21:42 PM PDT 24 Aug 02 05:21:44 PM PDT 24 2773047818 ps
T845 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1868442923 Aug 02 05:21:52 PM PDT 24 Aug 02 05:21:53 PM PDT 24 404694995 ps
T131 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2090769207 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:56 PM PDT 24 26477418425 ps
T846 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2020807550 Aug 02 05:22:04 PM PDT 24 Aug 02 05:22:05 PM PDT 24 553491171 ps
T847 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4058212738 Aug 02 05:21:36 PM PDT 24 Aug 02 05:21:40 PM PDT 24 2235216655 ps
T848 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3556450435 Aug 02 05:21:41 PM PDT 24 Aug 02 05:21:44 PM PDT 24 450517577 ps
T849 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2099854682 Aug 02 05:21:42 PM PDT 24 Aug 02 05:21:55 PM PDT 24 4146385987 ps
T132 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.877230598 Aug 02 05:21:28 PM PDT 24 Aug 02 05:21:31 PM PDT 24 1321712649 ps
T133 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1388000982 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:34 PM PDT 24 352429446 ps
T850 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.778367486 Aug 02 05:21:44 PM PDT 24 Aug 02 05:21:46 PM PDT 24 503782033 ps
T851 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2605384649 Aug 02 05:21:50 PM PDT 24 Aug 02 05:21:53 PM PDT 24 680082376 ps
T852 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4175009196 Aug 02 05:21:51 PM PDT 24 Aug 02 05:21:53 PM PDT 24 461068830 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1306829079 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:29 PM PDT 24 371298859 ps
T854 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3685418918 Aug 02 05:21:52 PM PDT 24 Aug 02 05:21:54 PM PDT 24 508056614 ps
T855 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2991548399 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:36 PM PDT 24 530766444 ps
T856 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3989536372 Aug 02 05:21:50 PM PDT 24 Aug 02 05:21:52 PM PDT 24 1154112600 ps
T857 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1360288364 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:47 PM PDT 24 8508342000 ps
T858 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.230080091 Aug 02 05:21:26 PM PDT 24 Aug 02 05:21:27 PM PDT 24 326352732 ps
T134 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1035876177 Aug 02 05:21:31 PM PDT 24 Aug 02 05:21:51 PM PDT 24 28760171808 ps
T859 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3891257965 Aug 02 05:21:50 PM PDT 24 Aug 02 05:21:51 PM PDT 24 355111484 ps
T860 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.904900438 Aug 02 05:21:57 PM PDT 24 Aug 02 05:21:58 PM PDT 24 443328293 ps
T861 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1458260773 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:28 PM PDT 24 423759085 ps
T862 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3967951331 Aug 02 05:21:33 PM PDT 24 Aug 02 05:21:35 PM PDT 24 352931908 ps
T135 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.748264817 Aug 02 05:21:26 PM PDT 24 Aug 02 05:21:29 PM PDT 24 444618560 ps
T863 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.500183790 Aug 02 05:21:52 PM PDT 24 Aug 02 05:21:53 PM PDT 24 512484558 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1841983728 Aug 02 05:22:01 PM PDT 24 Aug 02 05:22:05 PM PDT 24 4383281517 ps
T865 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4142219371 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:36 PM PDT 24 1033449044 ps
T866 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2737367481 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:36 PM PDT 24 2418409350 ps
T867 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1722552100 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:45 PM PDT 24 8603339059 ps
T868 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2920074546 Aug 02 05:21:29 PM PDT 24 Aug 02 05:21:36 PM PDT 24 1142178286 ps
T869 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2048357157 Aug 02 05:21:52 PM PDT 24 Aug 02 05:21:55 PM PDT 24 495728517 ps
T870 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3941149786 Aug 02 05:21:56 PM PDT 24 Aug 02 05:21:58 PM PDT 24 301863025 ps
T871 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.196787204 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:29 PM PDT 24 442608495 ps
T872 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1922070176 Aug 02 05:21:40 PM PDT 24 Aug 02 05:21:42 PM PDT 24 394224186 ps
T137 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4107616413 Aug 02 05:21:35 PM PDT 24 Aug 02 05:21:36 PM PDT 24 421567394 ps
T873 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4730253 Aug 02 05:21:33 PM PDT 24 Aug 02 05:22:58 PM PDT 24 26378239409 ps
T136 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.146911814 Aug 02 05:21:55 PM PDT 24 Aug 02 05:21:59 PM PDT 24 1103567444 ps
T874 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3582385088 Aug 02 05:21:50 PM PDT 24 Aug 02 05:21:54 PM PDT 24 4912707066 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1479941663 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:36 PM PDT 24 411363280 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1625405086 Aug 02 05:21:26 PM PDT 24 Aug 02 05:21:28 PM PDT 24 1121752335 ps
T877 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.882112194 Aug 02 05:22:00 PM PDT 24 Aug 02 05:22:02 PM PDT 24 295190331 ps
T878 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2971352248 Aug 02 05:21:56 PM PDT 24 Aug 02 05:21:58 PM PDT 24 489568900 ps
T879 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2068860873 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:37 PM PDT 24 2391471321 ps
T356 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1247492553 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:38 PM PDT 24 3986221788 ps
T880 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1289440233 Aug 02 05:22:00 PM PDT 24 Aug 02 05:22:02 PM PDT 24 326063749 ps
T881 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2905093976 Aug 02 05:21:33 PM PDT 24 Aug 02 05:21:34 PM PDT 24 365167415 ps
T882 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4229477584 Aug 02 05:22:03 PM PDT 24 Aug 02 05:22:05 PM PDT 24 507512096 ps
T883 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3030078492 Aug 02 05:21:29 PM PDT 24 Aug 02 05:21:30 PM PDT 24 375431915 ps
T884 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3106878902 Aug 02 05:21:57 PM PDT 24 Aug 02 05:21:59 PM PDT 24 440265585 ps
T885 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.696354372 Aug 02 05:21:49 PM PDT 24 Aug 02 05:21:49 PM PDT 24 460466631 ps
T886 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1211480025 Aug 02 05:21:29 PM PDT 24 Aug 02 05:21:51 PM PDT 24 31905510302 ps
T887 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1175005400 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:37 PM PDT 24 8948264075 ps
T888 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.237322106 Aug 02 05:21:52 PM PDT 24 Aug 02 05:21:53 PM PDT 24 417207788 ps
T889 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1288165123 Aug 02 05:21:59 PM PDT 24 Aug 02 05:22:00 PM PDT 24 343181415 ps
T890 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3010421071 Aug 02 05:21:58 PM PDT 24 Aug 02 05:22:00 PM PDT 24 327915906 ps
T891 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2524698733 Aug 02 05:21:51 PM PDT 24 Aug 02 05:21:53 PM PDT 24 2704462266 ps
T892 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3949361603 Aug 02 05:21:41 PM PDT 24 Aug 02 05:21:42 PM PDT 24 315798211 ps
T893 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3434323242 Aug 02 05:21:27 PM PDT 24 Aug 02 05:21:28 PM PDT 24 453932081 ps
T894 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2525305106 Aug 02 05:21:51 PM PDT 24 Aug 02 05:21:55 PM PDT 24 4961690547 ps
T895 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2531654201 Aug 02 05:21:59 PM PDT 24 Aug 02 05:22:01 PM PDT 24 432284009 ps
T896 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3664390983 Aug 02 05:21:33 PM PDT 24 Aug 02 05:21:40 PM PDT 24 4596811567 ps
T897 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.970573006 Aug 02 05:21:34 PM PDT 24 Aug 02 05:21:38 PM PDT 24 951673384 ps
T898 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2499011499 Aug 02 05:21:50 PM PDT 24 Aug 02 05:22:00 PM PDT 24 4127063651 ps
T899 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1137223525 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:41 PM PDT 24 549010254 ps
T900 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.956362027 Aug 02 05:21:51 PM PDT 24 Aug 02 05:21:52 PM PDT 24 608722487 ps
T901 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2769177984 Aug 02 05:21:39 PM PDT 24 Aug 02 05:21:40 PM PDT 24 620727402 ps
T902 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.131376123 Aug 02 05:21:57 PM PDT 24 Aug 02 05:21:58 PM PDT 24 424453298 ps
T903 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2469100137 Aug 02 05:22:01 PM PDT 24 Aug 02 05:22:03 PM PDT 24 402780569 ps
T904 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.995464130 Aug 02 05:21:29 PM PDT 24 Aug 02 05:21:30 PM PDT 24 486565595 ps
T78 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.354193982 Aug 02 05:21:50 PM PDT 24 Aug 02 05:21:58 PM PDT 24 7868177784 ps
T905 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3727530629 Aug 02 05:21:40 PM PDT 24 Aug 02 05:21:41 PM PDT 24 793988949 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2772944596 Aug 02 05:21:29 PM PDT 24 Aug 02 05:22:02 PM PDT 24 15442064726 ps
T907 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2952071890 Aug 02 05:21:26 PM PDT 24 Aug 02 05:21:28 PM PDT 24 535265091 ps
T908 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2095836204 Aug 02 05:21:52 PM PDT 24 Aug 02 05:21:53 PM PDT 24 708179398 ps
T909 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2167784588 Aug 02 05:21:56 PM PDT 24 Aug 02 05:21:57 PM PDT 24 360154224 ps
T910 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3937913627 Aug 02 05:21:55 PM PDT 24 Aug 02 05:21:57 PM PDT 24 378654473 ps
T911 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2021986786 Aug 02 05:21:41 PM PDT 24 Aug 02 05:21:44 PM PDT 24 4762859673 ps
T912 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3331841049 Aug 02 05:21:37 PM PDT 24 Aug 02 05:21:43 PM PDT 24 4250130619 ps
T913 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1263489249 Aug 02 05:21:28 PM PDT 24 Aug 02 05:21:34 PM PDT 24 2500769459 ps
T914 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1964281487 Aug 02 05:21:37 PM PDT 24 Aug 02 05:21:39 PM PDT 24 384796398 ps
T915 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2144984155 Aug 02 05:21:32 PM PDT 24 Aug 02 05:21:34 PM PDT 24 352074202 ps
T916 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1779268247 Aug 02 05:21:41 PM PDT 24 Aug 02 05:21:43 PM PDT 24 349650198 ps
T917 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.961094262 Aug 02 05:21:49 PM PDT 24 Aug 02 05:21:50 PM PDT 24 528968597 ps
T918 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.486384123 Aug 02 05:21:40 PM PDT 24 Aug 02 05:21:43 PM PDT 24 566384751 ps
T919 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1124932256 Aug 02 05:21:25 PM PDT 24 Aug 02 05:21:28 PM PDT 24 916500817 ps

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.540408799
Short name T6
Test name
Test status
Simulation time 328096816711 ps
CPU time 726.79 seconds
Started Aug 02 05:23:16 PM PDT 24
Finished Aug 02 05:35:23 PM PDT 24
Peak memory 201452 kb
Host smart-c5ecca62-f55c-4b97-9611-07fe733eb7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540408799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.540408799
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3152886065
Short name T15
Test name
Test status
Simulation time 298554771483 ps
CPU time 238.5 seconds
Started Aug 02 05:23:29 PM PDT 24
Finished Aug 02 05:27:28 PM PDT 24
Peak memory 210200 kb
Host smart-768345a9-a788-428a-859a-74ae1311a2ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152886065 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3152886065
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1458442480
Short name T47
Test name
Test status
Simulation time 508608365896 ps
CPU time 1163.31 seconds
Started Aug 02 05:24:45 PM PDT 24
Finished Aug 02 05:44:09 PM PDT 24
Peak memory 201496 kb
Host smart-39659563-7104-4cc3-9c54-5a0776e99c44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458442480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1458442480
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.529448867
Short name T40
Test name
Test status
Simulation time 128444732915 ps
CPU time 432.64 seconds
Started Aug 02 05:22:26 PM PDT 24
Finished Aug 02 05:29:39 PM PDT 24
Peak memory 218404 kb
Host smart-756819e3-ee40-4bd9-acbc-cd39cd0ded65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529448867 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.529448867
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.827980410
Short name T146
Test name
Test status
Simulation time 559571842076 ps
CPU time 296.79 seconds
Started Aug 02 05:24:31 PM PDT 24
Finished Aug 02 05:29:28 PM PDT 24
Peak memory 201468 kb
Host smart-4fcba637-8c32-4ea8-9a65-1ce4f5f59183
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827980410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.827980410
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3919094651
Short name T17
Test name
Test status
Simulation time 169929943478 ps
CPU time 175.2 seconds
Started Aug 02 05:23:28 PM PDT 24
Finished Aug 02 05:26:23 PM PDT 24
Peak memory 217444 kb
Host smart-e9d7b9a1-ba33-4142-9317-87009a5c0512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919094651 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3919094651
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3485136369
Short name T152
Test name
Test status
Simulation time 537296450090 ps
CPU time 300 seconds
Started Aug 02 05:23:49 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 201520 kb
Host smart-5caa8af3-0eda-4b63-a584-093cea588aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485136369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3485136369
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1550115764
Short name T181
Test name
Test status
Simulation time 571455577148 ps
CPU time 1266.05 seconds
Started Aug 02 05:22:48 PM PDT 24
Finished Aug 02 05:43:54 PM PDT 24
Peak memory 201480 kb
Host smart-6af6f395-d0c7-4349-88af-6761b336ab9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550115764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1550115764
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.321021973
Short name T39
Test name
Test status
Simulation time 63318985699 ps
CPU time 250.53 seconds
Started Aug 02 05:22:48 PM PDT 24
Finished Aug 02 05:26:59 PM PDT 24
Peak memory 210168 kb
Host smart-9e6bc27e-1ea9-4d5a-afd6-c930ddd53446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321021973 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.321021973
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1390110186
Short name T242
Test name
Test status
Simulation time 525694401023 ps
CPU time 284.12 seconds
Started Aug 02 05:24:00 PM PDT 24
Finished Aug 02 05:28:44 PM PDT 24
Peak memory 201516 kb
Host smart-abc2162e-43d7-405d-9e1e-197d9dd96c2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390110186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1390110186
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.354900432
Short name T2
Test name
Test status
Simulation time 485885936909 ps
CPU time 272.82 seconds
Started Aug 02 05:23:37 PM PDT 24
Finished Aug 02 05:28:10 PM PDT 24
Peak memory 201460 kb
Host smart-4c8c91ca-0902-4d49-9dcc-43484fb57606
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=354900432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.354900432
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2787493029
Short name T85
Test name
Test status
Simulation time 496743770133 ps
CPU time 1196.11 seconds
Started Aug 02 05:25:50 PM PDT 24
Finished Aug 02 05:45:46 PM PDT 24
Peak memory 201448 kb
Host smart-839c36e8-2671-4748-a583-7bd473faa8a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787493029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2787493029
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3495642066
Short name T68
Test name
Test status
Simulation time 562177426 ps
CPU time 1.61 seconds
Started Aug 02 05:21:42 PM PDT 24
Finished Aug 02 05:21:44 PM PDT 24
Peak memory 201660 kb
Host smart-d94d1a29-6a5c-4105-a005-4a1a20ec8cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495642066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3495642066
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3501635933
Short name T62
Test name
Test status
Simulation time 8616525764 ps
CPU time 5.34 seconds
Started Aug 02 05:22:29 PM PDT 24
Finished Aug 02 05:22:35 PM PDT 24
Peak memory 217764 kb
Host smart-759abcaf-49f9-4ca2-abaa-cbb481c124da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501635933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3501635933
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3874418029
Short name T260
Test name
Test status
Simulation time 572453259950 ps
CPU time 1339.07 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:45:25 PM PDT 24
Peak memory 201516 kb
Host smart-a80d1d27-f28e-44d9-bf4e-06b7b238c120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874418029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3874418029
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2012350000
Short name T157
Test name
Test status
Simulation time 349527346826 ps
CPU time 188.67 seconds
Started Aug 02 05:24:08 PM PDT 24
Finished Aug 02 05:27:17 PM PDT 24
Peak memory 201380 kb
Host smart-0511e17c-8bdb-4418-98bd-c8c2a9879886
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012350000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2012350000
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2273695964
Short name T270
Test name
Test status
Simulation time 487306117156 ps
CPU time 1062.32 seconds
Started Aug 02 05:25:33 PM PDT 24
Finished Aug 02 05:43:16 PM PDT 24
Peak memory 201476 kb
Host smart-1f7d1060-beb2-40f9-9aff-d5449ea756ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273695964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2273695964
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2811642738
Short name T35
Test name
Test status
Simulation time 352951337272 ps
CPU time 201.63 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:26:25 PM PDT 24
Peak memory 201448 kb
Host smart-abcae1c8-7229-4136-830f-f27b6e421ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811642738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2811642738
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.931179981
Short name T129
Test name
Test status
Simulation time 352940547 ps
CPU time 1.01 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:40 PM PDT 24
Peak memory 201384 kb
Host smart-f90465d6-422a-423b-b2e4-49dea4431728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931179981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.931179981
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3744103021
Short name T180
Test name
Test status
Simulation time 486979737521 ps
CPU time 1137.89 seconds
Started Aug 02 05:24:43 PM PDT 24
Finished Aug 02 05:43:42 PM PDT 24
Peak memory 201444 kb
Host smart-dcc5a4f4-6805-4540-b9bf-4c6638bf679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744103021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3744103021
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3565968338
Short name T177
Test name
Test status
Simulation time 325792881346 ps
CPU time 185.4 seconds
Started Aug 02 05:24:45 PM PDT 24
Finished Aug 02 05:27:51 PM PDT 24
Peak memory 201488 kb
Host smart-377d2f6a-ad59-4ff1-9b6e-0255a4f20ac6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565968338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3565968338
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.220648031
Short name T159
Test name
Test status
Simulation time 489395904997 ps
CPU time 277.2 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:27:40 PM PDT 24
Peak memory 201500 kb
Host smart-4b997c9a-dd9e-4767-b891-862901f51cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220648031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.220648031
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2307724159
Short name T185
Test name
Test status
Simulation time 499682616892 ps
CPU time 87.12 seconds
Started Aug 02 05:23:28 PM PDT 24
Finished Aug 02 05:24:56 PM PDT 24
Peak memory 201484 kb
Host smart-f06f61a8-b384-41f7-86b5-36a305eb6823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307724159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2307724159
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2990065103
Short name T188
Test name
Test status
Simulation time 335646396497 ps
CPU time 348.74 seconds
Started Aug 02 05:23:21 PM PDT 24
Finished Aug 02 05:29:09 PM PDT 24
Peak memory 201432 kb
Host smart-c0eefbbe-8d18-4a03-adff-5d293eba39eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990065103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2990065103
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.866609994
Short name T173
Test name
Test status
Simulation time 497952593445 ps
CPU time 262.37 seconds
Started Aug 02 05:22:27 PM PDT 24
Finished Aug 02 05:26:50 PM PDT 24
Peak memory 201440 kb
Host smart-b8eab761-2913-4561-b9b7-d520b08bc11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866609994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.866609994
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.140426763
Short name T315
Test name
Test status
Simulation time 343607883614 ps
CPU time 815.91 seconds
Started Aug 02 05:24:12 PM PDT 24
Finished Aug 02 05:37:48 PM PDT 24
Peak memory 201468 kb
Host smart-becb43a0-d453-40f7-ab14-b3d7835e5473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140426763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.140426763
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.523687800
Short name T170
Test name
Test status
Simulation time 582380415223 ps
CPU time 1200.77 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:42:50 PM PDT 24
Peak memory 201480 kb
Host smart-149920de-c9f9-4755-ac1e-3733c143eba9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523687800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.523687800
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4234810468
Short name T280
Test name
Test status
Simulation time 389607404913 ps
CPU time 107.6 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:24:24 PM PDT 24
Peak memory 201500 kb
Host smart-52fdd9c2-840f-4086-80de-2c4e9502c38e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234810468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4234810468
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1479901388
Short name T104
Test name
Test status
Simulation time 371258827301 ps
CPU time 809.53 seconds
Started Aug 02 05:22:52 PM PDT 24
Finished Aug 02 05:36:22 PM PDT 24
Peak memory 201468 kb
Host smart-939db0eb-7fa5-46a9-bbc7-bc107668a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479901388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1479901388
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1884218199
Short name T101
Test name
Test status
Simulation time 177711210979 ps
CPU time 290.1 seconds
Started Aug 02 05:25:42 PM PDT 24
Finished Aug 02 05:30:32 PM PDT 24
Peak memory 211252 kb
Host smart-42107f12-0f4f-422c-a8fd-07b42a159a1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884218199 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1884218199
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3053724158
Short name T56
Test name
Test status
Simulation time 7650425331 ps
CPU time 6.89 seconds
Started Aug 02 05:21:30 PM PDT 24
Finished Aug 02 05:21:37 PM PDT 24
Peak memory 201728 kb
Host smart-50da1bbe-abe0-4ee0-bb1b-2a9ffa4d051e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053724158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3053724158
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2861966486
Short name T259
Test name
Test status
Simulation time 350783033464 ps
CPU time 764.73 seconds
Started Aug 02 05:25:02 PM PDT 24
Finished Aug 02 05:37:47 PM PDT 24
Peak memory 201548 kb
Host smart-66579dfc-2515-4132-9627-7928933699d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861966486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2861966486
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3783597555
Short name T281
Test name
Test status
Simulation time 327393229397 ps
CPU time 201.06 seconds
Started Aug 02 05:23:00 PM PDT 24
Finished Aug 02 05:26:21 PM PDT 24
Peak memory 201512 kb
Host smart-5d9db9cd-f6fe-4825-9d7a-92992e64ef1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783597555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3783597555
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1315491210
Short name T69
Test name
Test status
Simulation time 527772684 ps
CPU time 1.29 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:23:04 PM PDT 24
Peak memory 201240 kb
Host smart-11dd3c77-9dc0-4baa-9c3f-dd89f8008a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315491210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1315491210
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2943438874
Short name T53
Test name
Test status
Simulation time 2698192769 ps
CPU time 10.84 seconds
Started Aug 02 05:21:43 PM PDT 24
Finished Aug 02 05:21:54 PM PDT 24
Peak memory 201424 kb
Host smart-986e99d4-b51d-4da2-981b-041660dfc6f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943438874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2943438874
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.403981293
Short name T66
Test name
Test status
Simulation time 468241952 ps
CPU time 2.13 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:30 PM PDT 24
Peak memory 201708 kb
Host smart-9e47b606-f6a1-4795-b69d-f44cc1f8a400
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403981293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.403981293
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2160312663
Short name T21
Test name
Test status
Simulation time 283791782295 ps
CPU time 234.75 seconds
Started Aug 02 05:25:38 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 217420 kb
Host smart-eb3e2ba4-7bf9-4f77-a3e1-d2b618b332b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160312663 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2160312663
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2958528399
Short name T304
Test name
Test status
Simulation time 343168129576 ps
CPU time 217.24 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:26:21 PM PDT 24
Peak memory 201508 kb
Host smart-8a414780-f3fd-4ffa-9459-06d875498749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958528399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2958528399
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1901837480
Short name T12
Test name
Test status
Simulation time 600146539322 ps
CPU time 93.51 seconds
Started Aug 02 05:24:38 PM PDT 24
Finished Aug 02 05:26:12 PM PDT 24
Peak memory 201440 kb
Host smart-b51e0f23-aedb-4c01-b27c-90f616bc649b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901837480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1901837480
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2669682530
Short name T300
Test name
Test status
Simulation time 510520771213 ps
CPU time 181.86 seconds
Started Aug 02 05:24:54 PM PDT 24
Finished Aug 02 05:27:56 PM PDT 24
Peak memory 201500 kb
Host smart-5609391c-cdb8-4fd9-a408-2aa4d0be16d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669682530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2669682530
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2692613345
Short name T229
Test name
Test status
Simulation time 545503686668 ps
CPU time 1708.52 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:51:18 PM PDT 24
Peak memory 201820 kb
Host smart-fcc24fb4-cf46-447f-98d0-22cd9934e555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692613345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2692613345
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3740398850
Short name T298
Test name
Test status
Simulation time 161570843592 ps
CPU time 381.13 seconds
Started Aug 02 05:23:10 PM PDT 24
Finished Aug 02 05:29:31 PM PDT 24
Peak memory 201488 kb
Host smart-07cba23e-5f7f-4f34-a0cf-ad3f58fb2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740398850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3740398850
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1203689884
Short name T269
Test name
Test status
Simulation time 362734769742 ps
CPU time 777.31 seconds
Started Aug 02 05:23:11 PM PDT 24
Finished Aug 02 05:36:08 PM PDT 24
Peak memory 201548 kb
Host smart-371e945c-8f3f-4a59-9f0d-7ba72bfb60ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203689884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1203689884
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3185272468
Short name T323
Test name
Test status
Simulation time 522068612817 ps
CPU time 314.42 seconds
Started Aug 02 05:22:41 PM PDT 24
Finished Aug 02 05:27:56 PM PDT 24
Peak memory 201524 kb
Host smart-3ee2dd44-18d7-41fb-a26c-87f132a4aafa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185272468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3185272468
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.415315061
Short name T8
Test name
Test status
Simulation time 130208263261 ps
CPU time 706.73 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:34:15 PM PDT 24
Peak memory 211548 kb
Host smart-95173d30-35c6-4d01-86c2-3f1c357ddd7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415315061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.415315061
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3271484525
Short name T256
Test name
Test status
Simulation time 139401546040 ps
CPU time 33.22 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:23:11 PM PDT 24
Peak memory 209764 kb
Host smart-fe6c04a8-ee86-4092-8d56-1b89e7a4ca2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271484525 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3271484525
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1262224869
Short name T220
Test name
Test status
Simulation time 370722897971 ps
CPU time 100.15 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:24:38 PM PDT 24
Peak memory 201480 kb
Host smart-7852e6dd-3a96-4a8d-b73c-f9a57ebb3703
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262224869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1262224869
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2756716065
Short name T114
Test name
Test status
Simulation time 96873222120 ps
CPU time 312.28 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 217560 kb
Host smart-4bd28849-aa8d-42f4-93c9-8460b2e10dab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756716065 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2756716065
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2904440905
Short name T321
Test name
Test status
Simulation time 538710693017 ps
CPU time 577.04 seconds
Started Aug 02 05:23:10 PM PDT 24
Finished Aug 02 05:32:48 PM PDT 24
Peak memory 201512 kb
Host smart-3e31cca4-ba03-4d5a-8ad2-18aa0e320f62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904440905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2904440905
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2717463158
Short name T246
Test name
Test status
Simulation time 343293924665 ps
CPU time 758.8 seconds
Started Aug 02 05:24:28 PM PDT 24
Finished Aug 02 05:37:07 PM PDT 24
Peak memory 201468 kb
Host smart-b2251ee5-ad78-484b-83f5-439767849c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717463158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2717463158
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3404976456
Short name T30
Test name
Test status
Simulation time 496460581649 ps
CPU time 1071 seconds
Started Aug 02 05:23:10 PM PDT 24
Finished Aug 02 05:41:02 PM PDT 24
Peak memory 201576 kb
Host smart-540f590a-fb71-40fc-b8fc-153799ef6c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404976456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3404976456
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2483756197
Short name T18
Test name
Test status
Simulation time 359300863826 ps
CPU time 238.83 seconds
Started Aug 02 05:24:25 PM PDT 24
Finished Aug 02 05:28:24 PM PDT 24
Peak memory 210216 kb
Host smart-a911ea39-e406-495d-b85d-021d9fde3e2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483756197 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2483756197
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2383825507
Short name T148
Test name
Test status
Simulation time 211598060625 ps
CPU time 57.82 seconds
Started Aug 02 05:24:31 PM PDT 24
Finished Aug 02 05:25:29 PM PDT 24
Peak memory 210188 kb
Host smart-3ed9e843-d0d5-4a43-82c7-c641d7ade53d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383825507 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2383825507
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3400071699
Short name T268
Test name
Test status
Simulation time 593403600260 ps
CPU time 367.39 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:29:10 PM PDT 24
Peak memory 201476 kb
Host smart-9a4fcbe9-4d2f-4ec9-8b3b-53f7f812e465
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400071699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3400071699
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.4108792023
Short name T279
Test name
Test status
Simulation time 173515371458 ps
CPU time 391.04 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:30:19 PM PDT 24
Peak memory 201476 kb
Host smart-de75bfa8-2faa-4578-bddf-83aea8d0c5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108792023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.4108792023
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3141145118
Short name T55
Test name
Test status
Simulation time 279097221691 ps
CPU time 824.22 seconds
Started Aug 02 05:24:19 PM PDT 24
Finished Aug 02 05:38:03 PM PDT 24
Peak memory 209828 kb
Host smart-778f3f44-0e0d-40ba-9208-83ef3fe43524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141145118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3141145118
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.4181143116
Short name T263
Test name
Test status
Simulation time 167562257835 ps
CPU time 392.78 seconds
Started Aug 02 05:25:40 PM PDT 24
Finished Aug 02 05:32:13 PM PDT 24
Peak memory 201492 kb
Host smart-e3fcc8a1-af15-4b7d-9819-4d76f97471d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181143116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.4181143116
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.912798360
Short name T319
Test name
Test status
Simulation time 515952581461 ps
CPU time 1081.46 seconds
Started Aug 02 05:22:53 PM PDT 24
Finished Aug 02 05:40:55 PM PDT 24
Peak memory 201476 kb
Host smart-386ded98-8db7-4a9a-87b2-4c68697d97c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912798360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.912798360
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1030823940
Short name T72
Test name
Test status
Simulation time 8442283664 ps
CPU time 19.17 seconds
Started Aug 02 05:21:42 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 201660 kb
Host smart-07f2e12e-bcdc-4ddf-bf0b-a898d4aa6a87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030823940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1030823940
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2096239614
Short name T303
Test name
Test status
Simulation time 51426821588 ps
CPU time 51.86 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:23:12 PM PDT 24
Peak memory 209864 kb
Host smart-ae6c4df9-4976-46ba-9107-9fa722ac8529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096239614 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2096239614
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.770902691
Short name T222
Test name
Test status
Simulation time 342540672251 ps
CPU time 207.26 seconds
Started Aug 02 05:23:17 PM PDT 24
Finished Aug 02 05:26:44 PM PDT 24
Peak memory 201456 kb
Host smart-0d7209b4-6703-451f-9c19-1fa7d7c8daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770902691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.770902691
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3509829893
Short name T331
Test name
Test status
Simulation time 175120208733 ps
CPU time 103.27 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:25:31 PM PDT 24
Peak memory 201396 kb
Host smart-f5d8cce7-b554-4ce2-8c40-0abff4fee220
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509829893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3509829893
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2498100075
Short name T285
Test name
Test status
Simulation time 510660504900 ps
CPU time 1233.98 seconds
Started Aug 02 05:24:38 PM PDT 24
Finished Aug 02 05:45:12 PM PDT 24
Peak memory 201492 kb
Host smart-4e161eb2-7a02-4de3-a824-84266c7004e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498100075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2498100075
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3447415987
Short name T349
Test name
Test status
Simulation time 93500370309 ps
CPU time 287.47 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 210184 kb
Host smart-bb6e38b9-02be-454d-94bc-e4721b41a86d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447415987 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3447415987
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2045718553
Short name T84
Test name
Test status
Simulation time 139408397959 ps
CPU time 700.13 seconds
Started Aug 02 05:23:01 PM PDT 24
Finished Aug 02 05:34:41 PM PDT 24
Peak memory 201740 kb
Host smart-29be52c7-0ae5-4098-a080-7b00219b5b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045718553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2045718553
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.523381967
Short name T305
Test name
Test status
Simulation time 177599946562 ps
CPU time 217.25 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:26:15 PM PDT 24
Peak memory 201508 kb
Host smart-f5f03789-c531-41a4-9d87-2bb236e6af5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523381967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.523381967
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.566031103
Short name T329
Test name
Test status
Simulation time 397562813669 ps
CPU time 412.88 seconds
Started Aug 02 05:25:16 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 201476 kb
Host smart-2f864e5c-e056-43c6-939e-3ee2ed561977
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566031103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.566031103
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2637707625
Short name T172
Test name
Test status
Simulation time 353061090165 ps
CPU time 214.14 seconds
Started Aug 02 05:25:49 PM PDT 24
Finished Aug 02 05:29:23 PM PDT 24
Peak memory 201500 kb
Host smart-401b0396-bc80-4a2b-9c0c-294845addc3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637707625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2637707625
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3583089242
Short name T147
Test name
Test status
Simulation time 80020220948 ps
CPU time 136.65 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:25:01 PM PDT 24
Peak memory 210080 kb
Host smart-76bc0fe8-70da-45f4-aee6-607efff2a154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583089242 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3583089242
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3958764370
Short name T264
Test name
Test status
Simulation time 176721753345 ps
CPU time 101.65 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:24:40 PM PDT 24
Peak memory 201480 kb
Host smart-a4060458-fdf7-4419-8c47-e3e3515a3003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958764370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3958764370
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1148166350
Short name T214
Test name
Test status
Simulation time 216290254505 ps
CPU time 131.09 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:25:08 PM PDT 24
Peak memory 201532 kb
Host smart-55ec123b-4d91-4e44-a0c3-a3b13fe634f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148166350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1148166350
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2511531085
Short name T151
Test name
Test status
Simulation time 322651729598 ps
CPU time 450.7 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:30:35 PM PDT 24
Peak memory 201468 kb
Host smart-8d48fab7-3ecf-43df-b7bc-48f8ed53cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511531085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2511531085
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.449022291
Short name T183
Test name
Test status
Simulation time 492735384267 ps
CPU time 280.62 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:27:43 PM PDT 24
Peak memory 201496 kb
Host smart-b53380e6-31b7-4021-99ef-51ae6db7d99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449022291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.449022291
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1106421085
Short name T312
Test name
Test status
Simulation time 171847980040 ps
CPU time 367.38 seconds
Started Aug 02 05:23:07 PM PDT 24
Finished Aug 02 05:29:15 PM PDT 24
Peak memory 201528 kb
Host smart-b6ef1b88-7487-4e80-b90f-605aae0264ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106421085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1106421085
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3077207779
Short name T574
Test name
Test status
Simulation time 127262188938 ps
CPU time 465.37 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:30:59 PM PDT 24
Peak memory 201908 kb
Host smart-e3d4bff6-5f35-4dc8-9f95-fe1ea0bc7030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077207779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3077207779
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3293204788
Short name T297
Test name
Test status
Simulation time 544898758805 ps
CPU time 460.05 seconds
Started Aug 02 05:23:07 PM PDT 24
Finished Aug 02 05:30:47 PM PDT 24
Peak memory 201456 kb
Host smart-547832ac-764c-4759-a918-cc39bf8fe328
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293204788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3293204788
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3358334876
Short name T286
Test name
Test status
Simulation time 176434242045 ps
CPU time 414.26 seconds
Started Aug 02 05:24:19 PM PDT 24
Finished Aug 02 05:31:13 PM PDT 24
Peak memory 201472 kb
Host smart-4e42f2b2-cf92-48f2-b3a3-9dd5bca61151
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358334876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3358334876
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1764840167
Short name T4
Test name
Test status
Simulation time 190399983246 ps
CPU time 224.8 seconds
Started Aug 02 05:24:12 PM PDT 24
Finished Aug 02 05:27:57 PM PDT 24
Peak memory 201476 kb
Host smart-4b548de2-3c4d-413e-a527-f3396a9baf15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764840167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1764840167
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2050420586
Short name T105
Test name
Test status
Simulation time 354117377599 ps
CPU time 763.6 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:35:33 PM PDT 24
Peak memory 201412 kb
Host smart-d5c50373-f573-4a8b-9e56-ef485772331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050420586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2050420586
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2302217589
Short name T237
Test name
Test status
Simulation time 426886936580 ps
CPU time 790.28 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 201884 kb
Host smart-65a7c231-ffc4-402e-a55e-3a98b1113d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302217589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2302217589
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3712951564
Short name T311
Test name
Test status
Simulation time 159687895422 ps
CPU time 370.86 seconds
Started Aug 02 05:22:29 PM PDT 24
Finished Aug 02 05:28:40 PM PDT 24
Peak memory 201436 kb
Host smart-824dbd9e-8c43-4f34-8edd-2e634d06f657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712951564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3712951564
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3339649893
Short name T296
Test name
Test status
Simulation time 187613058655 ps
CPU time 89.56 seconds
Started Aug 02 05:22:56 PM PDT 24
Finished Aug 02 05:24:26 PM PDT 24
Peak memory 201440 kb
Host smart-732f71a9-efc8-4591-92c0-ec21bd5ef2e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339649893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3339649893
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4183941199
Short name T603
Test name
Test status
Simulation time 114008748390 ps
CPU time 612.69 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:33:12 PM PDT 24
Peak memory 201928 kb
Host smart-453670ec-3fe6-44f1-80ad-2e30c6607995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183941199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4183941199
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.392858064
Short name T184
Test name
Test status
Simulation time 341408677539 ps
CPU time 392.08 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:29:30 PM PDT 24
Peak memory 201416 kb
Host smart-8a238aee-16d7-47e7-91c8-9fc859e0db26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392858064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.392858064
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4069103476
Short name T234
Test name
Test status
Simulation time 127561587614 ps
CPU time 488.19 seconds
Started Aug 02 05:22:55 PM PDT 24
Finished Aug 02 05:31:04 PM PDT 24
Peak memory 201800 kb
Host smart-a0a72bcb-ca5d-4d72-a860-6299374b6998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069103476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4069103476
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.611531551
Short name T328
Test name
Test status
Simulation time 165669310263 ps
CPU time 194.98 seconds
Started Aug 02 05:23:06 PM PDT 24
Finished Aug 02 05:26:21 PM PDT 24
Peak memory 201444 kb
Host smart-3549b8bc-3136-4489-9931-1d947800f129
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611531551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.611531551
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1011045892
Short name T362
Test name
Test status
Simulation time 61281903609 ps
CPU time 157.14 seconds
Started Aug 02 05:22:31 PM PDT 24
Finished Aug 02 05:25:08 PM PDT 24
Peak memory 210168 kb
Host smart-692035c3-f09c-4d0c-b5c3-35e69d2bb0b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011045892 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1011045892
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3305787035
Short name T224
Test name
Test status
Simulation time 328669112748 ps
CPU time 180.62 seconds
Started Aug 02 05:23:17 PM PDT 24
Finished Aug 02 05:26:17 PM PDT 24
Peak memory 201500 kb
Host smart-6905605c-cb90-47c0-add5-976c6118b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305787035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3305787035
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.826529745
Short name T218
Test name
Test status
Simulation time 534479488933 ps
CPU time 338.21 seconds
Started Aug 02 05:24:08 PM PDT 24
Finished Aug 02 05:29:47 PM PDT 24
Peak memory 201412 kb
Host smart-d3ccfe52-13b2-40d9-b637-c27451db21f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826529745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.826529745
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1754366773
Short name T187
Test name
Test status
Simulation time 499809865251 ps
CPU time 1025.11 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:39:50 PM PDT 24
Peak memory 201408 kb
Host smart-31348f0b-4d06-4589-8998-6a9da7aaacf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754366773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1754366773
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1905836687
Short name T233
Test name
Test status
Simulation time 113194347947 ps
CPU time 547.79 seconds
Started Aug 02 05:25:04 PM PDT 24
Finished Aug 02 05:34:12 PM PDT 24
Peak memory 201876 kb
Host smart-114fe28f-1fdf-45bf-bf92-6bd2ac58a08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905836687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1905836687
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.4201343365
Short name T250
Test name
Test status
Simulation time 336196829912 ps
CPU time 367.68 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:29:06 PM PDT 24
Peak memory 201452 kb
Host smart-2b5c801c-74ff-4f82-ab75-d41eb090e121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201343365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4201343365
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2884360479
Short name T126
Test name
Test status
Simulation time 849825511 ps
CPU time 3.17 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:35 PM PDT 24
Peak memory 201584 kb
Host smart-e9f13361-46ab-4513-b81e-e235442973c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884360479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2884360479
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2772944596
Short name T906
Test name
Test status
Simulation time 15442064726 ps
CPU time 32.85 seconds
Started Aug 02 05:21:29 PM PDT 24
Finished Aug 02 05:22:02 PM PDT 24
Peak memory 201668 kb
Host smart-808e0ec1-3908-4cfe-a755-1cf2448e4027
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772944596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2772944596
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1643243196
Short name T817
Test name
Test status
Simulation time 674646974 ps
CPU time 1.1 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:29 PM PDT 24
Peak memory 201440 kb
Host smart-7cdb456a-c936-47b3-bd03-e60bc618542d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643243196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1643243196
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.230080091
Short name T858
Test name
Test status
Simulation time 326352732 ps
CPU time 1.27 seconds
Started Aug 02 05:21:26 PM PDT 24
Finished Aug 02 05:21:27 PM PDT 24
Peak memory 201504 kb
Host smart-d1a0dba4-9b7a-480f-b1fa-bb925dd5cb4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230080091 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.230080091
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1208741231
Short name T823
Test name
Test status
Simulation time 315757200 ps
CPU time 0.86 seconds
Started Aug 02 05:21:31 PM PDT 24
Finished Aug 02 05:21:32 PM PDT 24
Peak memory 201380 kb
Host smart-f2fe0d02-c787-441c-9bc9-648fc50839cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208741231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1208741231
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1306829079
Short name T853
Test name
Test status
Simulation time 371298859 ps
CPU time 1.48 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:29 PM PDT 24
Peak memory 201360 kb
Host smart-3e57c19e-b00c-4537-95cf-0e85f4b02be6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306829079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1306829079
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1758484788
Short name T824
Test name
Test status
Simulation time 5104000554 ps
CPU time 17.42 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:45 PM PDT 24
Peak memory 201612 kb
Host smart-2ac5a2d5-3050-431a-aac3-42c4433afbdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758484788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1758484788
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.924686038
Short name T73
Test name
Test status
Simulation time 645705571 ps
CPU time 3.57 seconds
Started Aug 02 05:21:28 PM PDT 24
Finished Aug 02 05:21:32 PM PDT 24
Peak memory 217628 kb
Host smart-a9bf4d6c-45e4-4f99-ac2f-378e9c3d27a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924686038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.924686038
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3869573568
Short name T818
Test name
Test status
Simulation time 4018749681 ps
CPU time 3.85 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:35 PM PDT 24
Peak memory 201712 kb
Host smart-e7a899c0-e82f-4eb5-aa49-6c3840abfe67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869573568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3869573568
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.146911814
Short name T136
Test name
Test status
Simulation time 1103567444 ps
CPU time 4.59 seconds
Started Aug 02 05:21:55 PM PDT 24
Finished Aug 02 05:21:59 PM PDT 24
Peak memory 201548 kb
Host smart-bbe58553-55f3-4f13-a42e-ef9ef21d65d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146911814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.146911814
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2090769207
Short name T131
Test name
Test status
Simulation time 26477418425 ps
CPU time 28.87 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:56 PM PDT 24
Peak memory 201644 kb
Host smart-429771af-3df0-4b26-a787-3f7139771c59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090769207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2090769207
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1124932256
Short name T919
Test name
Test status
Simulation time 916500817 ps
CPU time 2.89 seconds
Started Aug 02 05:21:25 PM PDT 24
Finished Aug 02 05:21:28 PM PDT 24
Peak memory 201432 kb
Host smart-89c5c501-7d4a-4d28-9bce-9ad60a743b6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124932256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1124932256
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1458260773
Short name T861
Test name
Test status
Simulation time 423759085 ps
CPU time 1.13 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:28 PM PDT 24
Peak memory 201528 kb
Host smart-e9d0ea00-a14e-4231-82b6-3fdfb77d4a33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458260773 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1458260773
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2889615125
Short name T128
Test name
Test status
Simulation time 413195864 ps
CPU time 1.69 seconds
Started Aug 02 05:21:30 PM PDT 24
Finished Aug 02 05:21:32 PM PDT 24
Peak memory 201416 kb
Host smart-0c9e216a-6328-477b-bdfc-9db1b2d3c4ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889615125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2889615125
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.196787204
Short name T871
Test name
Test status
Simulation time 442608495 ps
CPU time 1.53 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:29 PM PDT 24
Peak memory 201416 kb
Host smart-04d165e5-764e-4f18-9af3-daba1ed5678a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196787204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.196787204
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3724641626
Short name T141
Test name
Test status
Simulation time 2371726872 ps
CPU time 9.59 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:42 PM PDT 24
Peak memory 201448 kb
Host smart-241f4bad-833d-4fa5-b2e3-1d934fc04742
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724641626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3724641626
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2702158184
Short name T825
Test name
Test status
Simulation time 593149881 ps
CPU time 3.37 seconds
Started Aug 02 05:21:28 PM PDT 24
Finished Aug 02 05:21:32 PM PDT 24
Peak memory 201680 kb
Host smart-59b21f6f-215e-4cfe-99ed-73dd5dcacd4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702158184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2702158184
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1247492553
Short name T356
Test name
Test status
Simulation time 3986221788 ps
CPU time 6.46 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:38 PM PDT 24
Peak memory 201716 kb
Host smart-4c67fe77-ff0f-4497-8241-722d472a65ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247492553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1247492553
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3148112131
Short name T92
Test name
Test status
Simulation time 599011411 ps
CPU time 1.21 seconds
Started Aug 02 05:21:41 PM PDT 24
Finished Aug 02 05:21:43 PM PDT 24
Peak memory 201412 kb
Host smart-4c4b9ea0-ca64-4ffe-a289-3ebc10314aef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148112131 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3148112131
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2803930000
Short name T138
Test name
Test status
Simulation time 416836697 ps
CPU time 0.86 seconds
Started Aug 02 05:21:44 PM PDT 24
Finished Aug 02 05:21:45 PM PDT 24
Peak memory 201364 kb
Host smart-4b3bf216-62a1-4eb2-ad8b-9df029c978b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803930000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2803930000
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2920832151
Short name T822
Test name
Test status
Simulation time 435326356 ps
CPU time 1.65 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:41 PM PDT 24
Peak memory 201372 kb
Host smart-9ce97f7c-2027-4d8e-8285-f4aee22da37c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920832151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2920832151
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1722552100
Short name T867
Test name
Test status
Simulation time 8603339059 ps
CPU time 5.98 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:45 PM PDT 24
Peak memory 201756 kb
Host smart-2a68a766-d20b-4264-a8ed-320f71bd0062
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722552100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1722552100
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2017311009
Short name T75
Test name
Test status
Simulation time 809096837 ps
CPU time 1.16 seconds
Started Aug 02 05:21:42 PM PDT 24
Finished Aug 02 05:21:43 PM PDT 24
Peak memory 201532 kb
Host smart-63b653b6-0919-40f9-8f3e-4f3fbc38fb61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017311009 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2017311009
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4071446649
Short name T830
Test name
Test status
Simulation time 526236586 ps
CPU time 0.93 seconds
Started Aug 02 05:21:45 PM PDT 24
Finished Aug 02 05:21:46 PM PDT 24
Peak memory 201344 kb
Host smart-6ac20952-daed-4e99-836c-c9587b6910ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071446649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.4071446649
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.417097922
Short name T52
Test name
Test status
Simulation time 4705430710 ps
CPU time 14.2 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:54 PM PDT 24
Peak memory 201600 kb
Host smart-7e33c7d1-408d-4b31-9c29-f5173832dd8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417097922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.417097922
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1922070176
Short name T872
Test name
Test status
Simulation time 394224186 ps
CPU time 2.58 seconds
Started Aug 02 05:21:40 PM PDT 24
Finished Aug 02 05:21:42 PM PDT 24
Peak memory 217960 kb
Host smart-68dbdb27-b420-4a7e-9d30-844363280561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922070176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1922070176
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.240201818
Short name T65
Test name
Test status
Simulation time 348161399 ps
CPU time 1.81 seconds
Started Aug 02 05:21:41 PM PDT 24
Finished Aug 02 05:21:43 PM PDT 24
Peak memory 201528 kb
Host smart-38cc70cc-0112-4de7-99ab-26424e06e59b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240201818 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.240201818
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1137223525
Short name T899
Test name
Test status
Simulation time 549010254 ps
CPU time 1.28 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:41 PM PDT 24
Peak memory 201444 kb
Host smart-49f7b553-a36b-424d-9e45-071e84522ef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137223525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1137223525
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4198705552
Short name T815
Test name
Test status
Simulation time 425199577 ps
CPU time 1.58 seconds
Started Aug 02 05:21:42 PM PDT 24
Finished Aug 02 05:21:43 PM PDT 24
Peak memory 201376 kb
Host smart-6f044299-f8b1-47b8-9a46-ed48b93c2a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198705552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.4198705552
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1022583935
Short name T144
Test name
Test status
Simulation time 3866313917 ps
CPU time 4.91 seconds
Started Aug 02 05:21:40 PM PDT 24
Finished Aug 02 05:21:45 PM PDT 24
Peak memory 201620 kb
Host smart-2c4d56f9-56a4-4fb6-9230-ae5192713bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022583935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1022583935
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.486384123
Short name T918
Test name
Test status
Simulation time 566384751 ps
CPU time 3.02 seconds
Started Aug 02 05:21:40 PM PDT 24
Finished Aug 02 05:21:43 PM PDT 24
Peak memory 201672 kb
Host smart-3b2aff2f-6c1d-4dde-bbf5-c427857a1597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486384123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.486384123
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2021986786
Short name T911
Test name
Test status
Simulation time 4762859673 ps
CPU time 2.94 seconds
Started Aug 02 05:21:41 PM PDT 24
Finished Aug 02 05:21:44 PM PDT 24
Peak memory 201624 kb
Host smart-15528751-7316-4d3c-981d-6c1e274a2251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021986786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2021986786
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.778367486
Short name T850
Test name
Test status
Simulation time 503782033 ps
CPU time 1.54 seconds
Started Aug 02 05:21:44 PM PDT 24
Finished Aug 02 05:21:46 PM PDT 24
Peak memory 201540 kb
Host smart-094896cf-73b2-4ae4-8878-dbb391da89ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778367486 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.778367486
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3949361603
Short name T892
Test name
Test status
Simulation time 315798211 ps
CPU time 1.1 seconds
Started Aug 02 05:21:41 PM PDT 24
Finished Aug 02 05:21:42 PM PDT 24
Peak memory 201392 kb
Host smart-ad6aa2a9-a8f3-40d5-bae6-d09883c1f808
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949361603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3949361603
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2859515757
Short name T806
Test name
Test status
Simulation time 455937032 ps
CPU time 0.86 seconds
Started Aug 02 05:21:43 PM PDT 24
Finished Aug 02 05:21:44 PM PDT 24
Peak memory 201348 kb
Host smart-8b0c7fbd-f349-4809-96a1-35c3afdf7cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859515757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2859515757
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2099854682
Short name T849
Test name
Test status
Simulation time 4146385987 ps
CPU time 13.33 seconds
Started Aug 02 05:21:42 PM PDT 24
Finished Aug 02 05:21:55 PM PDT 24
Peak memory 201624 kb
Host smart-98b08434-2048-4b8e-8a41-d9b24db17128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099854682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2099854682
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1779268247
Short name T916
Test name
Test status
Simulation time 349650198 ps
CPU time 1.95 seconds
Started Aug 02 05:21:41 PM PDT 24
Finished Aug 02 05:21:43 PM PDT 24
Peak memory 201676 kb
Host smart-12265a90-6b10-45a5-99b3-dab04775a865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779268247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1779268247
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1782220156
Short name T357
Test name
Test status
Simulation time 9321865159 ps
CPU time 23.8 seconds
Started Aug 02 05:21:38 PM PDT 24
Finished Aug 02 05:22:02 PM PDT 24
Peak memory 201688 kb
Host smart-47ebfb2a-7ffe-4298-a91d-4b86db4f85cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782220156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1782220156
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1535624613
Short name T828
Test name
Test status
Simulation time 535683547 ps
CPU time 1.23 seconds
Started Aug 02 05:21:52 PM PDT 24
Finished Aug 02 05:21:53 PM PDT 24
Peak memory 201512 kb
Host smart-1c9d4024-ba37-492a-ba16-67dc7056a1ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535624613 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1535624613
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.956362027
Short name T900
Test name
Test status
Simulation time 608722487 ps
CPU time 1.13 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:21:52 PM PDT 24
Peak memory 201424 kb
Host smart-1da0859c-15db-40d1-872d-b4bbe9c2b799
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956362027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.956362027
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.961094262
Short name T917
Test name
Test status
Simulation time 528968597 ps
CPU time 0.94 seconds
Started Aug 02 05:21:49 PM PDT 24
Finished Aug 02 05:21:50 PM PDT 24
Peak memory 201464 kb
Host smart-f75b1636-c4cd-4f7b-99a2-795d2631fba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961094262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.961094262
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2499011499
Short name T898
Test name
Test status
Simulation time 4127063651 ps
CPU time 9.8 seconds
Started Aug 02 05:21:50 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 201640 kb
Host smart-9cce51c0-2bfd-450e-b011-3d515f5505c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499011499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2499011499
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2605384649
Short name T851
Test name
Test status
Simulation time 680082376 ps
CPU time 3.1 seconds
Started Aug 02 05:21:50 PM PDT 24
Finished Aug 02 05:21:53 PM PDT 24
Peak memory 209912 kb
Host smart-70c13b4a-d4e3-4120-baee-093605494064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605384649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2605384649
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1874321477
Short name T57
Test name
Test status
Simulation time 4873025471 ps
CPU time 3.82 seconds
Started Aug 02 05:21:54 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201720 kb
Host smart-0d18135d-93aa-4c95-87f5-9172522041a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874321477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1874321477
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3480884819
Short name T74
Test name
Test status
Simulation time 537648826 ps
CPU time 1.14 seconds
Started Aug 02 05:21:53 PM PDT 24
Finished Aug 02 05:21:55 PM PDT 24
Peak memory 201512 kb
Host smart-440f43a1-b627-46f7-877b-9610a50f0f58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480884819 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3480884819
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4247081210
Short name T127
Test name
Test status
Simulation time 335523941 ps
CPU time 1.26 seconds
Started Aug 02 05:21:54 PM PDT 24
Finished Aug 02 05:21:55 PM PDT 24
Peak memory 201404 kb
Host smart-cc140d76-1ede-4d7a-a013-7eb17fd0fdeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247081210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.4247081210
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3257634427
Short name T826
Test name
Test status
Simulation time 529043558 ps
CPU time 1.16 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:21:52 PM PDT 24
Peak memory 201348 kb
Host smart-33ecb0d6-16cd-488c-8ce4-3e64f5bca853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257634427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3257634427
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1973068979
Short name T139
Test name
Test status
Simulation time 2357826981 ps
CPU time 3.9 seconds
Started Aug 02 05:21:50 PM PDT 24
Finished Aug 02 05:21:54 PM PDT 24
Peak memory 201428 kb
Host smart-94ee1054-49ea-4d53-a06a-4ac48cfafed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973068979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1973068979
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2095836204
Short name T908
Test name
Test status
Simulation time 708179398 ps
CPU time 1.69 seconds
Started Aug 02 05:21:52 PM PDT 24
Finished Aug 02 05:21:53 PM PDT 24
Peak memory 201656 kb
Host smart-c5ffa5be-a942-4e54-b58b-5ab8cb9b916d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095836204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2095836204
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2525305106
Short name T894
Test name
Test status
Simulation time 4961690547 ps
CPU time 4.05 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:21:55 PM PDT 24
Peak memory 200980 kb
Host smart-0d7a5d17-8bfb-4a48-8397-03f0ad9eb343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525305106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2525305106
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.500183790
Short name T863
Test name
Test status
Simulation time 512484558 ps
CPU time 1.34 seconds
Started Aug 02 05:21:52 PM PDT 24
Finished Aug 02 05:21:53 PM PDT 24
Peak memory 201484 kb
Host smart-8c2e62a1-3b55-4e62-bc4d-bafdbe9dd173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500183790 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.500183790
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3000423151
Short name T125
Test name
Test status
Simulation time 720335606 ps
CPU time 1.02 seconds
Started Aug 02 05:21:50 PM PDT 24
Finished Aug 02 05:21:51 PM PDT 24
Peak memory 201396 kb
Host smart-8961f90a-4ab1-498b-bd9d-32c189081115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000423151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3000423151
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.237322106
Short name T888
Test name
Test status
Simulation time 417207788 ps
CPU time 1.55 seconds
Started Aug 02 05:21:52 PM PDT 24
Finished Aug 02 05:21:53 PM PDT 24
Peak memory 201364 kb
Host smart-61db1ae7-9de7-46f7-a4f2-b4a35feefe96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237322106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.237322106
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2041516979
Short name T835
Test name
Test status
Simulation time 5310034604 ps
CPU time 9.73 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 201604 kb
Host smart-7a4b4764-f3a0-4cfb-a4ba-67ff77d18766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041516979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2041516979
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3989536372
Short name T856
Test name
Test status
Simulation time 1154112600 ps
CPU time 1.58 seconds
Started Aug 02 05:21:50 PM PDT 24
Finished Aug 02 05:21:52 PM PDT 24
Peak memory 201680 kb
Host smart-b7d53de4-be94-4cff-bb9a-3c3aa362b1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989536372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3989536372
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1563290659
Short name T61
Test name
Test status
Simulation time 4637100543 ps
CPU time 3.84 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:21:55 PM PDT 24
Peak memory 201680 kb
Host smart-a71c171a-9aed-42a3-9a2a-eb61e4fd4fba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563290659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1563290659
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.262023934
Short name T819
Test name
Test status
Simulation time 507271005 ps
CPU time 1.16 seconds
Started Aug 02 05:21:53 PM PDT 24
Finished Aug 02 05:21:54 PM PDT 24
Peak memory 201524 kb
Host smart-0350db04-d3bc-4448-8dab-60a12cac8618
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262023934 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.262023934
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3891257965
Short name T859
Test name
Test status
Simulation time 355111484 ps
CPU time 1.19 seconds
Started Aug 02 05:21:50 PM PDT 24
Finished Aug 02 05:21:51 PM PDT 24
Peak memory 201380 kb
Host smart-de7cdeca-09a2-4404-95d4-f92d2e340f47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891257965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3891257965
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1868442923
Short name T845
Test name
Test status
Simulation time 404694995 ps
CPU time 0.9 seconds
Started Aug 02 05:21:52 PM PDT 24
Finished Aug 02 05:21:53 PM PDT 24
Peak memory 201400 kb
Host smart-2d6b1da5-98bb-49ae-8e81-565cdb4ed4e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868442923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1868442923
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3582385088
Short name T874
Test name
Test status
Simulation time 4912707066 ps
CPU time 3.61 seconds
Started Aug 02 05:21:50 PM PDT 24
Finished Aug 02 05:21:54 PM PDT 24
Peak memory 201660 kb
Host smart-adac5263-bdc4-481f-8c52-03932bfe3dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582385088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3582385088
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2048357157
Short name T869
Test name
Test status
Simulation time 495728517 ps
CPU time 2.46 seconds
Started Aug 02 05:21:52 PM PDT 24
Finished Aug 02 05:21:55 PM PDT 24
Peak memory 201612 kb
Host smart-6c196aa4-1a0c-442e-867c-e1ae4c824edc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048357157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2048357157
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2443997098
Short name T816
Test name
Test status
Simulation time 4216216699 ps
CPU time 6.2 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:21:57 PM PDT 24
Peak memory 201664 kb
Host smart-6f93a90f-3b81-4c9c-a5da-ebea0bade4a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443997098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2443997098
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.867627627
Short name T60
Test name
Test status
Simulation time 420774285 ps
CPU time 1.19 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:21:52 PM PDT 24
Peak memory 200684 kb
Host smart-3d1d5813-f06a-4e1c-b0e2-2162b7efee6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867627627 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.867627627
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.696354372
Short name T885
Test name
Test status
Simulation time 460466631 ps
CPU time 0.86 seconds
Started Aug 02 05:21:49 PM PDT 24
Finished Aug 02 05:21:49 PM PDT 24
Peak memory 201404 kb
Host smart-cec47e8a-5618-4a40-9f3d-d956d67262a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696354372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.696354372
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2082791250
Short name T808
Test name
Test status
Simulation time 326051190 ps
CPU time 0.79 seconds
Started Aug 02 05:21:53 PM PDT 24
Finished Aug 02 05:21:54 PM PDT 24
Peak memory 201360 kb
Host smart-5d45564a-2993-4b76-8586-05b15557158b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082791250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2082791250
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2524698733
Short name T891
Test name
Test status
Simulation time 2704462266 ps
CPU time 1.67 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:21:53 PM PDT 24
Peak memory 201356 kb
Host smart-78cfe087-81c9-4a0c-ae19-d2780c03aa92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524698733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2524698733
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3685418918
Short name T854
Test name
Test status
Simulation time 508056614 ps
CPU time 2.1 seconds
Started Aug 02 05:21:52 PM PDT 24
Finished Aug 02 05:21:54 PM PDT 24
Peak memory 201744 kb
Host smart-edf0ad86-5f2b-4753-8d31-46829afbc6dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685418918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3685418918
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1955815447
Short name T358
Test name
Test status
Simulation time 8782387557 ps
CPU time 12.34 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:22:04 PM PDT 24
Peak memory 201628 kb
Host smart-a5cfa3f3-bcac-43aa-ad10-ae48baef460b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955815447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1955815447
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1289440233
Short name T880
Test name
Test status
Simulation time 326063749 ps
CPU time 1.55 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:02 PM PDT 24
Peak memory 201516 kb
Host smart-a54d5403-696a-486d-b4d5-16bc24a54b6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289440233 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1289440233
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3660926537
Short name T841
Test name
Test status
Simulation time 498214547 ps
CPU time 1.4 seconds
Started Aug 02 05:21:56 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201332 kb
Host smart-49e1ce0d-4270-4892-877d-e44673a05e4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660926537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3660926537
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3010421071
Short name T890
Test name
Test status
Simulation time 327915906 ps
CPU time 1.43 seconds
Started Aug 02 05:21:58 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 201352 kb
Host smart-8bf4320b-bab7-45ea-82f7-f49569784111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010421071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3010421071
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1841983728
Short name T864
Test name
Test status
Simulation time 4383281517 ps
CPU time 3.51 seconds
Started Aug 02 05:22:01 PM PDT 24
Finished Aug 02 05:22:05 PM PDT 24
Peak memory 201652 kb
Host smart-eabdb613-891d-4803-b839-e708021f2600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841983728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1841983728
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4175009196
Short name T852
Test name
Test status
Simulation time 461068830 ps
CPU time 1.4 seconds
Started Aug 02 05:21:51 PM PDT 24
Finished Aug 02 05:21:53 PM PDT 24
Peak memory 201716 kb
Host smart-2f502eb7-f9d8-4843-9ca3-ae5fbf0fbb51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175009196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4175009196
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.354193982
Short name T78
Test name
Test status
Simulation time 7868177784 ps
CPU time 7.17 seconds
Started Aug 02 05:21:50 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201704 kb
Host smart-5dac1069-95e1-435b-946e-ab4a5ce27e12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354193982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.354193982
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2920074546
Short name T868
Test name
Test status
Simulation time 1142178286 ps
CPU time 6.85 seconds
Started Aug 02 05:21:29 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201512 kb
Host smart-38c5e5a9-b970-4a4f-b6f9-398b6c7ad376
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920074546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2920074546
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1211480025
Short name T886
Test name
Test status
Simulation time 31905510302 ps
CPU time 22.4 seconds
Started Aug 02 05:21:29 PM PDT 24
Finished Aug 02 05:21:51 PM PDT 24
Peak memory 201676 kb
Host smart-60759605-e580-43cf-b3e0-f3e47611e991
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211480025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1211480025
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3285563404
Short name T124
Test name
Test status
Simulation time 718851144 ps
CPU time 1.11 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:28 PM PDT 24
Peak memory 201404 kb
Host smart-bab9efc9-020a-4d13-9d5f-505f9369a305
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285563404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3285563404
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3030078492
Short name T883
Test name
Test status
Simulation time 375431915 ps
CPU time 1.33 seconds
Started Aug 02 05:21:29 PM PDT 24
Finished Aug 02 05:21:30 PM PDT 24
Peak memory 201544 kb
Host smart-d79ff14b-c3c1-4c61-a749-27a649cf77fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030078492 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3030078492
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2952071890
Short name T907
Test name
Test status
Simulation time 535265091 ps
CPU time 1.92 seconds
Started Aug 02 05:21:26 PM PDT 24
Finished Aug 02 05:21:28 PM PDT 24
Peak memory 201384 kb
Host smart-f308ab0e-6aac-4747-8821-e6cb49935a11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952071890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2952071890
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3434323242
Short name T893
Test name
Test status
Simulation time 453932081 ps
CPU time 0.88 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:28 PM PDT 24
Peak memory 201384 kb
Host smart-9f5f1ea0-0b42-4536-b7de-25b315b24638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434323242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3434323242
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2737367481
Short name T866
Test name
Test status
Simulation time 2418409350 ps
CPU time 8.5 seconds
Started Aug 02 05:21:27 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201432 kb
Host smart-db569f58-0136-41eb-92e5-235d8a3b53fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737367481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2737367481
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3604565020
Short name T67
Test name
Test status
Simulation time 394960288 ps
CPU time 2.63 seconds
Started Aug 02 05:21:28 PM PDT 24
Finished Aug 02 05:21:31 PM PDT 24
Peak memory 201652 kb
Host smart-a0fa6f2a-5f6b-4c57-935f-b49e58fbddbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604565020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3604565020
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1175005400
Short name T887
Test name
Test status
Simulation time 8948264075 ps
CPU time 5.04 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:37 PM PDT 24
Peak memory 201688 kb
Host smart-b5d1639e-54c7-404f-9c39-ebc761b1e453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175005400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1175005400
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.657802424
Short name T837
Test name
Test status
Simulation time 412124534 ps
CPU time 1.56 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:59 PM PDT 24
Peak memory 201380 kb
Host smart-e6fa41af-8fb9-4718-8c9e-06a991a17e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657802424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.657802424
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3937913627
Short name T910
Test name
Test status
Simulation time 378654473 ps
CPU time 1.37 seconds
Started Aug 02 05:21:55 PM PDT 24
Finished Aug 02 05:21:57 PM PDT 24
Peak memory 201384 kb
Host smart-f6cbd05f-f8c9-4166-b894-4469ed26ca82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937913627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3937913627
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2971352248
Short name T878
Test name
Test status
Simulation time 489568900 ps
CPU time 1.74 seconds
Started Aug 02 05:21:56 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201364 kb
Host smart-ce3fff2d-bf67-4c71-bcf7-7a8da91b9fe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971352248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2971352248
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.309349597
Short name T809
Test name
Test status
Simulation time 363292045 ps
CPU time 1.11 seconds
Started Aug 02 05:21:56 PM PDT 24
Finished Aug 02 05:21:57 PM PDT 24
Peak memory 201400 kb
Host smart-ad9bf012-33ca-4639-8d9d-f725aa6a90d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309349597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.309349597
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3236329825
Short name T803
Test name
Test status
Simulation time 499005773 ps
CPU time 1.02 seconds
Started Aug 02 05:22:03 PM PDT 24
Finished Aug 02 05:22:04 PM PDT 24
Peak memory 201368 kb
Host smart-767015d2-dcb1-45d4-a70e-dbd56c991ab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236329825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3236329825
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2700996381
Short name T832
Test name
Test status
Simulation time 349544872 ps
CPU time 1.14 seconds
Started Aug 02 05:21:59 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 201336 kb
Host smart-7e1c606d-a427-4304-a4e0-c50ef7947290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700996381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2700996381
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2167784588
Short name T909
Test name
Test status
Simulation time 360154224 ps
CPU time 0.72 seconds
Started Aug 02 05:21:56 PM PDT 24
Finished Aug 02 05:21:57 PM PDT 24
Peak memory 201372 kb
Host smart-21725c7b-3386-4804-812f-c3531888f107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167784588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2167784588
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.882112194
Short name T877
Test name
Test status
Simulation time 295190331 ps
CPU time 1.21 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:02 PM PDT 24
Peak memory 201404 kb
Host smart-8cc4b0fd-a5f5-450a-8f80-4f86b8bdec3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882112194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.882112194
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2469100137
Short name T903
Test name
Test status
Simulation time 402780569 ps
CPU time 1.6 seconds
Started Aug 02 05:22:01 PM PDT 24
Finished Aug 02 05:22:03 PM PDT 24
Peak memory 201368 kb
Host smart-67f864de-7b1c-4dce-a298-14ba72038340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469100137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2469100137
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4266226752
Short name T814
Test name
Test status
Simulation time 344548099 ps
CPU time 1.41 seconds
Started Aug 02 05:21:58 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 201384 kb
Host smart-6eea283b-a38e-4d82-ab48-d021dceadf7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266226752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4266226752
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.877230598
Short name T132
Test name
Test status
Simulation time 1321712649 ps
CPU time 3.06 seconds
Started Aug 02 05:21:28 PM PDT 24
Finished Aug 02 05:21:31 PM PDT 24
Peak memory 201584 kb
Host smart-ed7804f6-72fb-443c-a32c-af6ea5dbbcb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877230598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.877230598
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1035876177
Short name T134
Test name
Test status
Simulation time 28760171808 ps
CPU time 20.07 seconds
Started Aug 02 05:21:31 PM PDT 24
Finished Aug 02 05:21:51 PM PDT 24
Peak memory 201636 kb
Host smart-5e95e961-0497-4f89-b111-8b5476ff16de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035876177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1035876177
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1625405086
Short name T876
Test name
Test status
Simulation time 1121752335 ps
CPU time 1.29 seconds
Started Aug 02 05:21:26 PM PDT 24
Finished Aug 02 05:21:28 PM PDT 24
Peak memory 201396 kb
Host smart-6725b732-b80f-4138-8f41-3b79e3fe50e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625405086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1625405086
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2122472154
Short name T834
Test name
Test status
Simulation time 571414604 ps
CPU time 2.28 seconds
Started Aug 02 05:21:25 PM PDT 24
Finished Aug 02 05:21:27 PM PDT 24
Peak memory 201440 kb
Host smart-ca623e5d-5445-4232-885f-c50a097bbeb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122472154 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2122472154
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.748264817
Short name T135
Test name
Test status
Simulation time 444618560 ps
CPU time 1.94 seconds
Started Aug 02 05:21:26 PM PDT 24
Finished Aug 02 05:21:29 PM PDT 24
Peak memory 201336 kb
Host smart-433d55e8-dc41-4323-832d-0e8e1bd1165e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748264817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.748264817
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.995464130
Short name T904
Test name
Test status
Simulation time 486565595 ps
CPU time 1.21 seconds
Started Aug 02 05:21:29 PM PDT 24
Finished Aug 02 05:21:30 PM PDT 24
Peak memory 201412 kb
Host smart-c8cdf5a8-5770-4f6a-a938-2b8b94fb2b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995464130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.995464130
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1263489249
Short name T913
Test name
Test status
Simulation time 2500769459 ps
CPU time 6.05 seconds
Started Aug 02 05:21:28 PM PDT 24
Finished Aug 02 05:21:34 PM PDT 24
Peak memory 201416 kb
Host smart-509f453d-f71a-4187-b9a6-f30affa49887
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263489249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1263489249
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3941149786
Short name T870
Test name
Test status
Simulation time 301863025 ps
CPU time 1.33 seconds
Started Aug 02 05:21:56 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201360 kb
Host smart-bddf4df3-8789-489d-9848-4a4e6d78a11b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941149786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3941149786
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1288165123
Short name T889
Test name
Test status
Simulation time 343181415 ps
CPU time 1.12 seconds
Started Aug 02 05:21:59 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 201352 kb
Host smart-a205fe65-e15f-4c9c-a6ab-769b0bac532a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288165123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1288165123
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3106878902
Short name T884
Test name
Test status
Simulation time 440265585 ps
CPU time 1.59 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:59 PM PDT 24
Peak memory 201308 kb
Host smart-ae7d5f13-9820-451d-9c54-13deb4a66c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106878902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3106878902
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2247935557
Short name T804
Test name
Test status
Simulation time 496464503 ps
CPU time 1.23 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:02 PM PDT 24
Peak memory 201416 kb
Host smart-a5c1e30e-a36b-4694-bf71-de689a4187d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247935557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2247935557
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1897473022
Short name T807
Test name
Test status
Simulation time 365628622 ps
CPU time 0.89 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 201396 kb
Host smart-ea59b533-cb67-4b8c-9d98-2c46d8c2de96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897473022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1897473022
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.404716626
Short name T802
Test name
Test status
Simulation time 488937832 ps
CPU time 0.79 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201460 kb
Host smart-a4adf2df-e6fb-4dc4-be0f-b54c52ed06e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404716626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.404716626
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1650020462
Short name T827
Test name
Test status
Simulation time 353220452 ps
CPU time 0.87 seconds
Started Aug 02 05:21:58 PM PDT 24
Finished Aug 02 05:21:59 PM PDT 24
Peak memory 201408 kb
Host smart-e55920cb-8d07-498a-a01e-654c0b4f5cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650020462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1650020462
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3026595559
Short name T811
Test name
Test status
Simulation time 517084127 ps
CPU time 1.32 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201404 kb
Host smart-91690618-5444-44bb-8b7f-1a3c430acbf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026595559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3026595559
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3776673972
Short name T813
Test name
Test status
Simulation time 480178547 ps
CPU time 1.56 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201368 kb
Host smart-a0402e71-6d44-4cb8-95e4-3a66c1353d96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776673972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3776673972
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4229477584
Short name T882
Test name
Test status
Simulation time 507512096 ps
CPU time 0.98 seconds
Started Aug 02 05:22:03 PM PDT 24
Finished Aug 02 05:22:05 PM PDT 24
Peak memory 201408 kb
Host smart-46b5e222-9e97-4589-8e3a-538a58c90c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229477584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.4229477584
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.970573006
Short name T897
Test name
Test status
Simulation time 951673384 ps
CPU time 2.93 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:38 PM PDT 24
Peak memory 201556 kb
Host smart-ff4134e0-1ee5-41da-a1e6-857eca9bb838
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970573006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.970573006
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4730253
Short name T873
Test name
Test status
Simulation time 26378239409 ps
CPU time 84.85 seconds
Started Aug 02 05:21:33 PM PDT 24
Finished Aug 02 05:22:58 PM PDT 24
Peak memory 201600 kb
Host smart-0074c4e5-e7fb-461b-9e75-8e557bcf20d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4730253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bas
h.4730253
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2153793973
Short name T843
Test name
Test status
Simulation time 828380774 ps
CPU time 1.08 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:34 PM PDT 24
Peak memory 201368 kb
Host smart-2e4544f4-d5c4-4b4e-85c0-2886a54027eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153793973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2153793973
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2726040285
Short name T838
Test name
Test status
Simulation time 522544777 ps
CPU time 1.18 seconds
Started Aug 02 05:21:33 PM PDT 24
Finished Aug 02 05:21:34 PM PDT 24
Peak memory 201572 kb
Host smart-5764ec8f-f5c9-41bc-b72e-2da1b1f2701a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726040285 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2726040285
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1388000982
Short name T133
Test name
Test status
Simulation time 352429446 ps
CPU time 1.6 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:34 PM PDT 24
Peak memory 201380 kb
Host smart-84bab6db-a9dc-4ef6-afdd-77b44c1b42c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388000982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1388000982
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2991548399
Short name T855
Test name
Test status
Simulation time 530766444 ps
CPU time 1.81 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201424 kb
Host smart-8e83ef33-0960-464c-a272-d08ab67c3ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991548399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2991548399
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.670530520
Short name T820
Test name
Test status
Simulation time 4379021119 ps
CPU time 3.43 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:42 PM PDT 24
Peak memory 201632 kb
Host smart-a872828e-d260-4ad0-b02e-a6a3ff0a469b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670530520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.670530520
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1084299464
Short name T70
Test name
Test status
Simulation time 394584966 ps
CPU time 2.01 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201668 kb
Host smart-219f3d69-60b0-4b19-b9e2-6a3a5a86fa58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084299464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1084299464
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3331841049
Short name T912
Test name
Test status
Simulation time 4250130619 ps
CPU time 6.24 seconds
Started Aug 02 05:21:37 PM PDT 24
Finished Aug 02 05:21:43 PM PDT 24
Peak memory 201696 kb
Host smart-57cd6287-a210-45bc-8224-6592ea9b8507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331841049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3331841049
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3294752521
Short name T829
Test name
Test status
Simulation time 410599739 ps
CPU time 0.89 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 201352 kb
Host smart-81042eea-0301-4e13-bc2f-c00181943051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294752521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3294752521
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.131376123
Short name T902
Test name
Test status
Simulation time 424453298 ps
CPU time 0.72 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201376 kb
Host smart-e67c57a1-8cfd-4bff-b1a3-900130d0d803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131376123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.131376123
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.855331479
Short name T812
Test name
Test status
Simulation time 385345184 ps
CPU time 1.54 seconds
Started Aug 02 05:21:58 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 201380 kb
Host smart-4817949e-2d95-48bb-80cb-9c9a88b5a08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855331479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.855331479
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.313091892
Short name T821
Test name
Test status
Simulation time 466678343 ps
CPU time 0.79 seconds
Started Aug 02 05:21:59 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 201364 kb
Host smart-6eb8736d-3a9e-4f2b-9610-aac92de2c73f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313091892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.313091892
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.887662907
Short name T839
Test name
Test status
Simulation time 311859180 ps
CPU time 0.82 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201376 kb
Host smart-ae39512e-2d96-44d8-b4ec-546edacb5b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887662907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.887662907
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.258980490
Short name T810
Test name
Test status
Simulation time 327919162 ps
CPU time 1.36 seconds
Started Aug 02 05:21:58 PM PDT 24
Finished Aug 02 05:21:59 PM PDT 24
Peak memory 201360 kb
Host smart-a233891b-40b4-408e-89e9-def81f9f6714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258980490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.258980490
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2531654201
Short name T895
Test name
Test status
Simulation time 432284009 ps
CPU time 1.7 seconds
Started Aug 02 05:21:59 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 201400 kb
Host smart-59f82a0b-f7ac-4e62-9983-f2a608f955eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531654201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2531654201
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.904900438
Short name T860
Test name
Test status
Simulation time 443328293 ps
CPU time 1.66 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 201424 kb
Host smart-fead2b32-7033-486c-9559-41e8869ba01a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904900438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.904900438
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2020807550
Short name T846
Test name
Test status
Simulation time 553491171 ps
CPU time 0.92 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:05 PM PDT 24
Peak memory 201316 kb
Host smart-9ddcafd8-a33f-4ac9-b3db-8bb1de3e3644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020807550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2020807550
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.429803500
Short name T836
Test name
Test status
Simulation time 357841004 ps
CPU time 1.05 seconds
Started Aug 02 05:21:58 PM PDT 24
Finished Aug 02 05:21:59 PM PDT 24
Peak memory 201352 kb
Host smart-e1e0696d-c03a-462a-a7ae-c9ae79fa1aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429803500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.429803500
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2905093976
Short name T881
Test name
Test status
Simulation time 365167415 ps
CPU time 1.56 seconds
Started Aug 02 05:21:33 PM PDT 24
Finished Aug 02 05:21:34 PM PDT 24
Peak memory 201504 kb
Host smart-ec3074cb-4f07-4c2d-b26f-9ef7f8016b66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905093976 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2905093976
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2769177984
Short name T901
Test name
Test status
Simulation time 620727402 ps
CPU time 0.96 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:40 PM PDT 24
Peak memory 201376 kb
Host smart-909956af-bc32-48ca-a27b-c0d7c187c4ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769177984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2769177984
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3068718801
Short name T805
Test name
Test status
Simulation time 398325958 ps
CPU time 1.15 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:35 PM PDT 24
Peak memory 201284 kb
Host smart-2e333d82-810b-47e7-8943-3b500f7506ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068718801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3068718801
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.579324890
Short name T54
Test name
Test status
Simulation time 3390793409 ps
CPU time 8.23 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:41 PM PDT 24
Peak memory 201612 kb
Host smart-c6d6af3f-3357-4215-a2fd-3d1481505e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579324890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.579324890
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3967951331
Short name T862
Test name
Test status
Simulation time 352931908 ps
CPU time 2.3 seconds
Started Aug 02 05:21:33 PM PDT 24
Finished Aug 02 05:21:35 PM PDT 24
Peak memory 201660 kb
Host smart-d8088a42-554f-4e68-af84-ef41b7977d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967951331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3967951331
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1272131976
Short name T831
Test name
Test status
Simulation time 8079131090 ps
CPU time 19.52 seconds
Started Aug 02 05:21:33 PM PDT 24
Finished Aug 02 05:21:53 PM PDT 24
Peak memory 201636 kb
Host smart-59f08b1a-c13e-4985-9dfa-30c1da02b7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272131976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1272131976
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3727530629
Short name T905
Test name
Test status
Simulation time 793988949 ps
CPU time 1.1 seconds
Started Aug 02 05:21:40 PM PDT 24
Finished Aug 02 05:21:41 PM PDT 24
Peak memory 201524 kb
Host smart-a45a438c-ada5-44db-b561-07b36c4a786d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727530629 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3727530629
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4107616413
Short name T137
Test name
Test status
Simulation time 421567394 ps
CPU time 1.09 seconds
Started Aug 02 05:21:35 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201280 kb
Host smart-da0481b2-b5c5-4377-af92-e6dde7c4e317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107616413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.4107616413
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3877548104
Short name T840
Test name
Test status
Simulation time 467744866 ps
CPU time 1.05 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:33 PM PDT 24
Peak memory 201380 kb
Host smart-75d6e2c8-7d4b-4cf1-b8d4-ad30d9f38bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877548104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3877548104
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3838478473
Short name T142
Test name
Test status
Simulation time 2588405584 ps
CPU time 3.48 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201488 kb
Host smart-a79346fd-6dd1-4b8a-bf10-6fbbbbc61cd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838478473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3838478473
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.847745520
Short name T842
Test name
Test status
Simulation time 366991601 ps
CPU time 3.03 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:42 PM PDT 24
Peak memory 210880 kb
Host smart-7266732d-2750-4358-9aa3-4e424912c958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847745520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.847745520
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1360288364
Short name T857
Test name
Test status
Simulation time 8508342000 ps
CPU time 7.43 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:47 PM PDT 24
Peak memory 201644 kb
Host smart-53087676-8547-43a3-98fc-4713c5a912e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360288364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1360288364
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2594563076
Short name T91
Test name
Test status
Simulation time 438288280 ps
CPU time 1.78 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201560 kb
Host smart-df04b102-1f18-439a-b6da-281912e3e3bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594563076 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2594563076
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.162189104
Short name T130
Test name
Test status
Simulation time 456199059 ps
CPU time 1.34 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:35 PM PDT 24
Peak memory 201264 kb
Host smart-9d5e6017-1561-452f-bb08-12092ace3a53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162189104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.162189104
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1964281487
Short name T914
Test name
Test status
Simulation time 384796398 ps
CPU time 1.52 seconds
Started Aug 02 05:21:37 PM PDT 24
Finished Aug 02 05:21:39 PM PDT 24
Peak memory 201416 kb
Host smart-eaebc7dc-347f-474e-abfa-ac366cfa45fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964281487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1964281487
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4058212738
Short name T847
Test name
Test status
Simulation time 2235216655 ps
CPU time 3.28 seconds
Started Aug 02 05:21:36 PM PDT 24
Finished Aug 02 05:21:40 PM PDT 24
Peak memory 201472 kb
Host smart-bd38818b-7f1b-47e8-b1a5-b5dde8ebb958
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058212738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4058212738
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4142219371
Short name T865
Test name
Test status
Simulation time 1033449044 ps
CPU time 1.55 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201720 kb
Host smart-4131c37d-90b0-4f7d-8327-8d585dcfd8a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142219371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4142219371
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2822584571
Short name T77
Test name
Test status
Simulation time 4404830024 ps
CPU time 6.62 seconds
Started Aug 02 05:21:33 PM PDT 24
Finished Aug 02 05:21:39 PM PDT 24
Peak memory 201696 kb
Host smart-62d982de-38fd-43bb-8227-c42d5da5499c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822584571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2822584571
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2144984155
Short name T915
Test name
Test status
Simulation time 352074202 ps
CPU time 1.64 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:34 PM PDT 24
Peak memory 201536 kb
Host smart-61c10d82-b9e6-499d-8259-6dae5e17123a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144984155 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2144984155
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1867469123
Short name T140
Test name
Test status
Simulation time 359075527 ps
CPU time 1.63 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201424 kb
Host smart-fc7b019e-90d2-47be-945e-34a2c9f3bdeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867469123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1867469123
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1479941663
Short name T875
Test name
Test status
Simulation time 411363280 ps
CPU time 1.61 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:36 PM PDT 24
Peak memory 201372 kb
Host smart-3e0dcb2c-b2b7-4e53-a137-26e26b62eae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479941663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1479941663
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2068860873
Short name T879
Test name
Test status
Simulation time 2391471321 ps
CPU time 2.13 seconds
Started Aug 02 05:21:34 PM PDT 24
Finished Aug 02 05:21:37 PM PDT 24
Peak memory 201448 kb
Host smart-3dd8a5ad-f45f-411c-9e4e-b7fd98aebb07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068860873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2068860873
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.243726330
Short name T76
Test name
Test status
Simulation time 590525751 ps
CPU time 1.84 seconds
Started Aug 02 05:21:32 PM PDT 24
Finished Aug 02 05:21:34 PM PDT 24
Peak memory 201644 kb
Host smart-4e10f11e-046c-43fb-8888-7457ec7ed941
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243726330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.243726330
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3664390983
Short name T896
Test name
Test status
Simulation time 4596811567 ps
CPU time 6.89 seconds
Started Aug 02 05:21:33 PM PDT 24
Finished Aug 02 05:21:40 PM PDT 24
Peak memory 201620 kb
Host smart-e15292fe-8c85-4fc3-bbd0-7a702ee4bd96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664390983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3664390983
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3710637895
Short name T71
Test name
Test status
Simulation time 368039461 ps
CPU time 1.37 seconds
Started Aug 02 05:21:38 PM PDT 24
Finished Aug 02 05:21:40 PM PDT 24
Peak memory 201512 kb
Host smart-3115bb87-614a-4cad-b6d0-33e1b544d08e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710637895 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3710637895
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4247386949
Short name T143
Test name
Test status
Simulation time 326422439 ps
CPU time 1.46 seconds
Started Aug 02 05:21:40 PM PDT 24
Finished Aug 02 05:21:42 PM PDT 24
Peak memory 201352 kb
Host smart-9ac81f77-c1c7-49ed-9a7a-d717b9565473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247386949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4247386949
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2985490666
Short name T833
Test name
Test status
Simulation time 363607653 ps
CPU time 1.44 seconds
Started Aug 02 05:21:39 PM PDT 24
Finished Aug 02 05:21:41 PM PDT 24
Peak memory 201392 kb
Host smart-7d753690-8b01-4896-9437-c1eaef2437db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985490666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2985490666
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2603813101
Short name T844
Test name
Test status
Simulation time 2773047818 ps
CPU time 2.27 seconds
Started Aug 02 05:21:42 PM PDT 24
Finished Aug 02 05:21:44 PM PDT 24
Peak memory 201412 kb
Host smart-cd5088b3-48cb-42ee-9d98-e73e511adbae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603813101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2603813101
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3556450435
Short name T848
Test name
Test status
Simulation time 450517577 ps
CPU time 2.54 seconds
Started Aug 02 05:21:41 PM PDT 24
Finished Aug 02 05:21:44 PM PDT 24
Peak memory 201636 kb
Host smart-e77edc99-182a-45ed-91ca-055597b4289a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556450435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3556450435
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3749041494
Short name T58
Test name
Test status
Simulation time 4511662093 ps
CPU time 6.91 seconds
Started Aug 02 05:21:44 PM PDT 24
Finished Aug 02 05:21:51 PM PDT 24
Peak memory 201716 kb
Host smart-46b10748-f59a-4b60-ab93-f933eeb93b52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749041494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3749041494
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2889652794
Short name T120
Test name
Test status
Simulation time 486553608 ps
CPU time 1.53 seconds
Started Aug 02 05:22:30 PM PDT 24
Finished Aug 02 05:22:32 PM PDT 24
Peak memory 201232 kb
Host smart-c91eee74-5367-49ed-ae02-b754f472164b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889652794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2889652794
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2398421017
Short name T595
Test name
Test status
Simulation time 227394717718 ps
CPU time 436.17 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:29:44 PM PDT 24
Peak memory 201508 kb
Host smart-10e7e3e7-603d-4691-9b6b-c6d65f062208
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398421017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2398421017
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4039116434
Short name T658
Test name
Test status
Simulation time 197001922712 ps
CPU time 114.58 seconds
Started Aug 02 05:22:26 PM PDT 24
Finished Aug 02 05:24:21 PM PDT 24
Peak memory 201512 kb
Host smart-b845e1f7-4cf4-4e31-895f-00077ea6cea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039116434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4039116434
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2330219565
Short name T589
Test name
Test status
Simulation time 500097782996 ps
CPU time 579.93 seconds
Started Aug 02 05:22:26 PM PDT 24
Finished Aug 02 05:32:06 PM PDT 24
Peak memory 201504 kb
Host smart-def0c711-0521-440d-ac02-f5fc9e7d4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330219565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2330219565
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3482806083
Short name T413
Test name
Test status
Simulation time 488055615506 ps
CPU time 1146.16 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:41:28 PM PDT 24
Peak memory 201400 kb
Host smart-bdcae5af-28c2-4922-8ee0-ecfbef1ed192
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482806083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3482806083
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2225866434
Short name T3
Test name
Test status
Simulation time 165185943682 ps
CPU time 96.46 seconds
Started Aug 02 05:22:26 PM PDT 24
Finished Aug 02 05:24:02 PM PDT 24
Peak memory 201520 kb
Host smart-c3d3c04f-74ca-419a-b292-0a16a6ad5aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225866434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2225866434
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2092320151
Short name T771
Test name
Test status
Simulation time 163431612381 ps
CPU time 385.69 seconds
Started Aug 02 05:22:23 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 201468 kb
Host smart-ee448ffa-5f2b-415e-968c-56af81eae221
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092320151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2092320151
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2016901102
Short name T598
Test name
Test status
Simulation time 188053018549 ps
CPU time 209.61 seconds
Started Aug 02 05:22:25 PM PDT 24
Finished Aug 02 05:25:54 PM PDT 24
Peak memory 201480 kb
Host smart-96259476-3dbb-4421-8396-b1b2cb4f8335
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016901102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2016901102
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1022956776
Short name T582
Test name
Test status
Simulation time 611492528881 ps
CPU time 362.23 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:28:30 PM PDT 24
Peak memory 201512 kb
Host smart-ad12f310-5872-46b2-a97f-817acc52743b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022956776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1022956776
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1964773282
Short name T388
Test name
Test status
Simulation time 94208370471 ps
CPU time 289.42 seconds
Started Aug 02 05:22:26 PM PDT 24
Finished Aug 02 05:27:15 PM PDT 24
Peak memory 201876 kb
Host smart-f24b8aba-1c1f-47b5-ab4a-d0804305a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964773282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1964773282
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3678519720
Short name T721
Test name
Test status
Simulation time 33485465115 ps
CPU time 9.02 seconds
Started Aug 02 05:22:27 PM PDT 24
Finished Aug 02 05:22:36 PM PDT 24
Peak memory 201416 kb
Host smart-639a1887-2260-46a5-a451-b2f6985164b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678519720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3678519720
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1272306105
Short name T714
Test name
Test status
Simulation time 4803445483 ps
CPU time 11.53 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:22:40 PM PDT 24
Peak memory 201424 kb
Host smart-1a52543d-f8c5-4ba5-bc1b-f0c4858e997b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272306105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1272306105
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1590316156
Short name T81
Test name
Test status
Simulation time 4428245594 ps
CPU time 5.74 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:26 PM PDT 24
Peak memory 217224 kb
Host smart-5e278e9e-ec89-4f96-9fdb-8f691fbd796a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590316156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1590316156
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3351674320
Short name T699
Test name
Test status
Simulation time 5808717360 ps
CPU time 7 seconds
Started Aug 02 05:22:24 PM PDT 24
Finished Aug 02 05:22:31 PM PDT 24
Peak memory 201372 kb
Host smart-8eba12aa-62c8-4856-b8b6-3c29e3f5fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351674320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3351674320
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2197913913
Short name T635
Test name
Test status
Simulation time 191213674491 ps
CPU time 404.24 seconds
Started Aug 02 05:22:26 PM PDT 24
Finished Aug 02 05:29:10 PM PDT 24
Peak memory 201436 kb
Host smart-ffc0e1ab-6b8b-4eca-8443-a4dc3814b403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197913913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2197913913
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.4319030
Short name T707
Test name
Test status
Simulation time 466551856 ps
CPU time 0.76 seconds
Started Aug 02 05:22:32 PM PDT 24
Finished Aug 02 05:22:33 PM PDT 24
Peak memory 201336 kb
Host smart-8065f55e-b746-4372-a97c-cdcf9ff97218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4319030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4319030
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3267051518
Short name T193
Test name
Test status
Simulation time 322319669469 ps
CPU time 87.64 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:23:56 PM PDT 24
Peak memory 201404 kb
Host smart-6ccf780f-918c-4eb4-8334-6ebf9df231e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267051518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3267051518
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3142205333
Short name T381
Test name
Test status
Simulation time 167375700297 ps
CPU time 382.33 seconds
Started Aug 02 05:22:32 PM PDT 24
Finished Aug 02 05:28:55 PM PDT 24
Peak memory 201484 kb
Host smart-aad4346b-74b3-45ca-b66e-9c8fc9e00f7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142205333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3142205333
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3633308780
Short name T335
Test name
Test status
Simulation time 163094355607 ps
CPU time 344.11 seconds
Started Aug 02 05:22:31 PM PDT 24
Finished Aug 02 05:28:15 PM PDT 24
Peak memory 201548 kb
Host smart-865fb165-ff1c-44c8-a1e0-d94b21e64d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633308780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3633308780
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1274893787
Short name T459
Test name
Test status
Simulation time 489318782666 ps
CPU time 89.68 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:23:58 PM PDT 24
Peak memory 201484 kb
Host smart-3eaf2185-1d2f-4d5f-95d9-d6f13938ad92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274893787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1274893787
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1237593873
Short name T575
Test name
Test status
Simulation time 176707654276 ps
CPU time 111.36 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:24:19 PM PDT 24
Peak memory 201528 kb
Host smart-e982728f-bb86-420c-97e0-f3a63a058f4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237593873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1237593873
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2558037129
Short name T662
Test name
Test status
Simulation time 583866149366 ps
CPU time 1344.7 seconds
Started Aug 02 05:22:31 PM PDT 24
Finished Aug 02 05:44:56 PM PDT 24
Peak memory 201548 kb
Host smart-2d6e76c3-9f6a-4c21-8708-e8e48a8a647f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558037129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2558037129
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2159727741
Short name T775
Test name
Test status
Simulation time 110912472718 ps
CPU time 476.66 seconds
Started Aug 02 05:22:30 PM PDT 24
Finished Aug 02 05:30:26 PM PDT 24
Peak memory 201864 kb
Host smart-75b22395-d62b-45b7-87ac-e36cf52d89ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159727741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2159727741
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3875007834
Short name T791
Test name
Test status
Simulation time 28714740547 ps
CPU time 9.22 seconds
Started Aug 02 05:22:27 PM PDT 24
Finished Aug 02 05:22:37 PM PDT 24
Peak memory 201416 kb
Host smart-194b7aad-e5b1-4c70-af67-4cae88ef3393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875007834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3875007834
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3830169849
Short name T692
Test name
Test status
Simulation time 3958956348 ps
CPU time 4.41 seconds
Started Aug 02 05:22:36 PM PDT 24
Finished Aug 02 05:22:40 PM PDT 24
Peak memory 201404 kb
Host smart-f9f222ec-6b02-45e0-b75f-dc27d02d0cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830169849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3830169849
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3056901033
Short name T772
Test name
Test status
Simulation time 5963462981 ps
CPU time 4.51 seconds
Started Aug 02 05:22:29 PM PDT 24
Finished Aug 02 05:22:34 PM PDT 24
Peak memory 201368 kb
Host smart-39cfb798-36ba-4702-a007-a565a54e9045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056901033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3056901033
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.932731188
Short name T461
Test name
Test status
Simulation time 391512187 ps
CPU time 0.87 seconds
Started Aug 02 05:22:51 PM PDT 24
Finished Aug 02 05:22:52 PM PDT 24
Peak memory 201244 kb
Host smart-898053bc-5845-4e3d-abff-250ef2c71ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932731188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.932731188
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1179672697
Short name T96
Test name
Test status
Simulation time 164048357878 ps
CPU time 314.42 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:27:58 PM PDT 24
Peak memory 201504 kb
Host smart-4f852556-aa05-49a0-bc0f-521172b254da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179672697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1179672697
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.786117660
Short name T350
Test name
Test status
Simulation time 167116488670 ps
CPU time 375.33 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:29:00 PM PDT 24
Peak memory 201528 kb
Host smart-40405f5a-780e-4765-b9f6-c51dbc85834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786117660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.786117660
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3981197607
Short name T580
Test name
Test status
Simulation time 488151955786 ps
CPU time 1086.48 seconds
Started Aug 02 05:22:55 PM PDT 24
Finished Aug 02 05:41:01 PM PDT 24
Peak memory 201496 kb
Host smart-e9dc6709-684f-4f6e-abe2-23dc5e30efb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981197607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3981197607
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2105038829
Short name T186
Test name
Test status
Simulation time 337194834049 ps
CPU time 200.31 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:26:18 PM PDT 24
Peak memory 201504 kb
Host smart-191ce8c7-550d-4500-84ec-f66ba2764abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105038829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2105038829
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2508630692
Short name T409
Test name
Test status
Simulation time 331678820012 ps
CPU time 694.95 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:34:32 PM PDT 24
Peak memory 201464 kb
Host smart-d8944bc3-e383-4635-9f53-6e7f3ea64ace
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508630692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2508630692
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.661228591
Short name T27
Test name
Test status
Simulation time 179413711319 ps
CPU time 203.42 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:26:20 PM PDT 24
Peak memory 201440 kb
Host smart-9e0b66a2-a20f-4ea1-8ae4-354633d6698a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661228591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.661228591
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2915817004
Short name T697
Test name
Test status
Simulation time 215104389628 ps
CPU time 65.05 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:24:07 PM PDT 24
Peak memory 201456 kb
Host smart-2dadcbde-79e4-4f55-9405-b610e43abdc5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915817004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2915817004
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1725013495
Short name T673
Test name
Test status
Simulation time 110773580917 ps
CPU time 417.97 seconds
Started Aug 02 05:22:51 PM PDT 24
Finished Aug 02 05:29:50 PM PDT 24
Peak memory 201872 kb
Host smart-8bdf7572-ba2c-4a51-afb8-ccca24060c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725013495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1725013495
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3383375644
Short name T508
Test name
Test status
Simulation time 33011812554 ps
CPU time 19.46 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:23:17 PM PDT 24
Peak memory 201420 kb
Host smart-66cdf512-d1d9-4ee4-9f68-1ce1e9828a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383375644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3383375644
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2133403295
Short name T649
Test name
Test status
Simulation time 4900998772 ps
CPU time 6.37 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:22:51 PM PDT 24
Peak memory 201404 kb
Host smart-c2e4797b-aed2-4aa0-8774-1c008d0d7997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133403295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2133403295
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2674444177
Short name T531
Test name
Test status
Simulation time 5822772407 ps
CPU time 7.67 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:22:53 PM PDT 24
Peak memory 201392 kb
Host smart-b9d13239-a255-4aaf-82f5-64f7631dc918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674444177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2674444177
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.205067441
Short name T624
Test name
Test status
Simulation time 169655431732 ps
CPU time 381.25 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 201500 kb
Host smart-eed6af41-0080-46cb-9f29-71c98d32dc38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205067441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
205067441
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1995196798
Short name T22
Test name
Test status
Simulation time 53441947991 ps
CPU time 111.23 seconds
Started Aug 02 05:22:54 PM PDT 24
Finished Aug 02 05:24:46 PM PDT 24
Peak memory 209840 kb
Host smart-95e9e59c-43d0-4d3d-8041-41ba2f37f8c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995196798 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1995196798
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1899253410
Short name T713
Test name
Test status
Simulation time 400502186 ps
CPU time 0.82 seconds
Started Aug 02 05:22:55 PM PDT 24
Finished Aug 02 05:22:56 PM PDT 24
Peak memory 201232 kb
Host smart-572e3df3-a714-44a7-b1e2-3301b8b5f457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899253410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1899253410
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3030848643
Short name T251
Test name
Test status
Simulation time 163031898356 ps
CPU time 99.16 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:24:42 PM PDT 24
Peak memory 201480 kb
Host smart-f2e7209b-84e3-4884-bc4e-ce30d407ea90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030848643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3030848643
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.485732020
Short name T174
Test name
Test status
Simulation time 484568435158 ps
CPU time 150.51 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:25:33 PM PDT 24
Peak memory 201468 kb
Host smart-ff9f81eb-0d41-4390-880f-833d025430f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485732020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.485732020
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2970345451
Short name T801
Test name
Test status
Simulation time 328639691923 ps
CPU time 181.21 seconds
Started Aug 02 05:22:50 PM PDT 24
Finished Aug 02 05:25:51 PM PDT 24
Peak memory 201520 kb
Host smart-bb7b391a-ad25-466c-977b-8b41e1deafc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970345451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2970345451
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1398077349
Short name T325
Test name
Test status
Simulation time 161934138744 ps
CPU time 174.78 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:25:52 PM PDT 24
Peak memory 201524 kb
Host smart-73fd4deb-93c1-4805-92cb-0032b2b04e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398077349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1398077349
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3295630460
Short name T769
Test name
Test status
Simulation time 333758085339 ps
CPU time 191.42 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:25:56 PM PDT 24
Peak memory 201440 kb
Host smart-f4e2648a-d9e9-4ad7-a23e-06fb283443c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295630460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3295630460
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1000493630
Short name T419
Test name
Test status
Simulation time 612245391992 ps
CPU time 729.46 seconds
Started Aug 02 05:22:50 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 201472 kb
Host smart-10faef66-eaf7-4dcf-9a44-96c283a6e6a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000493630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1000493630
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.353512435
Short name T410
Test name
Test status
Simulation time 38985155310 ps
CPU time 18.01 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:23:20 PM PDT 24
Peak memory 201368 kb
Host smart-1e28509d-1e03-4906-b21a-b73bc4a74097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353512435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.353512435
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3711668142
Short name T527
Test name
Test status
Simulation time 3101087013 ps
CPU time 2.04 seconds
Started Aug 02 05:22:51 PM PDT 24
Finished Aug 02 05:22:53 PM PDT 24
Peak memory 201368 kb
Host smart-3ba49fc4-a32c-471a-9ff1-2cb7751a41d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711668142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3711668142
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1761146845
Short name T644
Test name
Test status
Simulation time 5620473212 ps
CPU time 12.64 seconds
Started Aug 02 05:22:48 PM PDT 24
Finished Aug 02 05:23:01 PM PDT 24
Peak memory 201312 kb
Host smart-bb0e0dbb-1c02-4ed6-a835-4b5dcf7bcccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761146845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1761146845
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.110478951
Short name T216
Test name
Test status
Simulation time 194615135412 ps
CPU time 121.96 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:24:46 PM PDT 24
Peak memory 201444 kb
Host smart-fdcd4c39-9b0b-4f91-93cd-8211cb8655c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110478951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
110478951
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3627785063
Short name T792
Test name
Test status
Simulation time 83582544231 ps
CPU time 194.15 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:26:03 PM PDT 24
Peak memory 210152 kb
Host smart-832285be-5ab5-42bd-a8d0-55cf5ad75337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627785063 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3627785063
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3288983027
Short name T467
Test name
Test status
Simulation time 443417842 ps
CPU time 1.68 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:23:04 PM PDT 24
Peak memory 201264 kb
Host smart-382adcb7-7125-4ce2-a712-c72308e4dba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288983027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3288983027
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.307355557
Short name T559
Test name
Test status
Simulation time 204250618993 ps
CPU time 369.21 seconds
Started Aug 02 05:22:56 PM PDT 24
Finished Aug 02 05:29:06 PM PDT 24
Peak memory 201516 kb
Host smart-cf278c4f-a1a7-4584-a175-88612c8acbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307355557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.307355557
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.815389659
Short name T333
Test name
Test status
Simulation time 490293486041 ps
CPU time 1164.88 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:42:24 PM PDT 24
Peak memory 201472 kb
Host smart-55bcaceb-4097-4c31-9020-3453e600a2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815389659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.815389659
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1926877336
Short name T454
Test name
Test status
Simulation time 162913659512 ps
CPU time 42.02 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:23:39 PM PDT 24
Peak memory 201548 kb
Host smart-9b592ab6-5091-477a-b347-88935e59b8a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926877336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1926877336
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1882853362
Short name T241
Test name
Test status
Simulation time 168657482446 ps
CPU time 94.97 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:24:37 PM PDT 24
Peak memory 201436 kb
Host smart-16b078af-a08d-4e43-b162-1c9080f87b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882853362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1882853362
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1254072084
Short name T779
Test name
Test status
Simulation time 164085586718 ps
CPU time 46.94 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:23:50 PM PDT 24
Peak memory 201480 kb
Host smart-c749474f-1dcb-47c6-9f28-92b41225f023
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254072084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1254072084
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3653192611
Short name T456
Test name
Test status
Simulation time 606669345740 ps
CPU time 684.1 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 201344 kb
Host smart-ba9dc1c4-95be-4b7f-9510-a529dbb83d55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653192611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3653192611
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2625472983
Short name T369
Test name
Test status
Simulation time 21608428282 ps
CPU time 13.64 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:23:12 PM PDT 24
Peak memory 201372 kb
Host smart-565c9769-3e6e-49da-90e2-598d0bf2778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625472983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2625472983
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1966214037
Short name T689
Test name
Test status
Simulation time 3005470642 ps
CPU time 2.73 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:23:06 PM PDT 24
Peak memory 201352 kb
Host smart-7417e2ac-7540-4930-995c-7b8597168c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966214037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1966214037
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1996721385
Short name T438
Test name
Test status
Simulation time 5855228361 ps
CPU time 13.98 seconds
Started Aug 02 05:22:51 PM PDT 24
Finished Aug 02 05:23:05 PM PDT 24
Peak memory 201372 kb
Host smart-5020a2d4-d362-49d5-829f-5f77a271459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996721385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1996721385
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.490861223
Short name T176
Test name
Test status
Simulation time 426236912310 ps
CPU time 574.07 seconds
Started Aug 02 05:22:55 PM PDT 24
Finished Aug 02 05:32:29 PM PDT 24
Peak memory 201852 kb
Host smart-a0b1d1ec-ab85-4720-99f1-49bccf851c84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490861223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
490861223
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1238487160
Short name T756
Test name
Test status
Simulation time 47463339102 ps
CPU time 28.9 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:23:32 PM PDT 24
Peak memory 210788 kb
Host smart-14782e0c-9bd5-48f5-906a-da6c0664848b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238487160 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1238487160
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1374428748
Short name T485
Test name
Test status
Simulation time 534695302 ps
CPU time 0.91 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:23:06 PM PDT 24
Peak memory 201260 kb
Host smart-437f5640-0216-4cbc-afe7-1c39ee27cc5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374428748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1374428748
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.4201050699
Short name T314
Test name
Test status
Simulation time 337274736147 ps
CPU time 767.63 seconds
Started Aug 02 05:23:06 PM PDT 24
Finished Aug 02 05:35:54 PM PDT 24
Peak memory 201516 kb
Host smart-895e32e5-bb0b-4ebe-8fde-7a1d88196429
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201050699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.4201050699
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1135510920
Short name T320
Test name
Test status
Simulation time 176150029215 ps
CPU time 124.45 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:25:02 PM PDT 24
Peak memory 201464 kb
Host smart-26aa354e-9486-4334-a71f-36f4a5b012af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135510920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1135510920
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1811697946
Short name T201
Test name
Test status
Simulation time 484570047898 ps
CPU time 283.03 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:27:42 PM PDT 24
Peak memory 201488 kb
Host smart-eecbefb1-1cc6-48b4-bc7f-406cc2a553a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811697946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1811697946
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3565749208
Short name T29
Test name
Test status
Simulation time 167728329085 ps
CPU time 369.95 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:29:08 PM PDT 24
Peak memory 201436 kb
Host smart-b75bc737-6f4a-4bd2-a963-dafceb7fff1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565749208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3565749208
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.961131549
Short name T781
Test name
Test status
Simulation time 322818526147 ps
CPU time 46.18 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:23:49 PM PDT 24
Peak memory 201464 kb
Host smart-27b92c01-a507-4efa-9c39-b0aa2aee727b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=961131549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.961131549
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2913597073
Short name T155
Test name
Test status
Simulation time 186104587639 ps
CPU time 110.06 seconds
Started Aug 02 05:22:56 PM PDT 24
Finished Aug 02 05:24:46 PM PDT 24
Peak memory 201480 kb
Host smart-5c45f0a3-54b8-4403-b185-6f81f3b901fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913597073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2913597073
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3732937167
Short name T730
Test name
Test status
Simulation time 200065655782 ps
CPU time 241.95 seconds
Started Aug 02 05:23:08 PM PDT 24
Finished Aug 02 05:27:10 PM PDT 24
Peak memory 201432 kb
Host smart-78e01200-1a01-4c8a-9f3f-9b1487c46deb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732937167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3732937167
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3270179940
Short name T510
Test name
Test status
Simulation time 97899356964 ps
CPU time 492.03 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:31:14 PM PDT 24
Peak memory 201900 kb
Host smart-245afe27-5f60-4e41-8924-500c707c69db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270179940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3270179940
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2977254249
Short name T577
Test name
Test status
Simulation time 31749021226 ps
CPU time 76.93 seconds
Started Aug 02 05:23:06 PM PDT 24
Finished Aug 02 05:24:23 PM PDT 24
Peak memory 201400 kb
Host smart-4f16cb4e-08fe-45c6-8c08-128de9a74b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977254249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2977254249
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2064070692
Short name T560
Test name
Test status
Simulation time 3714412818 ps
CPU time 8.69 seconds
Started Aug 02 05:23:00 PM PDT 24
Finished Aug 02 05:23:09 PM PDT 24
Peak memory 201364 kb
Host smart-bbcb855e-6c5d-42dc-ac4f-0cee21c287f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064070692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2064070692
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.4238823943
Short name T663
Test name
Test status
Simulation time 5860025503 ps
CPU time 3.91 seconds
Started Aug 02 05:22:51 PM PDT 24
Finished Aug 02 05:22:55 PM PDT 24
Peak memory 201380 kb
Host smart-3bacda37-f653-4452-a289-5ace606ce11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238823943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.4238823943
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.279463197
Short name T117
Test name
Test status
Simulation time 160466602059 ps
CPU time 381.32 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:29:23 PM PDT 24
Peak memory 201520 kb
Host smart-d1614794-b4cd-4eb1-ae83-6b72d36fe20d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279463197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
279463197
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2793656357
Short name T638
Test name
Test status
Simulation time 395231102 ps
CPU time 0.69 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:23:05 PM PDT 24
Peak memory 201252 kb
Host smart-5ec52e19-2d59-4da0-8ec2-4f9b3f893891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793656357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2793656357
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.20699314
Short name T107
Test name
Test status
Simulation time 484984266631 ps
CPU time 957.21 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:38:56 PM PDT 24
Peak memory 201476 kb
Host smart-1897f16d-8974-4a28-93cf-368ddedfe88e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20699314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gatin
g.20699314
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1206334198
Short name T283
Test name
Test status
Simulation time 328824906663 ps
CPU time 233.83 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:26:52 PM PDT 24
Peak memory 201464 kb
Host smart-b4b77dfe-27ee-45a3-8e1b-d6c2330a001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206334198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1206334198
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.848749263
Short name T472
Test name
Test status
Simulation time 172658895516 ps
CPU time 399.01 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:29:44 PM PDT 24
Peak memory 201512 kb
Host smart-c29a9eae-837c-4e2d-9a7d-bc8604df349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848749263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.848749263
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3121133707
Short name T82
Test name
Test status
Simulation time 491973109714 ps
CPU time 1118.15 seconds
Started Aug 02 05:23:00 PM PDT 24
Finished Aug 02 05:41:38 PM PDT 24
Peak memory 201484 kb
Host smart-a924a233-4fda-4607-b96f-bac510e18362
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121133707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3121133707
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1944726855
Short name T578
Test name
Test status
Simulation time 328808123675 ps
CPU time 184.01 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:26:06 PM PDT 24
Peak memory 201428 kb
Host smart-aa945742-1e95-4f03-9bb5-5cadb9478f93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944726855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1944726855
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3612794086
Short name T276
Test name
Test status
Simulation time 171847524952 ps
CPU time 411.19 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:29:50 PM PDT 24
Peak memory 201360 kb
Host smart-ad12a386-3c56-4c47-a2b1-5f21609ed04d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612794086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3612794086
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3301245175
Short name T546
Test name
Test status
Simulation time 196738254631 ps
CPU time 231.75 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:26:51 PM PDT 24
Peak memory 201356 kb
Host smart-c2efb996-a353-465a-bc87-6656b449cfef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301245175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3301245175
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3334938235
Short name T113
Test name
Test status
Simulation time 46370690352 ps
CPU time 50.27 seconds
Started Aug 02 05:23:01 PM PDT 24
Finished Aug 02 05:23:51 PM PDT 24
Peak memory 201392 kb
Host smart-71553257-0609-438f-9daf-a5e7433dd24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334938235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3334938235
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.188927031
Short name T724
Test name
Test status
Simulation time 4314274023 ps
CPU time 3.14 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:23:03 PM PDT 24
Peak memory 201252 kb
Host smart-0ec4e61d-94eb-4021-a14f-3248fc95e1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188927031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.188927031
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2229206143
Short name T768
Test name
Test status
Simulation time 5968718247 ps
CPU time 4.47 seconds
Started Aug 02 05:22:56 PM PDT 24
Finished Aug 02 05:23:01 PM PDT 24
Peak memory 201392 kb
Host smart-61f1122c-6f7e-4c1d-95df-73dc84f681e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229206143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2229206143
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3698106517
Short name T273
Test name
Test status
Simulation time 175525676902 ps
CPU time 80.66 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:24:25 PM PDT 24
Peak memory 201468 kb
Host smart-840e570a-b6ae-4b94-b301-f2aa2ce9cd92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698106517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3698106517
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.809210686
Short name T274
Test name
Test status
Simulation time 94835357001 ps
CPU time 57.67 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:24:02 PM PDT 24
Peak memory 209848 kb
Host smart-e713afc2-d892-4a61-a77b-533f5b18cfe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809210686 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.809210686
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1141217063
Short name T317
Test name
Test status
Simulation time 345661877915 ps
CPU time 174.09 seconds
Started Aug 02 05:23:09 PM PDT 24
Finished Aug 02 05:26:03 PM PDT 24
Peak memory 201496 kb
Host smart-7ae85163-ae49-4403-b3f9-c9f62d415948
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141217063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1141217063
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1989012536
Short name T355
Test name
Test status
Simulation time 329649649454 ps
CPU time 162.88 seconds
Started Aug 02 05:23:11 PM PDT 24
Finished Aug 02 05:25:54 PM PDT 24
Peak memory 201464 kb
Host smart-88124f5c-487d-47ee-9724-d6fe7b98eb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989012536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1989012536
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1901073156
Short name T374
Test name
Test status
Simulation time 504070085173 ps
CPU time 1075.09 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:41:09 PM PDT 24
Peak memory 201444 kb
Host smart-54e7d6a9-28d0-40a2-a24d-18aee78894d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901073156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1901073156
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1845575455
Short name T568
Test name
Test status
Simulation time 162539615772 ps
CPU time 160.1 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:25:45 PM PDT 24
Peak memory 201488 kb
Host smart-8be974db-3e28-4d48-8093-5c9de581461f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845575455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1845575455
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3564127564
Short name T623
Test name
Test status
Simulation time 323238272586 ps
CPU time 646.46 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:34:00 PM PDT 24
Peak memory 201448 kb
Host smart-09f4604a-d135-4f91-974e-3921167fd6fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564127564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3564127564
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3832259521
Short name T347
Test name
Test status
Simulation time 179456716883 ps
CPU time 381.34 seconds
Started Aug 02 05:23:06 PM PDT 24
Finished Aug 02 05:29:28 PM PDT 24
Peak memory 201520 kb
Host smart-a4e4426e-dbe0-41b7-b018-eca5e2488d77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832259521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3832259521
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2273751944
Short name T416
Test name
Test status
Simulation time 396341385223 ps
CPU time 935.34 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:38:38 PM PDT 24
Peak memory 201508 kb
Host smart-2665f5f8-5ca2-4f5b-8cc4-a5293c258c79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273751944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2273751944
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3462045779
Short name T487
Test name
Test status
Simulation time 101088871244 ps
CPU time 424.86 seconds
Started Aug 02 05:23:07 PM PDT 24
Finished Aug 02 05:30:12 PM PDT 24
Peak memory 201884 kb
Host smart-874e9ced-3482-40a7-b6f5-3de2e5aed3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462045779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3462045779
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1608064500
Short name T748
Test name
Test status
Simulation time 34173717048 ps
CPU time 73.13 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:24:15 PM PDT 24
Peak memory 201356 kb
Host smart-2e6d02ec-72d6-4975-b127-cb2f01e1e4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608064500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1608064500
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.660726957
Short name T525
Test name
Test status
Simulation time 4002710772 ps
CPU time 2.04 seconds
Started Aug 02 05:23:07 PM PDT 24
Finished Aug 02 05:23:10 PM PDT 24
Peak memory 201368 kb
Host smart-b9878739-56b6-4d86-a4b7-18d979a114b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660726957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.660726957
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2902231663
Short name T436
Test name
Test status
Simulation time 5770516490 ps
CPU time 4.1 seconds
Started Aug 02 05:23:00 PM PDT 24
Finished Aug 02 05:23:05 PM PDT 24
Peak memory 201396 kb
Host smart-9cfdca98-30da-426f-98c6-823a5ccdadd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902231663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2902231663
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3366293940
Short name T16
Test name
Test status
Simulation time 150841567896 ps
CPU time 158.87 seconds
Started Aug 02 05:23:12 PM PDT 24
Finished Aug 02 05:25:51 PM PDT 24
Peak memory 210272 kb
Host smart-3476433b-ec15-4c2a-a384-49d8a81da37c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366293940 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3366293940
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3864966248
Short name T79
Test name
Test status
Simulation time 365699373 ps
CPU time 1.52 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:23:06 PM PDT 24
Peak memory 201220 kb
Host smart-f537d005-fbd8-4544-a3a4-a9de3db11664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864966248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3864966248
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1358071912
Short name T737
Test name
Test status
Simulation time 343662578637 ps
CPU time 776.8 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:36:01 PM PDT 24
Peak memory 201476 kb
Host smart-67420610-731d-45ad-98c9-09b4c6a9e774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358071912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1358071912
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.278935663
Short name T153
Test name
Test status
Simulation time 161761805463 ps
CPU time 38.35 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:23:40 PM PDT 24
Peak memory 201440 kb
Host smart-d3b64f80-375c-4084-a66c-831ecd705cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278935663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.278935663
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4091382514
Short name T453
Test name
Test status
Simulation time 326039655665 ps
CPU time 763.16 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:35:46 PM PDT 24
Peak memory 201520 kb
Host smart-c95bc464-8bce-41ff-b935-23483453ecf3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091382514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.4091382514
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.816895039
Short name T219
Test name
Test status
Simulation time 322990981997 ps
CPU time 654.57 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:33:58 PM PDT 24
Peak memory 201476 kb
Host smart-e005aebd-6308-48d1-bbee-440e1ae507ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816895039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.816895039
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1000550908
Short name T103
Test name
Test status
Simulation time 170115224564 ps
CPU time 214.52 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:26:34 PM PDT 24
Peak memory 201424 kb
Host smart-f3cca261-4373-4d26-b600-943919443e5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000550908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1000550908
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2031020442
Short name T192
Test name
Test status
Simulation time 551402209094 ps
CPU time 275.4 seconds
Started Aug 02 05:22:58 PM PDT 24
Finished Aug 02 05:27:34 PM PDT 24
Peak memory 201500 kb
Host smart-e1e90893-7a55-464c-b648-48f82ff05fc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031020442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2031020442
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.527912922
Short name T764
Test name
Test status
Simulation time 388683189403 ps
CPU time 447.9 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:30:34 PM PDT 24
Peak memory 201436 kb
Host smart-a4d3e9fb-8395-455f-9fbd-a8d2850310e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527912922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.527912922
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2442772186
Short name T386
Test name
Test status
Simulation time 24306183359 ps
CPU time 26.1 seconds
Started Aug 02 05:23:01 PM PDT 24
Finished Aug 02 05:23:27 PM PDT 24
Peak memory 201392 kb
Host smart-6afa3929-8dd8-495e-a0d5-bdf38bf9dff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442772186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2442772186
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1840690726
Short name T537
Test name
Test status
Simulation time 5231892606 ps
CPU time 3.68 seconds
Started Aug 02 05:23:16 PM PDT 24
Finished Aug 02 05:23:20 PM PDT 24
Peak memory 201440 kb
Host smart-d1d4ad57-dfa2-4d1e-a5bf-71136ed86f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840690726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1840690726
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2699449582
Short name T710
Test name
Test status
Simulation time 5783095528 ps
CPU time 4.21 seconds
Started Aug 02 05:23:14 PM PDT 24
Finished Aug 02 05:23:19 PM PDT 24
Peak memory 201404 kb
Host smart-f9225d16-e8b7-427a-8929-17bf65220676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699449582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2699449582
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2928362524
Short name T542
Test name
Test status
Simulation time 262460414998 ps
CPU time 561.55 seconds
Started Aug 02 05:23:09 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 201528 kb
Host smart-a2592fbe-b4f7-45cf-810a-acf6c969490a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928362524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2928362524
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3168582900
Short name T102
Test name
Test status
Simulation time 283076617406 ps
CPU time 212.95 seconds
Started Aug 02 05:23:10 PM PDT 24
Finished Aug 02 05:26:43 PM PDT 24
Peak memory 210264 kb
Host smart-7c5173d1-eff7-4542-a1d7-64eff07fbaac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168582900 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3168582900
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.983576641
Short name T720
Test name
Test status
Simulation time 312015947 ps
CPU time 0.9 seconds
Started Aug 02 05:23:09 PM PDT 24
Finished Aug 02 05:23:10 PM PDT 24
Peak memory 201256 kb
Host smart-24baa7e0-bcae-4420-9688-a588ffb77fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983576641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.983576641
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1519278050
Short name T266
Test name
Test status
Simulation time 319157615849 ps
CPU time 506.28 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:31:32 PM PDT 24
Peak memory 201516 kb
Host smart-44de1268-b2bf-4100-9ed3-f7308e49e209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519278050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1519278050
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4130284909
Short name T681
Test name
Test status
Simulation time 325749414011 ps
CPU time 697.26 seconds
Started Aug 02 05:22:59 PM PDT 24
Finished Aug 02 05:34:36 PM PDT 24
Peak memory 201468 kb
Host smart-6e1ed97e-2f49-49c0-9db9-5c0b8478fa73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130284909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4130284909
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.892370111
Short name T118
Test name
Test status
Simulation time 332156903816 ps
CPU time 776.1 seconds
Started Aug 02 05:23:19 PM PDT 24
Finished Aug 02 05:36:15 PM PDT 24
Peak memory 201592 kb
Host smart-1d6f847d-3b84-4030-b66f-f6a56d9409f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892370111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.892370111
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2987084398
Short name T502
Test name
Test status
Simulation time 320449847731 ps
CPU time 318.26 seconds
Started Aug 02 05:23:15 PM PDT 24
Finished Aug 02 05:28:33 PM PDT 24
Peak memory 201460 kb
Host smart-ae4fb69c-36aa-447a-b5ca-ae3b96cfed05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987084398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2987084398
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1773586748
Short name T680
Test name
Test status
Simulation time 561460605376 ps
CPU time 593.72 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:33:07 PM PDT 24
Peak memory 201452 kb
Host smart-e984e564-8e9e-4ef1-8d63-2022f426e39c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773586748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1773586748
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2245185265
Short name T108
Test name
Test status
Simulation time 602205086571 ps
CPU time 356.98 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:29:00 PM PDT 24
Peak memory 201452 kb
Host smart-722ff836-4d87-44c8-9352-fe568d5d1046
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245185265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2245185265
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.924144174
Short name T366
Test name
Test status
Simulation time 113520685951 ps
CPU time 471.87 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:30:55 PM PDT 24
Peak memory 201744 kb
Host smart-196362d3-0386-4a1e-ab24-73c2438e9b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924144174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.924144174
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2654252578
Short name T786
Test name
Test status
Simulation time 34449268872 ps
CPU time 9.13 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:23:11 PM PDT 24
Peak memory 201344 kb
Host smart-e5749d2f-e669-430d-a1fb-161b50edd40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654252578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2654252578
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1465377917
Short name T466
Test name
Test status
Simulation time 4765186969 ps
CPU time 11.31 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:23:17 PM PDT 24
Peak memory 201308 kb
Host smart-c0baabec-d1e9-439e-bc07-70c98a638e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465377917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1465377917
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3083876694
Short name T370
Test name
Test status
Simulation time 5787661543 ps
CPU time 14.56 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:23:18 PM PDT 24
Peak memory 201356 kb
Host smart-8dfe9480-c95a-44a5-a149-b11d1d7f4e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083876694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3083876694
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3657436921
Short name T334
Test name
Test status
Simulation time 355071102971 ps
CPU time 218.07 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:26:43 PM PDT 24
Peak memory 201568 kb
Host smart-18a336b9-81b6-4086-b5f8-a93ac3c610ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657436921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3657436921
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.523704786
Short name T800
Test name
Test status
Simulation time 335276597 ps
CPU time 0.72 seconds
Started Aug 02 05:23:11 PM PDT 24
Finished Aug 02 05:23:11 PM PDT 24
Peak memory 201280 kb
Host smart-f8429a4f-2a06-437f-9fae-81ce24a55b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523704786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.523704786
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3234133083
Short name T761
Test name
Test status
Simulation time 185382650609 ps
CPU time 45.19 seconds
Started Aug 02 05:23:02 PM PDT 24
Finished Aug 02 05:23:48 PM PDT 24
Peak memory 201480 kb
Host smart-f6f00e7e-bbfc-43f4-97c3-b60e13d35f3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234133083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3234133083
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1428509846
Short name T182
Test name
Test status
Simulation time 368217563115 ps
CPU time 56.2 seconds
Started Aug 02 05:23:19 PM PDT 24
Finished Aug 02 05:24:15 PM PDT 24
Peak memory 201548 kb
Host smart-1d737f64-19d5-4c02-bd77-09ee84d09355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428509846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1428509846
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1535650638
Short name T168
Test name
Test status
Simulation time 490322994380 ps
CPU time 175.57 seconds
Started Aug 02 05:23:17 PM PDT 24
Finished Aug 02 05:26:12 PM PDT 24
Peak memory 201452 kb
Host smart-360c4cec-6b38-41c2-91b0-23ef8598f6f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535650638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1535650638
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2074504068
Short name T149
Test name
Test status
Simulation time 484831119907 ps
CPU time 528.9 seconds
Started Aug 02 05:23:16 PM PDT 24
Finished Aug 02 05:32:06 PM PDT 24
Peak memory 201592 kb
Host smart-d41b85ea-d84e-445f-a825-eece04b14161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074504068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2074504068
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3267662559
Short name T83
Test name
Test status
Simulation time 163075629831 ps
CPU time 379.85 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:29:25 PM PDT 24
Peak memory 201440 kb
Host smart-b4d9674b-bf50-436f-9cca-3ab3d4daebc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267662559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3267662559
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1618391190
Short name T701
Test name
Test status
Simulation time 195948209722 ps
CPU time 433.91 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:30:27 PM PDT 24
Peak memory 201524 kb
Host smart-8e4e6787-f706-40f2-913d-419840d75536
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618391190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1618391190
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3857363318
Short name T702
Test name
Test status
Simulation time 124809310990 ps
CPU time 516.24 seconds
Started Aug 02 05:23:15 PM PDT 24
Finished Aug 02 05:31:51 PM PDT 24
Peak memory 201948 kb
Host smart-63b84b2a-d627-4ca7-a622-1a9dfe9a0c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857363318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3857363318
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2549368165
Short name T507
Test name
Test status
Simulation time 26573399388 ps
CPU time 13.96 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:23:18 PM PDT 24
Peak memory 201400 kb
Host smart-7dec2c3b-c8be-44ac-a43d-4728ad45ef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549368165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2549368165
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2570278580
Short name T585
Test name
Test status
Simulation time 4770543214 ps
CPU time 2.88 seconds
Started Aug 02 05:23:01 PM PDT 24
Finished Aug 02 05:23:04 PM PDT 24
Peak memory 201368 kb
Host smart-aa3b58e1-9648-4127-a6f1-1f09607f42fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570278580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2570278580
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.753479601
Short name T671
Test name
Test status
Simulation time 5781245276 ps
CPU time 8.57 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:23:14 PM PDT 24
Peak memory 201364 kb
Host smart-ffdef4f0-2f6f-46e5-ab30-158d3f131002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753479601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.753479601
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3675562530
Short name T42
Test name
Test status
Simulation time 17789606035 ps
CPU time 37.77 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:23:43 PM PDT 24
Peak memory 209868 kb
Host smart-b9c01d5c-0771-488a-acf1-06eaab642c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675562530 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3675562530
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1538632596
Short name T486
Test name
Test status
Simulation time 328867844 ps
CPU time 1.29 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:23:07 PM PDT 24
Peak memory 201204 kb
Host smart-f02630d7-cc06-44fc-8fe1-2ad4517e1744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538632596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1538632596
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3134029317
Short name T338
Test name
Test status
Simulation time 162383343678 ps
CPU time 385.79 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:29:39 PM PDT 24
Peak memory 201452 kb
Host smart-2b2015c7-516d-47da-95fa-abfb91953dbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134029317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3134029317
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.858632789
Short name T351
Test name
Test status
Simulation time 335270320566 ps
CPU time 202.69 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:26:36 PM PDT 24
Peak memory 201476 kb
Host smart-556566a1-0560-4638-99bf-318f0d060769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858632789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.858632789
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2710819009
Short name T471
Test name
Test status
Simulation time 321993409673 ps
CPU time 122.97 seconds
Started Aug 02 05:23:17 PM PDT 24
Finished Aug 02 05:25:20 PM PDT 24
Peak memory 201508 kb
Host smart-40861989-2865-451e-95fd-29b6d1aa96cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710819009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2710819009
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1161407654
Short name T352
Test name
Test status
Simulation time 167664085304 ps
CPU time 181.11 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:26:06 PM PDT 24
Peak memory 201472 kb
Host smart-9ff03a15-a18c-4f93-99b3-dbf849b2217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161407654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1161407654
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2441073239
Short name T562
Test name
Test status
Simulation time 483440976654 ps
CPU time 277.64 seconds
Started Aug 02 05:23:21 PM PDT 24
Finished Aug 02 05:27:59 PM PDT 24
Peak memory 201440 kb
Host smart-1480262f-9b65-4085-bc28-cacaddf8caae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441073239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2441073239
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.369928080
Short name T278
Test name
Test status
Simulation time 358207433520 ps
CPU time 200.94 seconds
Started Aug 02 05:23:16 PM PDT 24
Finished Aug 02 05:26:37 PM PDT 24
Peak memory 201484 kb
Host smart-a366a1c2-1684-428b-ba3c-670b6dae89aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369928080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.369928080
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.415736735
Short name T511
Test name
Test status
Simulation time 607543524359 ps
CPU time 280.41 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:27:44 PM PDT 24
Peak memory 201440 kb
Host smart-2311a270-2b40-49ba-bf61-b42a4a0a7a28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415736735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.415736735
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.292690717
Short name T238
Test name
Test status
Simulation time 113441018878 ps
CPU time 413.15 seconds
Started Aug 02 05:23:16 PM PDT 24
Finished Aug 02 05:30:10 PM PDT 24
Peak memory 201848 kb
Host smart-7d0f04d3-db56-4ba1-9782-89288371faf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292690717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.292690717
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2168446588
Short name T100
Test name
Test status
Simulation time 24472096230 ps
CPU time 36.57 seconds
Started Aug 02 05:23:17 PM PDT 24
Finished Aug 02 05:23:54 PM PDT 24
Peak memory 201444 kb
Host smart-c5c6a9f7-f00b-4528-bfec-839eece7edb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168446588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2168446588
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.854182826
Short name T393
Test name
Test status
Simulation time 4098186692 ps
CPU time 9.21 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:23:14 PM PDT 24
Peak memory 201368 kb
Host smart-460ef8b5-94e4-4f94-bc18-35dacb7d3828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854182826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.854182826
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.146470506
Short name T642
Test name
Test status
Simulation time 6082497824 ps
CPU time 2.68 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:23:06 PM PDT 24
Peak memory 201348 kb
Host smart-626759ef-198a-4145-b496-684b6252910e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146470506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.146470506
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.29774423
Short name T745
Test name
Test status
Simulation time 224664556572 ps
CPU time 135.04 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:25:28 PM PDT 24
Peak memory 201452 kb
Host smart-e9debadc-de0f-41bc-b46e-88ead30f9a2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29774423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.29774423
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1912771232
Short name T90
Test name
Test status
Simulation time 22999680514 ps
CPU time 24.29 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:23:29 PM PDT 24
Peak memory 209808 kb
Host smart-5ed68e0d-d77d-414e-a8d6-3f3a7b7db49e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912771232 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1912771232
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.788204852
Short name T616
Test name
Test status
Simulation time 313838683 ps
CPU time 0.87 seconds
Started Aug 02 05:22:35 PM PDT 24
Finished Aug 02 05:22:36 PM PDT 24
Peak memory 201292 kb
Host smart-73d2b54b-d33a-4e9a-b3c3-02a043d9b2a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788204852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.788204852
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3516267437
Short name T679
Test name
Test status
Simulation time 183873141297 ps
CPU time 380.19 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 201432 kb
Host smart-52bae5d7-db29-43d3-bad8-a4c8eedbd51d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516267437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3516267437
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3518896955
Short name T667
Test name
Test status
Simulation time 345812541607 ps
CPU time 743.68 seconds
Started Aug 02 05:22:32 PM PDT 24
Finished Aug 02 05:34:56 PM PDT 24
Peak memory 201500 kb
Host smart-401e269e-5b92-4a01-aba6-ccca1b5e8f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518896955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3518896955
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3275742869
Short name T249
Test name
Test status
Simulation time 162809311815 ps
CPU time 185.14 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:25:33 PM PDT 24
Peak memory 201372 kb
Host smart-17c9d79f-240f-4ace-93f2-79db4a37c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275742869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3275742869
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1372584792
Short name T116
Test name
Test status
Simulation time 490403433846 ps
CPU time 288.45 seconds
Started Aug 02 05:22:31 PM PDT 24
Finished Aug 02 05:27:20 PM PDT 24
Peak memory 201492 kb
Host smart-2e775353-a26e-4862-b867-9c51d2bfa66d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372584792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1372584792
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.364636632
Short name T563
Test name
Test status
Simulation time 164700419690 ps
CPU time 64.52 seconds
Started Aug 02 05:22:29 PM PDT 24
Finished Aug 02 05:23:33 PM PDT 24
Peak memory 201512 kb
Host smart-afe7dbbc-4bab-445f-b69a-f73d09d5a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364636632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.364636632
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1615739638
Short name T700
Test name
Test status
Simulation time 490060048787 ps
CPU time 264.45 seconds
Started Aug 02 05:22:39 PM PDT 24
Finished Aug 02 05:27:03 PM PDT 24
Peak memory 201468 kb
Host smart-4aa95b52-34bd-40f6-869b-bf9f5e7ebe55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615739638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1615739638
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1727787134
Short name T267
Test name
Test status
Simulation time 555176209865 ps
CPU time 1291.29 seconds
Started Aug 02 05:22:32 PM PDT 24
Finished Aug 02 05:44:04 PM PDT 24
Peak memory 201500 kb
Host smart-4acf8407-593c-4d96-9572-9320f5c1cff2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727787134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1727787134
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2073931892
Short name T501
Test name
Test status
Simulation time 199051815899 ps
CPU time 230.8 seconds
Started Aug 02 05:22:27 PM PDT 24
Finished Aug 02 05:26:18 PM PDT 24
Peak memory 201440 kb
Host smart-97216508-aace-458a-be21-76019ea3bd6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073931892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2073931892
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1628497784
Short name T533
Test name
Test status
Simulation time 96715012797 ps
CPU time 337.17 seconds
Started Aug 02 05:22:30 PM PDT 24
Finished Aug 02 05:28:08 PM PDT 24
Peak memory 201808 kb
Host smart-bd87948f-0a21-49c6-b785-116441e267e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628497784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1628497784
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3417303579
Short name T377
Test name
Test status
Simulation time 27118356205 ps
CPU time 18.57 seconds
Started Aug 02 05:22:29 PM PDT 24
Finished Aug 02 05:22:47 PM PDT 24
Peak memory 201444 kb
Host smart-4fc50958-fd49-41b9-9622-70bf824b8d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417303579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3417303579
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.514663214
Short name T523
Test name
Test status
Simulation time 4148226839 ps
CPU time 11.29 seconds
Started Aug 02 05:22:30 PM PDT 24
Finished Aug 02 05:22:41 PM PDT 24
Peak memory 201380 kb
Host smart-e10990d6-c5d3-4e09-b892-75888393b43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514663214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.514663214
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2488818031
Short name T63
Test name
Test status
Simulation time 4138269219 ps
CPU time 2.73 seconds
Started Aug 02 05:22:36 PM PDT 24
Finished Aug 02 05:22:39 PM PDT 24
Peak memory 217184 kb
Host smart-dd6e3a1b-8aac-4cfd-be9d-a2ff7f165fd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488818031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2488818031
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3280018638
Short name T478
Test name
Test status
Simulation time 5969254491 ps
CPU time 7.39 seconds
Started Aug 02 05:22:30 PM PDT 24
Finished Aug 02 05:22:38 PM PDT 24
Peak memory 201412 kb
Host smart-3b2ecda5-3041-4a8a-8fe3-75daa41ce449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280018638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3280018638
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2592349214
Short name T677
Test name
Test status
Simulation time 165758020249 ps
CPU time 388.5 seconds
Started Aug 02 05:22:30 PM PDT 24
Finished Aug 02 05:28:59 PM PDT 24
Peak memory 201568 kb
Host smart-0ec7fb09-0b9f-4a23-94c6-792071961c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592349214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2592349214
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.4022549000
Short name T615
Test name
Test status
Simulation time 438609913 ps
CPU time 1.67 seconds
Started Aug 02 05:23:08 PM PDT 24
Finished Aug 02 05:23:10 PM PDT 24
Peak memory 201204 kb
Host smart-3b103d98-8315-4ac6-bddd-26978bd65696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022549000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.4022549000
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1111088953
Short name T538
Test name
Test status
Simulation time 174735035360 ps
CPU time 102.28 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:24:56 PM PDT 24
Peak memory 201472 kb
Host smart-4d933b52-339d-4c6c-845f-fb5a98e3317b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111088953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1111088953
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3259077075
Short name T672
Test name
Test status
Simulation time 496297041849 ps
CPU time 680.41 seconds
Started Aug 02 05:23:14 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 201464 kb
Host smart-4acb1649-d39f-4608-9fae-053367d836d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259077075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3259077075
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1823686602
Short name T5
Test name
Test status
Simulation time 163541132883 ps
CPU time 379.22 seconds
Started Aug 02 05:23:11 PM PDT 24
Finished Aug 02 05:29:30 PM PDT 24
Peak memory 201464 kb
Host smart-120851a3-cb5c-42ed-810e-360e6083b622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823686602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1823686602
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2714951809
Short name T446
Test name
Test status
Simulation time 162243834054 ps
CPU time 383.84 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:29:28 PM PDT 24
Peak memory 201460 kb
Host smart-43b0e994-93e1-4494-9955-71dcf527ae1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714951809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2714951809
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1987272367
Short name T543
Test name
Test status
Simulation time 161450910942 ps
CPU time 179.62 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:26:05 PM PDT 24
Peak memory 201476 kb
Host smart-4d0e4c56-00be-48c9-9a7c-8f1b1dc1d8c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987272367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1987272367
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3172004895
Short name T306
Test name
Test status
Simulation time 195405822037 ps
CPU time 26.96 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:23:32 PM PDT 24
Peak memory 201488 kb
Host smart-d007d22d-c602-4171-948e-f4faaec441e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172004895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3172004895
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.427296291
Short name T460
Test name
Test status
Simulation time 390391296395 ps
CPU time 453.38 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:30:37 PM PDT 24
Peak memory 201448 kb
Host smart-1bdc4c0f-b36d-4d9d-9043-fea882179364
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427296291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.427296291
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3450582744
Short name T365
Test name
Test status
Simulation time 82540714674 ps
CPU time 341.9 seconds
Started Aug 02 05:23:07 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 201868 kb
Host smart-0c98bd02-5680-4921-892b-8c027cd09592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450582744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3450582744
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1063457316
Short name T783
Test name
Test status
Simulation time 35052568028 ps
CPU time 23.77 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:23:29 PM PDT 24
Peak memory 201316 kb
Host smart-1413f3d3-0fc2-49af-b0b3-5bacb57f059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063457316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1063457316
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3909228257
Short name T590
Test name
Test status
Simulation time 3510996041 ps
CPU time 5.42 seconds
Started Aug 02 05:23:07 PM PDT 24
Finished Aug 02 05:23:13 PM PDT 24
Peak memory 201404 kb
Host smart-2462ad2e-5a16-4f7d-b3b9-42b81869a8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909228257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3909228257
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3152628032
Short name T398
Test name
Test status
Simulation time 5994342340 ps
CPU time 3.13 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:23:06 PM PDT 24
Peak memory 201424 kb
Host smart-23c211a8-550e-4eb6-99b7-fac74b02b721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152628032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3152628032
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1820455210
Short name T741
Test name
Test status
Simulation time 163498470890 ps
CPU time 114.55 seconds
Started Aug 02 05:23:08 PM PDT 24
Finished Aug 02 05:25:03 PM PDT 24
Peak memory 201528 kb
Host smart-9208cd87-a563-4d53-abba-bfc7a6ceed67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820455210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1820455210
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3238929239
Short name T34
Test name
Test status
Simulation time 236934774270 ps
CPU time 338.2 seconds
Started Aug 02 05:23:11 PM PDT 24
Finished Aug 02 05:28:50 PM PDT 24
Peak memory 210140 kb
Host smart-a8d1ec01-8d66-42b5-acd9-28ca60b0c88b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238929239 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3238929239
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2905412914
Short name T31
Test name
Test status
Simulation time 285192104 ps
CPU time 1.24 seconds
Started Aug 02 05:23:12 PM PDT 24
Finished Aug 02 05:23:13 PM PDT 24
Peak memory 201248 kb
Host smart-92af0fc2-52a5-4534-9639-7d5f7777ba09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905412914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2905412914
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1287743277
Short name T244
Test name
Test status
Simulation time 328686781576 ps
CPU time 186.55 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:26:11 PM PDT 24
Peak memory 201528 kb
Host smart-89f84c6c-db4a-4c31-bfa7-2ba5ea679c4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287743277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1287743277
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1468340975
Short name T687
Test name
Test status
Simulation time 183442074379 ps
CPU time 377.62 seconds
Started Aug 02 05:23:07 PM PDT 24
Finished Aug 02 05:29:29 PM PDT 24
Peak memory 201504 kb
Host smart-e806e466-ce6b-426e-83b3-fc2fb6e4f01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468340975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1468340975
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2306948500
Short name T596
Test name
Test status
Simulation time 165381748719 ps
CPU time 92.97 seconds
Started Aug 02 05:23:11 PM PDT 24
Finished Aug 02 05:24:44 PM PDT 24
Peak memory 201516 kb
Host smart-65cbb199-a2cf-4bc2-b24a-ad8443574dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306948500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2306948500
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2557139031
Short name T742
Test name
Test status
Simulation time 326931901325 ps
CPU time 407.93 seconds
Started Aug 02 05:23:19 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 201476 kb
Host smart-c733c6d2-070c-41ab-a697-471dcde88ddd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557139031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2557139031
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3389422058
Short name T418
Test name
Test status
Simulation time 171342667050 ps
CPU time 399.47 seconds
Started Aug 02 05:23:11 PM PDT 24
Finished Aug 02 05:29:51 PM PDT 24
Peak memory 201440 kb
Host smart-eb45ecca-4a60-4190-97c8-2b47a26626ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389422058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3389422058
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2690996758
Short name T455
Test name
Test status
Simulation time 408217679946 ps
CPU time 932.02 seconds
Started Aug 02 05:23:16 PM PDT 24
Finished Aug 02 05:38:48 PM PDT 24
Peak memory 201492 kb
Host smart-3c19e61b-7e1b-4d1e-98b9-f9e80fc6a7df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690996758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2690996758
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.419324761
Short name T719
Test name
Test status
Simulation time 121790016868 ps
CPU time 637.43 seconds
Started Aug 02 05:23:15 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 201852 kb
Host smart-69228d03-fb10-446a-b09f-5ae495a84863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419324761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.419324761
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3336325017
Short name T457
Test name
Test status
Simulation time 43809829363 ps
CPU time 25.03 seconds
Started Aug 02 05:23:04 PM PDT 24
Finished Aug 02 05:23:30 PM PDT 24
Peak memory 201376 kb
Host smart-9e2d5a3d-2738-4d73-b327-cd1f4e198a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336325017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3336325017
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.120936027
Short name T441
Test name
Test status
Simulation time 4029707826 ps
CPU time 9.32 seconds
Started Aug 02 05:23:07 PM PDT 24
Finished Aug 02 05:23:17 PM PDT 24
Peak memory 201396 kb
Host smart-45594ec2-fdbf-4fbd-9958-e881cb3a3106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120936027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.120936027
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.336231816
Short name T476
Test name
Test status
Simulation time 5821164179 ps
CPU time 13.17 seconds
Started Aug 02 05:23:03 PM PDT 24
Finished Aug 02 05:23:16 PM PDT 24
Peak memory 201388 kb
Host smart-3582dcad-2dec-4f44-bdc3-1dfd5603308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336231816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.336231816
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.991609905
Short name T226
Test name
Test status
Simulation time 114800452749 ps
CPU time 405.61 seconds
Started Aug 02 05:23:09 PM PDT 24
Finished Aug 02 05:29:55 PM PDT 24
Peak memory 201772 kb
Host smart-8c608949-1772-46f4-ae4b-d951fa890a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991609905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
991609905
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4232356728
Short name T41
Test name
Test status
Simulation time 37721001155 ps
CPU time 74.7 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:24:28 PM PDT 24
Peak memory 209840 kb
Host smart-d0bcb34c-6266-4944-ab21-d6fdfa3b3f36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232356728 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4232356728
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.240955837
Short name T553
Test name
Test status
Simulation time 283055039 ps
CPU time 1.25 seconds
Started Aug 02 05:23:16 PM PDT 24
Finished Aug 02 05:23:17 PM PDT 24
Peak memory 201260 kb
Host smart-82112fc8-2078-47b7-936a-6781d54a8d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240955837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.240955837
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.718375756
Short name T652
Test name
Test status
Simulation time 355604694784 ps
CPU time 402.78 seconds
Started Aug 02 05:23:15 PM PDT 24
Finished Aug 02 05:29:58 PM PDT 24
Peak memory 201420 kb
Host smart-4b03cc7e-dde8-4b08-a013-2d8cd5640051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718375756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.718375756
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1167933226
Short name T265
Test name
Test status
Simulation time 161646693983 ps
CPU time 94.65 seconds
Started Aug 02 05:23:09 PM PDT 24
Finished Aug 02 05:24:44 PM PDT 24
Peak memory 201376 kb
Host smart-ab5b5e17-e13c-4953-b995-f620571c894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167933226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1167933226
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2299441322
Short name T208
Test name
Test status
Simulation time 497581720706 ps
CPU time 301.1 seconds
Started Aug 02 05:23:09 PM PDT 24
Finished Aug 02 05:28:10 PM PDT 24
Peak memory 201404 kb
Host smart-d254f682-8a50-4f86-a930-5ec14b5caaee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299441322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2299441322
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3907722032
Short name T605
Test name
Test status
Simulation time 161603717105 ps
CPU time 305.99 seconds
Started Aug 02 05:23:05 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 201468 kb
Host smart-c135d751-735b-42c6-85a2-7b1161fb8fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907722032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3907722032
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.558151325
Short name T754
Test name
Test status
Simulation time 166566620677 ps
CPU time 365.31 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 201464 kb
Host smart-6235426e-6856-4009-91ad-d7a41bb0179c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=558151325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.558151325
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1139975914
Short name T424
Test name
Test status
Simulation time 602246814026 ps
CPU time 747.86 seconds
Started Aug 02 05:23:22 PM PDT 24
Finished Aug 02 05:35:50 PM PDT 24
Peak memory 201556 kb
Host smart-6c6a0be7-81c9-4925-9a23-b6d8c0cf69d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139975914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1139975914
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3900754998
Short name T50
Test name
Test status
Simulation time 81384964315 ps
CPU time 285.35 seconds
Started Aug 02 05:23:10 PM PDT 24
Finished Aug 02 05:27:56 PM PDT 24
Peak memory 201904 kb
Host smart-da5737bf-73d0-490e-a8bd-dd1ec78efff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900754998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3900754998
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.641235963
Short name T551
Test name
Test status
Simulation time 43375585100 ps
CPU time 6.04 seconds
Started Aug 02 05:23:20 PM PDT 24
Finished Aug 02 05:23:27 PM PDT 24
Peak memory 201404 kb
Host smart-d3da57b5-1de6-43af-96ff-8c47f8aa07b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641235963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.641235963
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1271001952
Short name T676
Test name
Test status
Simulation time 4604075746 ps
CPU time 11.45 seconds
Started Aug 02 05:23:17 PM PDT 24
Finished Aug 02 05:23:29 PM PDT 24
Peak memory 201388 kb
Host smart-5dc28075-88c4-4a3d-939a-aebdd263a1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271001952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1271001952
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1585971250
Short name T505
Test name
Test status
Simulation time 5821690560 ps
CPU time 3.84 seconds
Started Aug 02 05:23:14 PM PDT 24
Finished Aug 02 05:23:19 PM PDT 24
Peak memory 201368 kb
Host smart-56fb58be-5a12-4026-952c-d9233ea666bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585971250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1585971250
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3004332520
Short name T37
Test name
Test status
Simulation time 214133773791 ps
CPU time 513 seconds
Started Aug 02 05:23:15 PM PDT 24
Finished Aug 02 05:31:48 PM PDT 24
Peak memory 201436 kb
Host smart-62fad2c8-13af-4e9c-afe6-ec42b23a7024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004332520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3004332520
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2863811232
Short name T111
Test name
Test status
Simulation time 119325002043 ps
CPU time 105.73 seconds
Started Aug 02 05:23:19 PM PDT 24
Finished Aug 02 05:25:05 PM PDT 24
Peak memory 210212 kb
Host smart-cc7b9e78-2057-4d62-9a95-a2664af37906
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863811232 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2863811232
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3338666458
Short name T403
Test name
Test status
Simulation time 545423091 ps
CPU time 0.69 seconds
Started Aug 02 05:23:23 PM PDT 24
Finished Aug 02 05:23:24 PM PDT 24
Peak memory 201180 kb
Host smart-abdfa833-45de-46e4-afa1-14ba49a615fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338666458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3338666458
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1315144916
Short name T579
Test name
Test status
Simulation time 162816880416 ps
CPU time 340.37 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 201488 kb
Host smart-1163381b-f5a8-4965-9a6c-500021bf2d4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315144916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1315144916
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3090460388
Short name T469
Test name
Test status
Simulation time 330954414496 ps
CPU time 101.3 seconds
Started Aug 02 05:23:15 PM PDT 24
Finished Aug 02 05:24:56 PM PDT 24
Peak memory 201468 kb
Host smart-24e9547b-9f10-4f4a-b8c3-5e5defaba0bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090460388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3090460388
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2111242858
Short name T169
Test name
Test status
Simulation time 335693316695 ps
CPU time 517.34 seconds
Started Aug 02 05:23:20 PM PDT 24
Finished Aug 02 05:31:57 PM PDT 24
Peak memory 201428 kb
Host smart-84c37dc7-e488-495c-83cf-577c282c4bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111242858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2111242858
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1704557368
Short name T556
Test name
Test status
Simulation time 325969927094 ps
CPU time 659.58 seconds
Started Aug 02 05:23:19 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 201468 kb
Host smart-1c6a91c4-0125-41c8-84d3-fc6502d728bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704557368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1704557368
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1469400084
Short name T785
Test name
Test status
Simulation time 572963881400 ps
CPU time 1324.12 seconds
Started Aug 02 05:23:13 PM PDT 24
Finished Aug 02 05:45:17 PM PDT 24
Peak memory 201452 kb
Host smart-d794f7b0-a281-4b6f-ae4f-b4faa7760e8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469400084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1469400084
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2046007845
Short name T452
Test name
Test status
Simulation time 604638569083 ps
CPU time 791.67 seconds
Started Aug 02 05:23:20 PM PDT 24
Finished Aug 02 05:36:32 PM PDT 24
Peak memory 201528 kb
Host smart-28536cd8-e54a-4059-a6e6-98774e54d4cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046007845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2046007845
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4278199075
Short name T363
Test name
Test status
Simulation time 114715850555 ps
CPU time 356.29 seconds
Started Aug 02 05:23:17 PM PDT 24
Finished Aug 02 05:29:13 PM PDT 24
Peak memory 201840 kb
Host smart-2dae994d-2c92-453e-b721-6694997ed692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278199075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4278199075
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.4229034757
Short name T626
Test name
Test status
Simulation time 36035001829 ps
CPU time 63.27 seconds
Started Aug 02 05:23:15 PM PDT 24
Finished Aug 02 05:24:18 PM PDT 24
Peak memory 201384 kb
Host smart-35148fb6-0ac1-4a3a-9ebd-73120c2a7063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229034757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.4229034757
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2352649121
Short name T500
Test name
Test status
Simulation time 2781606774 ps
CPU time 1.88 seconds
Started Aug 02 05:23:21 PM PDT 24
Finished Aug 02 05:23:23 PM PDT 24
Peak memory 201356 kb
Host smart-84d8505a-bac8-428d-a64b-7680e28bd8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352649121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2352649121
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1687362669
Short name T432
Test name
Test status
Simulation time 5772342574 ps
CPU time 4.03 seconds
Started Aug 02 05:23:11 PM PDT 24
Finished Aug 02 05:23:15 PM PDT 24
Peak memory 201428 kb
Host smart-a92a1d25-e0ec-4ddf-9c7b-d71c497d56f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687362669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1687362669
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1755638900
Short name T552
Test name
Test status
Simulation time 137192924514 ps
CPU time 401.02 seconds
Started Aug 02 05:23:21 PM PDT 24
Finished Aug 02 05:30:03 PM PDT 24
Peak memory 201872 kb
Host smart-ccfa8431-0059-4fbc-a36f-04ce7949ddde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755638900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1755638900
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.539202757
Short name T427
Test name
Test status
Simulation time 406394614 ps
CPU time 1.5 seconds
Started Aug 02 05:23:29 PM PDT 24
Finished Aug 02 05:23:31 PM PDT 24
Peak memory 201244 kb
Host smart-ae0fa09b-ef7e-42c7-b1fb-0554ce24080b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539202757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.539202757
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1774221180
Short name T25
Test name
Test status
Simulation time 161232611189 ps
CPU time 103.02 seconds
Started Aug 02 05:23:25 PM PDT 24
Finished Aug 02 05:25:08 PM PDT 24
Peak memory 201496 kb
Host smart-c7c77f96-3970-41a0-a640-418f3f831797
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774221180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1774221180
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2419554256
Short name T567
Test name
Test status
Simulation time 178324805359 ps
CPU time 406.87 seconds
Started Aug 02 05:23:23 PM PDT 24
Finished Aug 02 05:30:10 PM PDT 24
Peak memory 201600 kb
Host smart-6511088c-8063-4bdb-8824-fd187a50a9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419554256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2419554256
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.548831955
Short name T86
Test name
Test status
Simulation time 161691801018 ps
CPU time 64.38 seconds
Started Aug 02 05:23:22 PM PDT 24
Finished Aug 02 05:24:27 PM PDT 24
Peak memory 201476 kb
Host smart-ef5b419b-e351-41e3-86f4-0bf1923c0f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548831955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.548831955
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.883287121
Short name T499
Test name
Test status
Simulation time 493298511073 ps
CPU time 568.89 seconds
Started Aug 02 05:23:23 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 201480 kb
Host smart-7031d8de-ef96-47ca-97cc-b2947fdfd0d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=883287121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.883287121
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3720811662
Short name T287
Test name
Test status
Simulation time 161455935717 ps
CPU time 288.26 seconds
Started Aug 02 05:23:20 PM PDT 24
Finished Aug 02 05:28:09 PM PDT 24
Peak memory 201500 kb
Host smart-0be089d1-21d3-45b8-a1da-4a42d16fbb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720811662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3720811662
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1515201108
Short name T462
Test name
Test status
Simulation time 157257509404 ps
CPU time 95.47 seconds
Started Aug 02 05:23:22 PM PDT 24
Finished Aug 02 05:24:58 PM PDT 24
Peak memory 201412 kb
Host smart-a16e2880-315c-4393-bd18-e9a60978954f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515201108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1515201108
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.4215493045
Short name T340
Test name
Test status
Simulation time 631798780232 ps
CPU time 1381.97 seconds
Started Aug 02 05:23:26 PM PDT 24
Finished Aug 02 05:46:28 PM PDT 24
Peak memory 201496 kb
Host smart-ec72f616-33f7-4b44-98c7-d263dae3afeb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215493045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.4215493045
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1821123547
Short name T261
Test name
Test status
Simulation time 606603333814 ps
CPU time 739.77 seconds
Started Aug 02 05:23:24 PM PDT 24
Finished Aug 02 05:35:44 PM PDT 24
Peak memory 201564 kb
Host smart-2d122c3f-d492-414f-8cc2-7e53df3979aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821123547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1821123547
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.406107543
Short name T360
Test name
Test status
Simulation time 74014678317 ps
CPU time 354.53 seconds
Started Aug 02 05:23:25 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 201952 kb
Host smart-df5020ca-51c7-45a6-a4aa-6577d8f3961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406107543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.406107543
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2658457606
Short name T48
Test name
Test status
Simulation time 45133130033 ps
CPU time 98.04 seconds
Started Aug 02 05:23:31 PM PDT 24
Finished Aug 02 05:25:09 PM PDT 24
Peak memory 201364 kb
Host smart-a1659390-755c-4fc2-bf00-c55ba52871b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658457606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2658457606
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2104760635
Short name T376
Test name
Test status
Simulation time 5138723979 ps
CPU time 11.55 seconds
Started Aug 02 05:23:24 PM PDT 24
Finished Aug 02 05:23:35 PM PDT 24
Peak memory 201304 kb
Host smart-d022cb12-451a-4dc2-bce5-f2dedb6029b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104760635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2104760635
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.564482426
Short name T411
Test name
Test status
Simulation time 6122396368 ps
CPU time 1.76 seconds
Started Aug 02 05:23:21 PM PDT 24
Finished Aug 02 05:23:23 PM PDT 24
Peak memory 201424 kb
Host smart-59c9ea63-865b-4d5d-a34c-9f59e6cdea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564482426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.564482426
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4034199933
Short name T547
Test name
Test status
Simulation time 168601703123 ps
CPU time 57.21 seconds
Started Aug 02 05:23:22 PM PDT 24
Finished Aug 02 05:24:20 PM PDT 24
Peak memory 201488 kb
Host smart-ef03e1c2-1ad5-4c24-9cbc-5fdf7c706bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034199933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4034199933
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1188163027
Short name T20
Test name
Test status
Simulation time 32893446408 ps
CPU time 87.01 seconds
Started Aug 02 05:23:26 PM PDT 24
Finished Aug 02 05:24:54 PM PDT 24
Peak memory 210260 kb
Host smart-8f133d1a-babc-479a-b81c-37100b4a990a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188163027 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1188163027
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3969839251
Short name T588
Test name
Test status
Simulation time 510706673 ps
CPU time 1.76 seconds
Started Aug 02 05:23:30 PM PDT 24
Finished Aug 02 05:23:32 PM PDT 24
Peak memory 201280 kb
Host smart-8288dd33-35e5-4c6f-bc4f-26efb3ba908d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969839251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3969839251
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2826126864
Short name T294
Test name
Test status
Simulation time 359042233245 ps
CPU time 209.43 seconds
Started Aug 02 05:23:22 PM PDT 24
Finished Aug 02 05:26:52 PM PDT 24
Peak memory 201608 kb
Host smart-468cbbf5-25ac-4aec-b8a9-34b955281b5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826126864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2826126864
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.868171119
Short name T310
Test name
Test status
Simulation time 346527591065 ps
CPU time 412.06 seconds
Started Aug 02 05:23:24 PM PDT 24
Finished Aug 02 05:30:17 PM PDT 24
Peak memory 201456 kb
Host smart-f653a8e7-4963-4d0a-a725-bd090a196971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868171119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.868171119
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.211705331
Short name T160
Test name
Test status
Simulation time 333777284198 ps
CPU time 712.16 seconds
Started Aug 02 05:23:23 PM PDT 24
Finished Aug 02 05:35:15 PM PDT 24
Peak memory 201364 kb
Host smart-b3fe0ddf-0187-41ff-bd58-c69e4bc7ce73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211705331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.211705331
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.799646289
Short name T387
Test name
Test status
Simulation time 164958825336 ps
CPU time 372.83 seconds
Started Aug 02 05:23:20 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 201460 kb
Host smart-8174ae1c-9647-41cf-b7c1-a2cb9ec32269
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=799646289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.799646289
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.476527821
Short name T648
Test name
Test status
Simulation time 338316952919 ps
CPU time 385.78 seconds
Started Aug 02 05:23:27 PM PDT 24
Finished Aug 02 05:29:52 PM PDT 24
Peak memory 201480 kb
Host smart-75ade670-8bea-45a3-aa75-178b1a0f8581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476527821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.476527821
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4226766720
Short name T215
Test name
Test status
Simulation time 326947079882 ps
CPU time 802.87 seconds
Started Aug 02 05:23:24 PM PDT 24
Finished Aug 02 05:36:47 PM PDT 24
Peak memory 201500 kb
Host smart-84fa89ef-176c-46a3-853c-d78d2c1f6fc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226766720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.4226766720
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4275502510
Short name T504
Test name
Test status
Simulation time 375350869345 ps
CPU time 807.16 seconds
Started Aug 02 05:23:24 PM PDT 24
Finished Aug 02 05:36:51 PM PDT 24
Peak memory 201496 kb
Host smart-dfc29ce5-eb9d-45b3-b92e-206eb4bb898b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275502510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4275502510
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.739244298
Short name T492
Test name
Test status
Simulation time 398255966437 ps
CPU time 153.54 seconds
Started Aug 02 05:23:26 PM PDT 24
Finished Aug 02 05:26:00 PM PDT 24
Peak memory 201476 kb
Host smart-f0d81581-ff9f-471c-8e0b-37ed350cdab5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739244298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.739244298
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1008247763
Short name T544
Test name
Test status
Simulation time 89892946232 ps
CPU time 468.86 seconds
Started Aug 02 05:23:29 PM PDT 24
Finished Aug 02 05:31:18 PM PDT 24
Peak memory 201752 kb
Host smart-35508f83-fcbf-4a73-9e9a-0c38962960d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008247763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1008247763
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.394515432
Short name T196
Test name
Test status
Simulation time 30207226455 ps
CPU time 16.81 seconds
Started Aug 02 05:23:29 PM PDT 24
Finished Aug 02 05:23:46 PM PDT 24
Peak memory 201372 kb
Host smart-a96984cf-217b-4c0d-959c-b762434f2e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394515432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.394515432
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3070572803
Short name T716
Test name
Test status
Simulation time 5507255766 ps
CPU time 13.99 seconds
Started Aug 02 05:23:31 PM PDT 24
Finished Aug 02 05:23:45 PM PDT 24
Peak memory 201376 kb
Host smart-d260ce13-9ae4-4eb4-b2de-133adadb506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070572803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3070572803
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.276586358
Short name T541
Test name
Test status
Simulation time 6199634521 ps
CPU time 13.63 seconds
Started Aug 02 05:23:25 PM PDT 24
Finished Aug 02 05:23:39 PM PDT 24
Peak memory 201424 kb
Host smart-f57bc97e-7ebc-436a-aed0-e2a0181e0ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276586358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.276586358
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.106477249
Short name T483
Test name
Test status
Simulation time 41574012340 ps
CPU time 24.85 seconds
Started Aug 02 05:23:27 PM PDT 24
Finished Aug 02 05:23:52 PM PDT 24
Peak memory 201364 kb
Host smart-241ff485-cd4c-4362-bb2b-88ba5f3d8a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106477249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
106477249
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3932768187
Short name T450
Test name
Test status
Simulation time 506737593 ps
CPU time 0.8 seconds
Started Aug 02 05:23:29 PM PDT 24
Finished Aug 02 05:23:30 PM PDT 24
Peak memory 201276 kb
Host smart-a98a0227-27cb-4272-b422-1b5a51370500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932768187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3932768187
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1125753675
Short name T211
Test name
Test status
Simulation time 336030070307 ps
CPU time 113.74 seconds
Started Aug 02 05:23:30 PM PDT 24
Finished Aug 02 05:25:24 PM PDT 24
Peak memory 200844 kb
Host smart-7844aa60-abcb-4508-a803-5e7fcf4e356d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125753675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1125753675
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.45822467
Short name T212
Test name
Test status
Simulation time 511637160978 ps
CPU time 505.95 seconds
Started Aug 02 05:23:30 PM PDT 24
Finished Aug 02 05:31:56 PM PDT 24
Peak memory 200800 kb
Host smart-c68a277a-8822-457d-b50f-f1c783f43c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45822467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.45822467
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.4260880203
Short name T406
Test name
Test status
Simulation time 165062857482 ps
CPU time 410.41 seconds
Started Aug 02 05:23:28 PM PDT 24
Finished Aug 02 05:30:18 PM PDT 24
Peak memory 201460 kb
Host smart-311e2d9e-c36c-45d0-8d5b-5f706f332119
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260880203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.4260880203
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.530461242
Short name T341
Test name
Test status
Simulation time 333402123906 ps
CPU time 222.54 seconds
Started Aug 02 05:23:33 PM PDT 24
Finished Aug 02 05:27:15 PM PDT 24
Peak memory 201452 kb
Host smart-c09bd150-a648-4d29-b97c-d0fda7a23e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530461242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.530461242
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.616534559
Short name T98
Test name
Test status
Simulation time 159174335523 ps
CPU time 112.16 seconds
Started Aug 02 05:23:30 PM PDT 24
Finished Aug 02 05:25:23 PM PDT 24
Peak memory 201464 kb
Host smart-12e9dc54-c2ed-46de-be26-69adaa7f6911
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=616534559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.616534559
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.4088770485
Short name T690
Test name
Test status
Simulation time 572066866570 ps
CPU time 349.78 seconds
Started Aug 02 05:23:30 PM PDT 24
Finished Aug 02 05:29:20 PM PDT 24
Peak memory 200844 kb
Host smart-d4c12991-995e-4816-827c-ceca966a1a55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088770485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.4088770485
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3220667460
Short name T655
Test name
Test status
Simulation time 203956442852 ps
CPU time 108.84 seconds
Started Aug 02 05:23:30 PM PDT 24
Finished Aug 02 05:25:19 PM PDT 24
Peak memory 200968 kb
Host smart-6167763c-cd63-41b8-86e5-a96783b8c979
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220667460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3220667460
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2394830231
Short name T746
Test name
Test status
Simulation time 76793764881 ps
CPU time 248.69 seconds
Started Aug 02 05:23:30 PM PDT 24
Finished Aug 02 05:27:39 PM PDT 24
Peak memory 201152 kb
Host smart-cc222117-5478-4c20-b05d-1ea0e58bedff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394830231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2394830231
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2357256947
Short name T645
Test name
Test status
Simulation time 44413236773 ps
CPU time 12.55 seconds
Started Aug 02 05:23:35 PM PDT 24
Finished Aug 02 05:23:48 PM PDT 24
Peak memory 201440 kb
Host smart-c07f930c-c50b-48f5-9f78-9dcfa4c3e2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357256947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2357256947
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.244262934
Short name T400
Test name
Test status
Simulation time 4568785339 ps
CPU time 10.92 seconds
Started Aug 02 05:23:34 PM PDT 24
Finished Aug 02 05:23:46 PM PDT 24
Peak memory 201352 kb
Host smart-127a3a6f-d600-4d2f-850f-2f286de20cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244262934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.244262934
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1846868632
Short name T576
Test name
Test status
Simulation time 5851786207 ps
CPU time 4.2 seconds
Started Aug 02 05:23:28 PM PDT 24
Finished Aug 02 05:23:33 PM PDT 24
Peak memory 201312 kb
Host smart-412b2dd4-fad2-44b5-9b4a-41d7b2a0a704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846868632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1846868632
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1638416247
Short name T799
Test name
Test status
Simulation time 385419300389 ps
CPU time 1542.92 seconds
Started Aug 02 05:23:31 PM PDT 24
Finished Aug 02 05:49:14 PM PDT 24
Peak memory 209972 kb
Host smart-431f9526-dae3-42f1-91d3-a4b60077432f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638416247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1638416247
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.174135214
Short name T23
Test name
Test status
Simulation time 61659552391 ps
CPU time 156.09 seconds
Started Aug 02 05:23:29 PM PDT 24
Finished Aug 02 05:26:05 PM PDT 24
Peak memory 209892 kb
Host smart-2167cd45-8844-480a-8d68-7d84a02ebaa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174135214 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.174135214
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.625396730
Short name T481
Test name
Test status
Simulation time 512616502 ps
CPU time 0.84 seconds
Started Aug 02 05:23:38 PM PDT 24
Finished Aug 02 05:23:39 PM PDT 24
Peak memory 201304 kb
Host smart-ce0a6998-a099-426d-ac47-bd75be196f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625396730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.625396730
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3372991655
Short name T770
Test name
Test status
Simulation time 345815158810 ps
CPU time 47.11 seconds
Started Aug 02 05:23:40 PM PDT 24
Finished Aug 02 05:24:27 PM PDT 24
Peak memory 201476 kb
Host smart-f099100a-4ce2-48f2-9e65-1ca84c2e8169
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372991655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3372991655
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1739745059
Short name T354
Test name
Test status
Simulation time 343782671347 ps
CPU time 220.96 seconds
Started Aug 02 05:23:39 PM PDT 24
Finished Aug 02 05:27:20 PM PDT 24
Peak memory 201364 kb
Host smart-e26fe39f-9db7-4ecd-93e9-a5e9f997b43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739745059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1739745059
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1256267217
Short name T203
Test name
Test status
Simulation time 330217293592 ps
CPU time 824.8 seconds
Started Aug 02 05:23:48 PM PDT 24
Finished Aug 02 05:37:33 PM PDT 24
Peak memory 201560 kb
Host smart-1f6c7084-ea5c-4164-991e-3c7394ee214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256267217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1256267217
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3219800574
Short name T593
Test name
Test status
Simulation time 166804666397 ps
CPU time 365.51 seconds
Started Aug 02 05:23:36 PM PDT 24
Finished Aug 02 05:29:42 PM PDT 24
Peak memory 201524 kb
Host smart-1f454ca1-d203-427b-8ecc-fea29c53e2f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219800574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3219800574
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3490028770
Short name T660
Test name
Test status
Simulation time 491985722869 ps
CPU time 581.12 seconds
Started Aug 02 05:23:33 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 201488 kb
Host smart-4aa968a6-8c94-4298-b5ad-3b9f8ca9b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490028770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3490028770
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.743179676
Short name T691
Test name
Test status
Simulation time 324271402250 ps
CPU time 667.17 seconds
Started Aug 02 05:23:29 PM PDT 24
Finished Aug 02 05:34:37 PM PDT 24
Peak memory 201464 kb
Host smart-3234ae23-7abf-4e40-a30b-b58f79455a23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=743179676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.743179676
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1405091626
Short name T99
Test name
Test status
Simulation time 381663308295 ps
CPU time 873.08 seconds
Started Aug 02 05:23:36 PM PDT 24
Finished Aug 02 05:38:09 PM PDT 24
Peak memory 201540 kb
Host smart-4d65a5e8-8ccd-46bd-8889-c9e26986bb35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405091626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1405091626
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.302729615
Short name T506
Test name
Test status
Simulation time 198287970007 ps
CPU time 252.64 seconds
Started Aug 02 05:23:37 PM PDT 24
Finished Aug 02 05:27:50 PM PDT 24
Peak memory 201512 kb
Host smart-25e2abe1-fcbf-4dc6-9274-564337fe97f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302729615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.302729615
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2731910741
Short name T495
Test name
Test status
Simulation time 114911174332 ps
CPU time 367.18 seconds
Started Aug 02 05:23:38 PM PDT 24
Finished Aug 02 05:29:45 PM PDT 24
Peak memory 201900 kb
Host smart-516dca33-c0e1-499e-a795-303834f0657a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731910741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2731910741
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2011447148
Short name T530
Test name
Test status
Simulation time 34996596111 ps
CPU time 82.69 seconds
Started Aug 02 05:23:38 PM PDT 24
Finished Aug 02 05:25:01 PM PDT 24
Peak memory 201364 kb
Host smart-48c18144-4097-481c-bfc4-01028c978ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011447148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2011447148
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4115916167
Short name T609
Test name
Test status
Simulation time 3206349329 ps
CPU time 1.9 seconds
Started Aug 02 05:23:36 PM PDT 24
Finished Aug 02 05:23:39 PM PDT 24
Peak memory 201380 kb
Host smart-e7ac47d3-2a95-41e4-ba54-12079672e6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115916167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4115916167
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2999683985
Short name T379
Test name
Test status
Simulation time 5800223244 ps
CPU time 16.02 seconds
Started Aug 02 05:23:27 PM PDT 24
Finished Aug 02 05:23:44 PM PDT 24
Peak memory 201392 kb
Host smart-19df084a-421d-4b54-b02b-dbe22c8bd251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999683985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2999683985
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.805035387
Short name T557
Test name
Test status
Simulation time 230658733496 ps
CPU time 510.73 seconds
Started Aug 02 05:23:37 PM PDT 24
Finished Aug 02 05:32:08 PM PDT 24
Peak memory 201416 kb
Host smart-21358074-7662-45f3-95d9-2c230c53b042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805035387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
805035387
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.626181398
Short name T19
Test name
Test status
Simulation time 37915380240 ps
CPU time 104.29 seconds
Started Aug 02 05:23:41 PM PDT 24
Finished Aug 02 05:25:25 PM PDT 24
Peak memory 217876 kb
Host smart-0ab6b6ad-0bc2-49aa-89e7-28291f2499ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626181398 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.626181398
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3949457604
Short name T740
Test name
Test status
Simulation time 516555455 ps
CPU time 0.84 seconds
Started Aug 02 05:23:37 PM PDT 24
Finished Aug 02 05:23:38 PM PDT 24
Peak memory 201260 kb
Host smart-ec4fd459-830a-411f-adb4-d241a165c1c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949457604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3949457604
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.34741114
Short name T194
Test name
Test status
Simulation time 588038659619 ps
CPU time 85.46 seconds
Started Aug 02 05:23:38 PM PDT 24
Finished Aug 02 05:25:04 PM PDT 24
Peak memory 201544 kb
Host smart-a630e9ef-69e1-4eea-9741-de395c0dbfe5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34741114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gatin
g.34741114
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3658995804
Short name T255
Test name
Test status
Simulation time 558631438872 ps
CPU time 1301.25 seconds
Started Aug 02 05:23:46 PM PDT 24
Finished Aug 02 05:45:28 PM PDT 24
Peak memory 201392 kb
Host smart-0527ef1f-6af2-46a2-9354-3204dacadafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658995804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3658995804
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3076268339
Short name T629
Test name
Test status
Simulation time 503482512742 ps
CPU time 1221.36 seconds
Started Aug 02 05:23:39 PM PDT 24
Finished Aug 02 05:44:00 PM PDT 24
Peak memory 201408 kb
Host smart-515e2bd0-9c52-4f72-ba8a-249607d64b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076268339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3076268339
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.503802226
Short name T750
Test name
Test status
Simulation time 319159257215 ps
CPU time 211.21 seconds
Started Aug 02 05:23:39 PM PDT 24
Finished Aug 02 05:27:11 PM PDT 24
Peak memory 201540 kb
Host smart-613dace6-4844-47eb-971a-b2f684d06fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503802226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.503802226
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3685010255
Short name T119
Test name
Test status
Simulation time 161884516857 ps
CPU time 90.63 seconds
Started Aug 02 05:23:38 PM PDT 24
Finished Aug 02 05:25:09 PM PDT 24
Peak memory 201504 kb
Host smart-43257052-ef06-422d-b928-7cef50f7bed5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685010255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3685010255
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.929328903
Short name T282
Test name
Test status
Simulation time 256749480932 ps
CPU time 105.79 seconds
Started Aug 02 05:23:38 PM PDT 24
Finished Aug 02 05:25:24 PM PDT 24
Peak memory 201508 kb
Host smart-35e0f7c1-f92a-4986-ae5c-04344369bdab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929328903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.929328903
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.920652283
Short name T394
Test name
Test status
Simulation time 204817033381 ps
CPU time 490.1 seconds
Started Aug 02 05:23:44 PM PDT 24
Finished Aug 02 05:31:54 PM PDT 24
Peak memory 201408 kb
Host smart-329d6cb9-8160-40d1-9728-cdeebcefd862
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920652283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.920652283
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2432408928
Short name T364
Test name
Test status
Simulation time 86920618154 ps
CPU time 320.61 seconds
Started Aug 02 05:23:44 PM PDT 24
Finished Aug 02 05:29:05 PM PDT 24
Peak memory 201848 kb
Host smart-1e3a5bc9-5f29-4287-b7a1-b2c1b7f53a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432408928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2432408928
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3561243644
Short name T94
Test name
Test status
Simulation time 35129378865 ps
CPU time 30.05 seconds
Started Aug 02 05:23:38 PM PDT 24
Finished Aug 02 05:24:08 PM PDT 24
Peak memory 201376 kb
Host smart-7be63c23-0344-4609-8c3c-28e02a67d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561243644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3561243644
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3815413845
Short name T372
Test name
Test status
Simulation time 4488364307 ps
CPU time 3.08 seconds
Started Aug 02 05:23:37 PM PDT 24
Finished Aug 02 05:23:40 PM PDT 24
Peak memory 201424 kb
Host smart-b740754e-f1b2-49a0-832f-47895483c07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815413845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3815413845
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.931832205
Short name T397
Test name
Test status
Simulation time 5906660276 ps
CPU time 4.22 seconds
Started Aug 02 05:23:45 PM PDT 24
Finished Aug 02 05:23:49 PM PDT 24
Peak memory 201396 kb
Host smart-bd8bd7d5-214b-456d-b39b-b6fe11b578a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931832205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.931832205
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1140371670
Short name T703
Test name
Test status
Simulation time 348369371119 ps
CPU time 659.87 seconds
Started Aug 02 05:23:38 PM PDT 24
Finished Aug 02 05:34:38 PM PDT 24
Peak memory 210116 kb
Host smart-6b41f1aa-3b25-4677-add9-1a7ee02e791a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140371670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1140371670
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1757039947
Short name T659
Test name
Test status
Simulation time 195443112281 ps
CPU time 112.56 seconds
Started Aug 02 05:23:46 PM PDT 24
Finished Aug 02 05:25:39 PM PDT 24
Peak memory 210148 kb
Host smart-52995696-b660-4bd8-8c08-de32e03274a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757039947 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1757039947
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.581607895
Short name T516
Test name
Test status
Simulation time 540788144 ps
CPU time 0.93 seconds
Started Aug 02 05:23:49 PM PDT 24
Finished Aug 02 05:23:50 PM PDT 24
Peak memory 201240 kb
Host smart-d1016763-af49-49c1-804c-58a8d91ed33f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581607895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.581607895
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4286374703
Short name T336
Test name
Test status
Simulation time 332197331454 ps
CPU time 740.48 seconds
Started Aug 02 05:23:40 PM PDT 24
Finished Aug 02 05:36:01 PM PDT 24
Peak memory 201464 kb
Host smart-9a8ffb71-b424-4bc6-956b-97bac377a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286374703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4286374703
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2730132100
Short name T429
Test name
Test status
Simulation time 162034559833 ps
CPU time 393.43 seconds
Started Aug 02 05:23:45 PM PDT 24
Finished Aug 02 05:30:18 PM PDT 24
Peak memory 201532 kb
Host smart-1ca714a4-5aa3-4b9a-9624-728d8d1725e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730132100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2730132100
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3888795913
Short name T191
Test name
Test status
Simulation time 487801677753 ps
CPU time 259.95 seconds
Started Aug 02 05:23:43 PM PDT 24
Finished Aug 02 05:28:03 PM PDT 24
Peak memory 201432 kb
Host smart-b4e9fe01-a1b1-46ca-8d93-1e84b2fb0385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888795913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3888795913
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.653042191
Short name T706
Test name
Test status
Simulation time 156553007148 ps
CPU time 46.09 seconds
Started Aug 02 05:23:44 PM PDT 24
Finished Aug 02 05:24:30 PM PDT 24
Peak memory 201524 kb
Host smart-0547834b-4e17-46db-a77c-76fc88a03d09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=653042191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.653042191
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2043405391
Short name T88
Test name
Test status
Simulation time 196607452535 ps
CPU time 425.4 seconds
Started Aug 02 05:23:49 PM PDT 24
Finished Aug 02 05:30:55 PM PDT 24
Peak memory 201492 kb
Host smart-48f1de64-9138-4e05-86eb-07e16ac4356c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043405391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2043405391
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2197279896
Short name T668
Test name
Test status
Simulation time 613005123598 ps
CPU time 87.09 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:25:15 PM PDT 24
Peak memory 201448 kb
Host smart-41609876-f487-42cb-beb3-432edbd25bc3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197279896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2197279896
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3028335021
Short name T239
Test name
Test status
Simulation time 105955243009 ps
CPU time 437.81 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:31:05 PM PDT 24
Peak memory 201868 kb
Host smart-83340986-df05-4b52-b9e6-6fd3a8a82c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028335021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3028335021
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1008726651
Short name T639
Test name
Test status
Simulation time 41784545231 ps
CPU time 26.31 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:24:14 PM PDT 24
Peak memory 201384 kb
Host smart-1473f61c-9924-4ce8-9897-856616467ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008726651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1008726651
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.93336063
Short name T752
Test name
Test status
Simulation time 2968263451 ps
CPU time 2.37 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:23:50 PM PDT 24
Peak memory 201368 kb
Host smart-9847872f-e665-41c5-aa15-4b1852430fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93336063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.93336063
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1215540072
Short name T666
Test name
Test status
Simulation time 5834993900 ps
CPU time 14.66 seconds
Started Aug 02 05:23:40 PM PDT 24
Finished Aug 02 05:23:54 PM PDT 24
Peak memory 201420 kb
Host smart-71ff7c5a-ff18-44b3-9564-6b1b5375b038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215540072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1215540072
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4205317254
Short name T51
Test name
Test status
Simulation time 271397105689 ps
CPU time 386.77 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 210040 kb
Host smart-3b04dd2f-e305-4ce8-8f5e-69d720e2de4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205317254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4205317254
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1983077685
Short name T175
Test name
Test status
Simulation time 142950775808 ps
CPU time 133.14 seconds
Started Aug 02 05:23:49 PM PDT 24
Finished Aug 02 05:26:03 PM PDT 24
Peak memory 209784 kb
Host smart-0a5d799f-4d68-4ec7-8f9a-f7200e0a369c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983077685 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1983077685
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3489426128
Short name T213
Test name
Test status
Simulation time 523265860 ps
CPU time 1.32 seconds
Started Aug 02 05:22:36 PM PDT 24
Finished Aug 02 05:22:38 PM PDT 24
Peak memory 201268 kb
Host smart-24ab2faf-6348-4182-99a2-94224759ff1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489426128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3489426128
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.275615945
Short name T302
Test name
Test status
Simulation time 170702916070 ps
CPU time 59.12 seconds
Started Aug 02 05:22:38 PM PDT 24
Finished Aug 02 05:23:37 PM PDT 24
Peak memory 201540 kb
Host smart-b9d9e87c-33c9-41ef-9fbe-7aee2beac7b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275615945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.275615945
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1734459531
Short name T243
Test name
Test status
Simulation time 332258326110 ps
CPU time 737.51 seconds
Started Aug 02 05:22:52 PM PDT 24
Finished Aug 02 05:35:09 PM PDT 24
Peak memory 201516 kb
Host smart-ea8c99a7-c658-4700-a3ff-baff09797f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734459531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1734459531
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1849710167
Short name T661
Test name
Test status
Simulation time 484689987260 ps
CPU time 850.29 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:36:47 PM PDT 24
Peak memory 201484 kb
Host smart-f7142ff5-2756-4ace-9865-032585fedb54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849710167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1849710167
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3927583091
Short name T330
Test name
Test status
Simulation time 163841160476 ps
CPU time 198.37 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:25:55 PM PDT 24
Peak memory 201512 kb
Host smart-30b7406c-b8e1-499b-9e16-87144c321817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927583091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3927583091
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3166748999
Short name T373
Test name
Test status
Simulation time 159311166349 ps
CPU time 99.12 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:24:16 PM PDT 24
Peak memory 201500 kb
Host smart-475d3cb3-7a4d-4ad4-83ad-bb3ef1e46b1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166748999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3166748999
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2216634509
Short name T571
Test name
Test status
Simulation time 532195251191 ps
CPU time 1296.32 seconds
Started Aug 02 05:22:50 PM PDT 24
Finished Aug 02 05:44:27 PM PDT 24
Peak memory 201488 kb
Host smart-6aaffb5b-f5dc-48cc-bc26-49ac65c9db0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216634509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2216634509
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2398192542
Short name T793
Test name
Test status
Simulation time 402496708692 ps
CPU time 877.2 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:37:22 PM PDT 24
Peak memory 201472 kb
Host smart-3b4370c4-598b-45d9-adb4-1923ffcdc644
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398192542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2398192542
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3152422541
Short name T227
Test name
Test status
Simulation time 132505004289 ps
CPU time 426.92 seconds
Started Aug 02 05:22:34 PM PDT 24
Finished Aug 02 05:29:41 PM PDT 24
Peak memory 201824 kb
Host smart-6fb72d05-1692-49cc-9ae8-ae99d81ccdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152422541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3152422541
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1333598206
Short name T526
Test name
Test status
Simulation time 32583597259 ps
CPU time 37.67 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:23:15 PM PDT 24
Peak memory 201388 kb
Host smart-74bcb44c-16cd-4a28-8ddb-5b37b4b8fe92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333598206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1333598206
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2297690364
Short name T778
Test name
Test status
Simulation time 3326733055 ps
CPU time 8.98 seconds
Started Aug 02 05:22:40 PM PDT 24
Finished Aug 02 05:22:49 PM PDT 24
Peak memory 201316 kb
Host smart-33c3440e-7105-4c88-9b2c-3b379403308e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297690364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2297690364
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.4126811786
Short name T80
Test name
Test status
Simulation time 4226671933 ps
CPU time 1.84 seconds
Started Aug 02 05:22:41 PM PDT 24
Finished Aug 02 05:22:43 PM PDT 24
Peak memory 217340 kb
Host smart-b35c2b4e-dbc9-4cac-830e-b77206626d57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126811786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.4126811786
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3859476840
Short name T641
Test name
Test status
Simulation time 6114769415 ps
CPU time 3.99 seconds
Started Aug 02 05:22:41 PM PDT 24
Finished Aug 02 05:22:45 PM PDT 24
Peak memory 201424 kb
Host smart-4b80850e-c7dd-41d7-83e9-47b7b770fc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859476840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3859476840
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.465713220
Short name T209
Test name
Test status
Simulation time 203303367189 ps
CPU time 230.28 seconds
Started Aug 02 05:22:47 PM PDT 24
Finished Aug 02 05:26:37 PM PDT 24
Peak memory 201444 kb
Host smart-0eac4f29-bfbd-4eda-bcef-d333893c32ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465713220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.465713220
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1143987612
Short name T43
Test name
Test status
Simulation time 227244783453 ps
CPU time 41.18 seconds
Started Aug 02 05:22:51 PM PDT 24
Finished Aug 02 05:23:32 PM PDT 24
Peak memory 209888 kb
Host smart-43e6c071-29ef-48d4-b790-6585eb7bd012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143987612 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1143987612
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1843339970
Short name T109
Test name
Test status
Simulation time 371797876 ps
CPU time 0.85 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:23:48 PM PDT 24
Peak memory 201280 kb
Host smart-e3a1e72a-47f4-4d78-9510-d48963ae2301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843339970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1843339970
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3090869076
Short name T11
Test name
Test status
Simulation time 162371128421 ps
CPU time 25.1 seconds
Started Aug 02 05:23:50 PM PDT 24
Finished Aug 02 05:24:15 PM PDT 24
Peak memory 201500 kb
Host smart-2422df85-363e-4681-83ba-a54a497557e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090869076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3090869076
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2083166047
Short name T205
Test name
Test status
Simulation time 161191498710 ps
CPU time 93.17 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:25:21 PM PDT 24
Peak memory 201448 kb
Host smart-8da03c48-9e27-46ad-98cd-11fe612c31cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083166047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2083166047
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.4021699315
Short name T760
Test name
Test status
Simulation time 320429590899 ps
CPU time 226.15 seconds
Started Aug 02 05:23:48 PM PDT 24
Finished Aug 02 05:27:34 PM PDT 24
Peak memory 201508 kb
Host smart-9610021a-06d6-430f-9788-eea6e20e7fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021699315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.4021699315
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2763325376
Short name T606
Test name
Test status
Simulation time 488413823527 ps
CPU time 1082.53 seconds
Started Aug 02 05:23:51 PM PDT 24
Finished Aug 02 05:41:53 PM PDT 24
Peak memory 201488 kb
Host smart-850093ec-01fb-4804-abbc-f79932576a3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763325376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2763325376
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.9611914
Short name T345
Test name
Test status
Simulation time 162947330030 ps
CPU time 210.9 seconds
Started Aug 02 05:23:48 PM PDT 24
Finished Aug 02 05:27:19 PM PDT 24
Peak memory 201484 kb
Host smart-e43f3586-ad3b-4a52-b2b1-0e4620ef1c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9611914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.9611914
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.4269475327
Short name T561
Test name
Test status
Simulation time 331242307715 ps
CPU time 222.59 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:27:29 PM PDT 24
Peak memory 201448 kb
Host smart-8d6dde08-8dba-43fb-bd04-42c1aa53fea4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269475327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.4269475327
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3018997507
Short name T190
Test name
Test status
Simulation time 349267324240 ps
CPU time 180.39 seconds
Started Aug 02 05:23:49 PM PDT 24
Finished Aug 02 05:26:50 PM PDT 24
Peak memory 201448 kb
Host smart-bd147690-06cd-481f-80dd-98ffec625ce0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018997507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3018997507
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1051288326
Short name T602
Test name
Test status
Simulation time 200475638695 ps
CPU time 467.12 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 201500 kb
Host smart-6c4de7ce-1854-44ce-98b9-ce3629d5451e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051288326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1051288326
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.816068894
Short name T475
Test name
Test status
Simulation time 136296451033 ps
CPU time 458.27 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:31:25 PM PDT 24
Peak memory 201744 kb
Host smart-a30e7814-9a23-41ee-a8b3-bd17b717c607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816068894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.816068894
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3411695617
Short name T528
Test name
Test status
Simulation time 38130903330 ps
CPU time 20.12 seconds
Started Aug 02 05:23:48 PM PDT 24
Finished Aug 02 05:24:09 PM PDT 24
Peak memory 201440 kb
Host smart-af9adbdc-9723-4c57-a3f2-12a9c2b7adcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411695617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3411695617
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3351243233
Short name T396
Test name
Test status
Simulation time 3372170771 ps
CPU time 4.47 seconds
Started Aug 02 05:23:51 PM PDT 24
Finished Aug 02 05:23:56 PM PDT 24
Peak memory 201412 kb
Host smart-a31f8632-24f0-47a3-aad3-977e657d3b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351243233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3351243233
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.738701689
Short name T451
Test name
Test status
Simulation time 6050518148 ps
CPU time 14.33 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:24:01 PM PDT 24
Peak memory 201380 kb
Host smart-e0286ff2-1c59-48a1-8831-6d15bbee13b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738701689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.738701689
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1996010479
Short name T110
Test name
Test status
Simulation time 810261334595 ps
CPU time 231.1 seconds
Started Aug 02 05:23:46 PM PDT 24
Finished Aug 02 05:27:37 PM PDT 24
Peak memory 209696 kb
Host smart-9c22ae94-736e-453a-8fa7-a9dcb2ff4e30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996010479 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1996010479
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2965943115
Short name T755
Test name
Test status
Simulation time 325738631 ps
CPU time 0.98 seconds
Started Aug 02 05:24:00 PM PDT 24
Finished Aug 02 05:24:01 PM PDT 24
Peak memory 201268 kb
Host smart-11494067-8281-4695-ad3d-7557aaa1eba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965943115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2965943115
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1186959512
Short name T145
Test name
Test status
Simulation time 366729195586 ps
CPU time 798.64 seconds
Started Aug 02 05:23:48 PM PDT 24
Finished Aug 02 05:37:07 PM PDT 24
Peak memory 201432 kb
Host smart-60c4f566-143f-4000-9596-e07b9e428e31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186959512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1186959512
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2660654589
Short name T223
Test name
Test status
Simulation time 330038572578 ps
CPU time 781.55 seconds
Started Aug 02 05:23:49 PM PDT 24
Finished Aug 02 05:36:50 PM PDT 24
Peak memory 201444 kb
Host smart-9187f137-da56-4550-80c5-c49ae76ba886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660654589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2660654589
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2959315384
Short name T200
Test name
Test status
Simulation time 327107923644 ps
CPU time 195.02 seconds
Started Aug 02 05:23:50 PM PDT 24
Finished Aug 02 05:27:05 PM PDT 24
Peak memory 201488 kb
Host smart-f7b6ce30-0cc4-4833-ba12-30c065c18bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959315384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2959315384
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1431798285
Short name T674
Test name
Test status
Simulation time 487299445161 ps
CPU time 121.17 seconds
Started Aug 02 05:23:49 PM PDT 24
Finished Aug 02 05:25:51 PM PDT 24
Peak memory 201484 kb
Host smart-3f8f8d23-9b80-4290-ae73-262b61a46ddc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431798285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1431798285
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3928268458
Short name T731
Test name
Test status
Simulation time 169203209774 ps
CPU time 407.36 seconds
Started Aug 02 05:23:46 PM PDT 24
Finished Aug 02 05:30:34 PM PDT 24
Peak memory 201436 kb
Host smart-38028ca2-05b0-4360-83c1-76728533b07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928268458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3928268458
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3698134428
Short name T468
Test name
Test status
Simulation time 171161295773 ps
CPU time 24.54 seconds
Started Aug 02 05:23:46 PM PDT 24
Finished Aug 02 05:24:10 PM PDT 24
Peak memory 201472 kb
Host smart-5661fd96-a8bc-4dfc-a29e-d70e7d8209b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698134428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3698134428
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3150556165
Short name T162
Test name
Test status
Simulation time 534575774877 ps
CPU time 569.29 seconds
Started Aug 02 05:23:48 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 201516 kb
Host smart-66aeb19b-5018-4537-83a2-58a4c827af74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150556165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3150556165
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2649537748
Short name T412
Test name
Test status
Simulation time 200795074758 ps
CPU time 94.63 seconds
Started Aug 02 05:23:47 PM PDT 24
Finished Aug 02 05:25:22 PM PDT 24
Peak memory 201472 kb
Host smart-b18e7d36-1d3d-4591-bf2f-a73cea0681cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649537748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2649537748
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3768336848
Short name T726
Test name
Test status
Simulation time 118287966026 ps
CPU time 365.61 seconds
Started Aug 02 05:24:01 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 201832 kb
Host smart-58c2ed0e-bba5-4260-a3a7-369368dcb482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768336848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3768336848
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1512163304
Short name T494
Test name
Test status
Simulation time 35772041603 ps
CPU time 72.15 seconds
Started Aug 02 05:24:01 PM PDT 24
Finished Aug 02 05:25:14 PM PDT 24
Peak memory 201368 kb
Host smart-e534053b-6ba1-42e0-886a-cb935d4bc7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512163304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1512163304
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.4205590293
Short name T734
Test name
Test status
Simulation time 3460396834 ps
CPU time 9.33 seconds
Started Aug 02 05:23:51 PM PDT 24
Finished Aug 02 05:24:00 PM PDT 24
Peak memory 201408 kb
Host smart-ee962438-e1ea-42ed-be64-c5b91e4a56c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205590293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.4205590293
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2077653701
Short name T26
Test name
Test status
Simulation time 6051110423 ps
CPU time 3.78 seconds
Started Aug 02 05:23:50 PM PDT 24
Finished Aug 02 05:23:54 PM PDT 24
Peak memory 201420 kb
Host smart-50738765-bee6-455e-8627-8c4fe4f0f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077653701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2077653701
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3374312100
Short name T359
Test name
Test status
Simulation time 298804422615 ps
CPU time 732.3 seconds
Started Aug 02 05:23:59 PM PDT 24
Finished Aug 02 05:36:12 PM PDT 24
Peak memory 210096 kb
Host smart-6a77e3c9-8d85-439c-b136-18668f23fdeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374312100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3374312100
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2773541654
Short name T112
Test name
Test status
Simulation time 154235252851 ps
CPU time 167.54 seconds
Started Aug 02 05:24:03 PM PDT 24
Finished Aug 02 05:26:51 PM PDT 24
Peak memory 210940 kb
Host smart-e2f9d484-febd-4312-b038-06d83f7069be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773541654 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2773541654
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3711559124
Short name T529
Test name
Test status
Simulation time 480950616 ps
CPU time 0.91 seconds
Started Aug 02 05:24:00 PM PDT 24
Finished Aug 02 05:24:01 PM PDT 24
Peak memory 201232 kb
Host smart-f3ebda96-5441-48da-9a65-8e5c0ba839af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711559124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3711559124
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2898005433
Short name T711
Test name
Test status
Simulation time 346460023097 ps
CPU time 190.65 seconds
Started Aug 02 05:24:02 PM PDT 24
Finished Aug 02 05:27:13 PM PDT 24
Peak memory 201536 kb
Host smart-bf0f76dd-dab2-431a-a038-8b2b4ae54f64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898005433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2898005433
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3394616053
Short name T709
Test name
Test status
Simulation time 166901653140 ps
CPU time 395.18 seconds
Started Aug 02 05:24:00 PM PDT 24
Finished Aug 02 05:30:36 PM PDT 24
Peak memory 201484 kb
Host smart-281b9f9b-c8e0-47eb-a228-7aa4bbeec41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394616053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3394616053
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.560823000
Short name T163
Test name
Test status
Simulation time 488192962170 ps
CPU time 289.81 seconds
Started Aug 02 05:23:59 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 201516 kb
Host smart-e45073a6-2724-4499-91ed-4c3caa572cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560823000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.560823000
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2917485465
Short name T421
Test name
Test status
Simulation time 168032831822 ps
CPU time 102.28 seconds
Started Aug 02 05:24:02 PM PDT 24
Finished Aug 02 05:25:44 PM PDT 24
Peak memory 201452 kb
Host smart-8fb2ea31-30fd-4720-a6cd-8ccbf3362e6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917485465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2917485465
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1362382523
Short name T513
Test name
Test status
Simulation time 161431055770 ps
CPU time 177.14 seconds
Started Aug 02 05:24:02 PM PDT 24
Finished Aug 02 05:27:00 PM PDT 24
Peak memory 201504 kb
Host smart-924f0b95-30fd-40ed-b1fb-62fe79bcdcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362382523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1362382523
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3473800806
Short name T712
Test name
Test status
Simulation time 497284052582 ps
CPU time 90.02 seconds
Started Aug 02 05:23:59 PM PDT 24
Finished Aug 02 05:25:29 PM PDT 24
Peak memory 201504 kb
Host smart-32dfcb8f-9a81-4dd3-b1f2-c8f7279ef811
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473800806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3473800806
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3446155280
Short name T313
Test name
Test status
Simulation time 358043894917 ps
CPU time 65.71 seconds
Started Aug 02 05:24:02 PM PDT 24
Finished Aug 02 05:25:08 PM PDT 24
Peak memory 201508 kb
Host smart-5397d416-7fb9-4260-a8fb-ce84228dd061
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446155280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3446155280
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4245435633
Short name T197
Test name
Test status
Simulation time 582440656576 ps
CPU time 314.37 seconds
Started Aug 02 05:24:00 PM PDT 24
Finished Aug 02 05:29:15 PM PDT 24
Peak memory 201428 kb
Host smart-469c4c07-6600-488f-8194-c9d498b7c6a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245435633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4245435633
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.308513009
Short name T32
Test name
Test status
Simulation time 101560667758 ps
CPU time 339.35 seconds
Started Aug 02 05:24:01 PM PDT 24
Finished Aug 02 05:29:41 PM PDT 24
Peak memory 201900 kb
Host smart-7e80bfec-ccf9-404c-9371-48b0943a0dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308513009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.308513009
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.633025236
Short name T367
Test name
Test status
Simulation time 38390812009 ps
CPU time 23.35 seconds
Started Aug 02 05:24:01 PM PDT 24
Finished Aug 02 05:24:24 PM PDT 24
Peak memory 201356 kb
Host smart-0d41719f-e4c4-4eb4-aba1-46d325691b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633025236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.633025236
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.393230372
Short name T601
Test name
Test status
Simulation time 5018547085 ps
CPU time 3.73 seconds
Started Aug 02 05:24:01 PM PDT 24
Finished Aug 02 05:24:04 PM PDT 24
Peak memory 201352 kb
Host smart-e74d2d82-9e57-4726-be2f-9d10d6637e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393230372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.393230372
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3568982807
Short name T591
Test name
Test status
Simulation time 5885440415 ps
CPU time 5.2 seconds
Started Aug 02 05:24:02 PM PDT 24
Finished Aug 02 05:24:07 PM PDT 24
Peak memory 201316 kb
Host smart-cd4413b5-1abf-4b4e-86d6-df34f9f4bc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568982807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3568982807
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3876992762
Short name T465
Test name
Test status
Simulation time 310460151209 ps
CPU time 990.62 seconds
Started Aug 02 05:24:00 PM PDT 24
Finished Aug 02 05:40:31 PM PDT 24
Peak memory 210016 kb
Host smart-8eece23d-44ba-4688-8265-3669b74163c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876992762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3876992762
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3742081645
Short name T258
Test name
Test status
Simulation time 149816730319 ps
CPU time 90.98 seconds
Started Aug 02 05:24:03 PM PDT 24
Finished Aug 02 05:25:34 PM PDT 24
Peak memory 209780 kb
Host smart-29579b80-6d04-4fe4-af89-54ae0dcd38b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742081645 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3742081645
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3388391764
Short name T97
Test name
Test status
Simulation time 422315711 ps
CPU time 1.56 seconds
Started Aug 02 05:24:12 PM PDT 24
Finished Aug 02 05:24:13 PM PDT 24
Peak memory 201208 kb
Host smart-dcd128e0-84b0-4054-bbc8-a4f2762b86bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388391764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3388391764
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.863799987
Short name T46
Test name
Test status
Simulation time 180391917038 ps
CPU time 106.15 seconds
Started Aug 02 05:24:11 PM PDT 24
Finished Aug 02 05:25:57 PM PDT 24
Peak memory 201456 kb
Host smart-c43fd829-65bd-4a5d-975d-89f88f88e802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863799987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.863799987
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.145227335
Short name T156
Test name
Test status
Simulation time 330205109776 ps
CPU time 379.24 seconds
Started Aug 02 05:24:01 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 201464 kb
Host smart-28ed8f88-4f45-4f88-aed2-84e6477883c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145227335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.145227335
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3682704746
Short name T449
Test name
Test status
Simulation time 488880685796 ps
CPU time 271.01 seconds
Started Aug 02 05:24:00 PM PDT 24
Finished Aug 02 05:28:31 PM PDT 24
Peak memory 201496 kb
Host smart-45245234-54f6-4344-9804-4779321e2503
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682704746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3682704746
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1297030506
Short name T798
Test name
Test status
Simulation time 484185636304 ps
CPU time 357.18 seconds
Started Aug 02 05:24:00 PM PDT 24
Finished Aug 02 05:29:58 PM PDT 24
Peak memory 201504 kb
Host smart-f1ea9dbd-02cb-4aeb-832d-ebdb3c791f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297030506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1297030506
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1771802856
Short name T470
Test name
Test status
Simulation time 164817159484 ps
CPU time 99.35 seconds
Started Aug 02 05:24:02 PM PDT 24
Finished Aug 02 05:25:42 PM PDT 24
Peak memory 201488 kb
Host smart-d89cac54-c37d-46bf-9992-d50561fcd0f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771802856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1771802856
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2487979489
Short name T401
Test name
Test status
Simulation time 203551056101 ps
CPU time 134.57 seconds
Started Aug 02 05:24:09 PM PDT 24
Finished Aug 02 05:26:24 PM PDT 24
Peak memory 201436 kb
Host smart-0b237e5a-f805-463d-8345-f6a550ea98cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487979489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2487979489
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2931720414
Short name T517
Test name
Test status
Simulation time 94866275092 ps
CPU time 492.11 seconds
Started Aug 02 05:24:09 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 201936 kb
Host smart-1886f3fc-63d3-49f0-96e7-c06ac795c577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931720414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2931720414
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3164574502
Short name T583
Test name
Test status
Simulation time 34429120438 ps
CPU time 78.66 seconds
Started Aug 02 05:24:10 PM PDT 24
Finished Aug 02 05:25:29 PM PDT 24
Peak memory 201416 kb
Host smart-7d2030bb-471a-476f-98a7-a04273821dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164574502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3164574502
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1442097759
Short name T790
Test name
Test status
Simulation time 4852953346 ps
CPU time 12.3 seconds
Started Aug 02 05:24:08 PM PDT 24
Finished Aug 02 05:24:20 PM PDT 24
Peak memory 201384 kb
Host smart-347d18b1-22b0-4f55-9cb8-fd8567501b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442097759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1442097759
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2022525630
Short name T433
Test name
Test status
Simulation time 6067803832 ps
CPU time 7.36 seconds
Started Aug 02 05:23:59 PM PDT 24
Finished Aug 02 05:24:06 PM PDT 24
Peak memory 201416 kb
Host smart-f4f9af9d-8edd-4811-9d8c-381956954fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022525630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2022525630
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.653257590
Short name T230
Test name
Test status
Simulation time 338862483736 ps
CPU time 1062.19 seconds
Started Aug 02 05:24:08 PM PDT 24
Finished Aug 02 05:41:51 PM PDT 24
Peak memory 218188 kb
Host smart-6ba68893-32ea-4ce1-bf53-00a7c9fd7ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653257590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
653257590
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.694870176
Short name T299
Test name
Test status
Simulation time 66673395109 ps
CPU time 107.17 seconds
Started Aug 02 05:24:10 PM PDT 24
Finished Aug 02 05:25:57 PM PDT 24
Peak memory 217408 kb
Host smart-e16fdb2b-3ac7-4b66-a069-86f04554adda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694870176 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.694870176
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.857400072
Short name T683
Test name
Test status
Simulation time 532008286 ps
CPU time 1.07 seconds
Started Aug 02 05:24:10 PM PDT 24
Finished Aug 02 05:24:11 PM PDT 24
Peak memory 201276 kb
Host smart-ad31a38c-241e-42cf-b24d-eac8a6d91bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857400072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.857400072
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1763539276
Short name T637
Test name
Test status
Simulation time 165031249447 ps
CPU time 81.99 seconds
Started Aug 02 05:24:10 PM PDT 24
Finished Aug 02 05:25:32 PM PDT 24
Peak memory 201544 kb
Host smart-bf0cbae6-2157-48f7-b760-7a3458228ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763539276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1763539276
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.963400416
Short name T158
Test name
Test status
Simulation time 494482513285 ps
CPU time 274 seconds
Started Aug 02 05:24:09 PM PDT 24
Finished Aug 02 05:28:43 PM PDT 24
Peak memory 201412 kb
Host smart-7548511c-92a0-4abb-8a86-6b817d8c9bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963400416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.963400416
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1824400081
Short name T753
Test name
Test status
Simulation time 162559834146 ps
CPU time 187.17 seconds
Started Aug 02 05:24:10 PM PDT 24
Finished Aug 02 05:27:18 PM PDT 24
Peak memory 201424 kb
Host smart-44ff233f-a55f-41ae-a330-0f92195ebe7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824400081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1824400081
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1341920497
Short name T614
Test name
Test status
Simulation time 161045313976 ps
CPU time 384.15 seconds
Started Aug 02 05:24:12 PM PDT 24
Finished Aug 02 05:30:37 PM PDT 24
Peak memory 201472 kb
Host smart-86b3dbe9-4a26-47d2-bed6-50a4f862eb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341920497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1341920497
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2839237024
Short name T10
Test name
Test status
Simulation time 497903571219 ps
CPU time 309.66 seconds
Started Aug 02 05:24:13 PM PDT 24
Finished Aug 02 05:29:23 PM PDT 24
Peak memory 201468 kb
Host smart-58fcd95a-7b3e-4062-99cf-1e63b464fab3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839237024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2839237024
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3105144220
Short name T558
Test name
Test status
Simulation time 610245674253 ps
CPU time 1006.66 seconds
Started Aug 02 05:24:12 PM PDT 24
Finished Aug 02 05:40:58 PM PDT 24
Peak memory 201516 kb
Host smart-8f454810-a1a7-496d-b444-3dbcc07ad2f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105144220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3105144220
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3608811244
Short name T228
Test name
Test status
Simulation time 83019763721 ps
CPU time 438.35 seconds
Started Aug 02 05:24:09 PM PDT 24
Finished Aug 02 05:31:27 PM PDT 24
Peak memory 201832 kb
Host smart-d7562452-c163-4b12-be11-9e24bbeefde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608811244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3608811244
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.276070006
Short name T390
Test name
Test status
Simulation time 29312421115 ps
CPU time 59.54 seconds
Started Aug 02 05:24:11 PM PDT 24
Finished Aug 02 05:25:11 PM PDT 24
Peak memory 201408 kb
Host smart-4772a5aa-9f23-437a-84da-6922f017fb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276070006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.276070006
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3592698529
Short name T414
Test name
Test status
Simulation time 3250201032 ps
CPU time 2.61 seconds
Started Aug 02 05:24:10 PM PDT 24
Finished Aug 02 05:24:13 PM PDT 24
Peak memory 201388 kb
Host smart-e3b4e782-3e75-44ec-8973-a56925ac6663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592698529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3592698529
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.104927003
Short name T514
Test name
Test status
Simulation time 5979263712 ps
CPU time 5.75 seconds
Started Aug 02 05:24:12 PM PDT 24
Finished Aug 02 05:24:17 PM PDT 24
Peak memory 201344 kb
Host smart-973af23f-fa19-4646-acd2-ac84dd5212d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104927003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.104927003
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1086371832
Short name T519
Test name
Test status
Simulation time 212328761038 ps
CPU time 138.84 seconds
Started Aug 02 05:24:09 PM PDT 24
Finished Aug 02 05:26:28 PM PDT 24
Peak memory 201452 kb
Host smart-61086de4-8062-4dcc-bada-22b0de82fb54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086371832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1086371832
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1143394574
Short name T657
Test name
Test status
Simulation time 510739481340 ps
CPU time 1034.59 seconds
Started Aug 02 05:24:11 PM PDT 24
Finished Aug 02 05:41:26 PM PDT 24
Peak memory 210392 kb
Host smart-be930dc6-bf75-493b-8c78-655eb74558c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143394574 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1143394574
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2477035835
Short name T532
Test name
Test status
Simulation time 345632361 ps
CPU time 0.93 seconds
Started Aug 02 05:24:17 PM PDT 24
Finished Aug 02 05:24:18 PM PDT 24
Peak memory 201312 kb
Host smart-bccc97dc-b08b-409d-9107-a01e66e17d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477035835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2477035835
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3411474557
Short name T789
Test name
Test status
Simulation time 164554251508 ps
CPU time 365.57 seconds
Started Aug 02 05:24:08 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 201420 kb
Host smart-70f9a9c2-008b-46e8-827e-057eb831f839
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411474557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3411474557
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2070137524
Short name T353
Test name
Test status
Simulation time 483095801118 ps
CPU time 1047.91 seconds
Started Aug 02 05:24:11 PM PDT 24
Finished Aug 02 05:41:39 PM PDT 24
Peak memory 201476 kb
Host smart-39c6f917-77a2-4db1-a790-d5e07ab4da05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070137524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2070137524
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2177247921
Short name T474
Test name
Test status
Simulation time 163711870884 ps
CPU time 174.18 seconds
Started Aug 02 05:24:11 PM PDT 24
Finished Aug 02 05:27:05 PM PDT 24
Peak memory 201480 kb
Host smart-cd331906-0b06-4559-9c11-9f5002bcba31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177247921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2177247921
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.904710654
Short name T247
Test name
Test status
Simulation time 328627955615 ps
CPU time 190.74 seconds
Started Aug 02 05:24:07 PM PDT 24
Finished Aug 02 05:27:18 PM PDT 24
Peak memory 201368 kb
Host smart-2cd0d32c-5a80-46a6-b237-240c5277a683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904710654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.904710654
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2285266754
Short name T749
Test name
Test status
Simulation time 482897239208 ps
CPU time 568.31 seconds
Started Aug 02 05:24:11 PM PDT 24
Finished Aug 02 05:33:39 PM PDT 24
Peak memory 201472 kb
Host smart-41acb70b-44e3-4c23-8c9f-7d0fdf4fdd6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285266754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2285266754
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1520976294
Short name T545
Test name
Test status
Simulation time 194874423025 ps
CPU time 459.53 seconds
Started Aug 02 05:24:10 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 201512 kb
Host smart-a9c3185a-a2b1-4766-8feb-465d46e63e61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520976294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1520976294
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3454563035
Short name T232
Test name
Test status
Simulation time 123885066947 ps
CPU time 659.82 seconds
Started Aug 02 05:24:17 PM PDT 24
Finished Aug 02 05:35:17 PM PDT 24
Peak memory 201828 kb
Host smart-ca15e873-3498-467b-8fba-2aeab7ecf4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454563035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3454563035
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1475020736
Short name T405
Test name
Test status
Simulation time 25434576191 ps
CPU time 29.04 seconds
Started Aug 02 05:24:17 PM PDT 24
Finished Aug 02 05:24:46 PM PDT 24
Peak memory 201324 kb
Host smart-4fd395a4-6769-4333-b8e6-48824dd2196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475020736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1475020736
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2938558025
Short name T206
Test name
Test status
Simulation time 4553254492 ps
CPU time 11.03 seconds
Started Aug 02 05:24:15 PM PDT 24
Finished Aug 02 05:24:26 PM PDT 24
Peak memory 201368 kb
Host smart-4d680d42-6f5a-4680-bac9-2bb3e0e182bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938558025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2938558025
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3463966689
Short name T484
Test name
Test status
Simulation time 5864310967 ps
CPU time 4.17 seconds
Started Aug 02 05:24:08 PM PDT 24
Finished Aug 02 05:24:12 PM PDT 24
Peak memory 201392 kb
Host smart-02d7fe42-2650-412c-9c27-938f5dc0c8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463966689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3463966689
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.736480248
Short name T622
Test name
Test status
Simulation time 373212099198 ps
CPU time 105.4 seconds
Started Aug 02 05:24:17 PM PDT 24
Finished Aug 02 05:26:03 PM PDT 24
Peak memory 201564 kb
Host smart-f9e2dc32-fbad-4ba8-82c6-27316648558d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736480248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
736480248
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.9059569
Short name T324
Test name
Test status
Simulation time 227438264084 ps
CPU time 280.97 seconds
Started Aug 02 05:24:16 PM PDT 24
Finished Aug 02 05:28:57 PM PDT 24
Peak memory 201620 kb
Host smart-f06459b1-eaa7-492f-8a01-77194712c985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9059569 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.9059569
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2185357056
Short name T718
Test name
Test status
Simulation time 401607800 ps
CPU time 1.58 seconds
Started Aug 02 05:24:28 PM PDT 24
Finished Aug 02 05:24:30 PM PDT 24
Peak memory 201256 kb
Host smart-5080b61b-98d0-4f41-8682-52628418343f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185357056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2185357056
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3604252564
Short name T292
Test name
Test status
Simulation time 169114653964 ps
CPU time 317.69 seconds
Started Aug 02 05:24:16 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 201452 kb
Host smart-1b2c998e-94ed-4d3c-8e99-49dbf7c4b20d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604252564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3604252564
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.181195216
Short name T253
Test name
Test status
Simulation time 164963549094 ps
CPU time 188.52 seconds
Started Aug 02 05:24:16 PM PDT 24
Finished Aug 02 05:27:24 PM PDT 24
Peak memory 201544 kb
Host smart-2c596cd5-9942-4c1d-8521-84ba38668c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181195216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.181195216
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.858514702
Short name T524
Test name
Test status
Simulation time 334006300965 ps
CPU time 197.33 seconds
Started Aug 02 05:24:18 PM PDT 24
Finished Aug 02 05:27:35 PM PDT 24
Peak memory 201500 kb
Host smart-6822288d-13af-4d88-bf2b-9987e7801b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858514702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.858514702
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3450447199
Short name T766
Test name
Test status
Simulation time 164979406214 ps
CPU time 340.77 seconds
Started Aug 02 05:24:16 PM PDT 24
Finished Aug 02 05:29:57 PM PDT 24
Peak memory 201508 kb
Host smart-35cdb420-a2ba-4651-842b-0f74f8602f11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450447199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3450447199
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.114675411
Short name T348
Test name
Test status
Simulation time 324557723574 ps
CPU time 214.14 seconds
Started Aug 02 05:24:15 PM PDT 24
Finished Aug 02 05:27:50 PM PDT 24
Peak memory 201492 kb
Host smart-f6363693-329e-4567-b44e-64ad48ad3e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114675411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.114675411
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2761792907
Short name T385
Test name
Test status
Simulation time 330471535497 ps
CPU time 750.41 seconds
Started Aug 02 05:24:17 PM PDT 24
Finished Aug 02 05:36:48 PM PDT 24
Peak memory 201448 kb
Host smart-dfe0f046-6e2e-46dd-a2f9-5458edd6da60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761792907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2761792907
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1449489049
Short name T621
Test name
Test status
Simulation time 164837741551 ps
CPU time 49.85 seconds
Started Aug 02 05:24:15 PM PDT 24
Finished Aug 02 05:25:05 PM PDT 24
Peak memory 201508 kb
Host smart-fcf7b259-6984-4c6d-ac36-81054e944bf8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449489049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1449489049
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1355033017
Short name T95
Test name
Test status
Simulation time 598471405186 ps
CPU time 695.67 seconds
Started Aug 02 05:24:16 PM PDT 24
Finished Aug 02 05:35:51 PM PDT 24
Peak memory 201456 kb
Host smart-57425d4b-1c19-4bc0-a1a2-83b04ff0c281
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355033017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1355033017
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2439933550
Short name T236
Test name
Test status
Simulation time 133498007613 ps
CPU time 539.08 seconds
Started Aug 02 05:24:19 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 201636 kb
Host smart-3871087c-9982-4080-8e93-27a22b7915ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439933550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2439933550
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.496506590
Short name T620
Test name
Test status
Simulation time 41965545554 ps
CPU time 94.2 seconds
Started Aug 02 05:24:16 PM PDT 24
Finished Aug 02 05:25:50 PM PDT 24
Peak memory 201348 kb
Host smart-dffc8594-fa48-4ae2-9f07-128f84adacb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496506590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.496506590
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3417565002
Short name T378
Test name
Test status
Simulation time 3690145990 ps
CPU time 1.66 seconds
Started Aug 02 05:24:17 PM PDT 24
Finished Aug 02 05:24:19 PM PDT 24
Peak memory 201320 kb
Host smart-f18186b9-239a-466c-a7df-096389446dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417565002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3417565002
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3285557766
Short name T796
Test name
Test status
Simulation time 6092046240 ps
CPU time 4.62 seconds
Started Aug 02 05:24:16 PM PDT 24
Finished Aug 02 05:24:21 PM PDT 24
Peak memory 201388 kb
Host smart-2c292ed8-e024-44b6-9a7b-1c75a61bc86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285557766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3285557766
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2381837922
Short name T762
Test name
Test status
Simulation time 14679092887 ps
CPU time 73.92 seconds
Started Aug 02 05:24:18 PM PDT 24
Finished Aug 02 05:25:32 PM PDT 24
Peak memory 210184 kb
Host smart-4fd67c93-d92f-43cb-9642-2e7e0c0c7cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381837922 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2381837922
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.976294481
Short name T604
Test name
Test status
Simulation time 430579191 ps
CPU time 1.59 seconds
Started Aug 02 05:24:28 PM PDT 24
Finished Aug 02 05:24:30 PM PDT 24
Peak memory 201260 kb
Host smart-0aea720c-8a5f-46e5-825b-93ab9095bf1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976294481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.976294481
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1518268393
Short name T327
Test name
Test status
Simulation time 347191540699 ps
CPU time 181 seconds
Started Aug 02 05:24:25 PM PDT 24
Finished Aug 02 05:27:26 PM PDT 24
Peak memory 201464 kb
Host smart-1ed81ff9-a9db-4475-a1f7-e88cbcdac297
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518268393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1518268393
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.223076144
Short name T757
Test name
Test status
Simulation time 329131788195 ps
CPU time 336.49 seconds
Started Aug 02 05:24:24 PM PDT 24
Finished Aug 02 05:30:01 PM PDT 24
Peak memory 201440 kb
Host smart-481553e8-0084-4f0d-9daf-e501ec0e01d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223076144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.223076144
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2354796719
Short name T696
Test name
Test status
Simulation time 336503216639 ps
CPU time 719.11 seconds
Started Aug 02 05:24:26 PM PDT 24
Finished Aug 02 05:36:25 PM PDT 24
Peak memory 201464 kb
Host smart-852f6a41-74de-460a-8459-e368e17219a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354796719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2354796719
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3746505266
Short name T705
Test name
Test status
Simulation time 160166339379 ps
CPU time 192.08 seconds
Started Aug 02 05:24:26 PM PDT 24
Finished Aug 02 05:27:38 PM PDT 24
Peak memory 201520 kb
Host smart-27703627-567e-4cdb-905f-bad7a0c22961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746505266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3746505266
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.4249134345
Short name T555
Test name
Test status
Simulation time 162372610746 ps
CPU time 51.39 seconds
Started Aug 02 05:24:26 PM PDT 24
Finished Aug 02 05:25:18 PM PDT 24
Peak memory 201468 kb
Host smart-63e9ba9f-3dae-4261-a184-f3becaceceba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249134345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.4249134345
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1030875221
Short name T773
Test name
Test status
Simulation time 183674297655 ps
CPU time 107.35 seconds
Started Aug 02 05:24:24 PM PDT 24
Finished Aug 02 05:26:12 PM PDT 24
Peak memory 201520 kb
Host smart-5a7f2165-9c03-40c4-a587-38a14d7e0df1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030875221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1030875221
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1886121376
Short name T717
Test name
Test status
Simulation time 619246768643 ps
CPU time 135.18 seconds
Started Aug 02 05:24:23 PM PDT 24
Finished Aug 02 05:26:39 PM PDT 24
Peak memory 201476 kb
Host smart-d0dee265-5d38-4bf1-a293-e327a71ff1d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886121376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1886121376
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4170073357
Short name T509
Test name
Test status
Simulation time 74910553030 ps
CPU time 333.66 seconds
Started Aug 02 05:24:22 PM PDT 24
Finished Aug 02 05:29:56 PM PDT 24
Peak memory 201840 kb
Host smart-1a7cfadd-aeee-421e-a07b-da82894f38b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170073357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4170073357
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.314558672
Short name T440
Test name
Test status
Simulation time 39568170836 ps
CPU time 21.04 seconds
Started Aug 02 05:24:25 PM PDT 24
Finished Aug 02 05:24:46 PM PDT 24
Peak memory 201388 kb
Host smart-2cdadd01-6cb8-4998-ac00-1495d3723041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314558672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.314558672
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.961199288
Short name T795
Test name
Test status
Simulation time 4148589173 ps
CPU time 9.97 seconds
Started Aug 02 05:24:23 PM PDT 24
Finished Aug 02 05:24:34 PM PDT 24
Peak memory 201352 kb
Host smart-19ab85c5-014d-4f98-bf50-d2ca3d1b382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961199288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.961199288
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2726137883
Short name T383
Test name
Test status
Simulation time 5601422565 ps
CPU time 14.38 seconds
Started Aug 02 05:24:29 PM PDT 24
Finished Aug 02 05:24:43 PM PDT 24
Peak memory 201384 kb
Host smart-58d66c3b-3867-465d-9cc4-c3fb0a6ca6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726137883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2726137883
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2134223166
Short name T36
Test name
Test status
Simulation time 388897109383 ps
CPU time 60.3 seconds
Started Aug 02 05:24:23 PM PDT 24
Finished Aug 02 05:25:24 PM PDT 24
Peak memory 201464 kb
Host smart-f6a5b0b4-cee9-4781-931a-3c5d426cdc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134223166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2134223166
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3496524707
Short name T685
Test name
Test status
Simulation time 405312332 ps
CPU time 1.05 seconds
Started Aug 02 05:24:30 PM PDT 24
Finished Aug 02 05:24:32 PM PDT 24
Peak memory 201240 kb
Host smart-bbd7fb26-1042-4762-ad74-01bcb166c5a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496524707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3496524707
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2613033379
Short name T254
Test name
Test status
Simulation time 188386319422 ps
CPU time 223 seconds
Started Aug 02 05:24:29 PM PDT 24
Finished Aug 02 05:28:13 PM PDT 24
Peak memory 201528 kb
Host smart-3600b76b-9364-4a61-af32-4e19284b48e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613033379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2613033379
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.548443520
Short name T316
Test name
Test status
Simulation time 329013762828 ps
CPU time 732.84 seconds
Started Aug 02 05:24:32 PM PDT 24
Finished Aug 02 05:36:45 PM PDT 24
Peak memory 201448 kb
Host smart-516eb256-ce9e-42a1-96d4-19e52ad81a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548443520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.548443520
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1781314325
Short name T442
Test name
Test status
Simulation time 486519497948 ps
CPU time 342.58 seconds
Started Aug 02 05:24:31 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 201508 kb
Host smart-3a95552f-92a9-4f95-b3bc-cfe0cbb8e1c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781314325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1781314325
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3643636273
Short name T322
Test name
Test status
Simulation time 321008413805 ps
CPU time 125.78 seconds
Started Aug 02 05:24:24 PM PDT 24
Finished Aug 02 05:26:30 PM PDT 24
Peak memory 201428 kb
Host smart-8edb6a50-4e1c-4a45-af01-9f5f7fffe192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643636273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3643636273
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2268663648
Short name T788
Test name
Test status
Simulation time 337485370544 ps
CPU time 787.24 seconds
Started Aug 02 05:24:32 PM PDT 24
Finished Aug 02 05:37:40 PM PDT 24
Peak memory 201452 kb
Host smart-1616fc08-d373-4f6c-84a4-1d6d80c460d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268663648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2268663648
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1219484102
Short name T221
Test name
Test status
Simulation time 563386483477 ps
CPU time 1217.74 seconds
Started Aug 02 05:24:30 PM PDT 24
Finished Aug 02 05:44:48 PM PDT 24
Peak memory 201504 kb
Host smart-13fd4e4b-e149-4457-96ce-a58aa90b6aed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219484102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1219484102
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2023475467
Short name T437
Test name
Test status
Simulation time 204578412141 ps
CPU time 134.22 seconds
Started Aug 02 05:24:31 PM PDT 24
Finished Aug 02 05:26:45 PM PDT 24
Peak memory 201472 kb
Host smart-ddcaca8e-f672-47e4-a7ae-6ee3db3cd2d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023475467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2023475467
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1849997035
Short name T682
Test name
Test status
Simulation time 119681145713 ps
CPU time 611.45 seconds
Started Aug 02 05:24:29 PM PDT 24
Finished Aug 02 05:34:41 PM PDT 24
Peak memory 201860 kb
Host smart-663534ed-92bd-4285-8a85-bc3ef0a4afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849997035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1849997035
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.341899026
Short name T382
Test name
Test status
Simulation time 32256992950 ps
CPU time 20.08 seconds
Started Aug 02 05:24:31 PM PDT 24
Finished Aug 02 05:24:51 PM PDT 24
Peak memory 201360 kb
Host smart-5130fdff-0e5d-4a94-9ee4-17885f66bf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341899026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.341899026
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2934828517
Short name T404
Test name
Test status
Simulation time 4640834960 ps
CPU time 3.35 seconds
Started Aug 02 05:24:32 PM PDT 24
Finished Aug 02 05:24:36 PM PDT 24
Peak memory 201420 kb
Host smart-7c27fb8f-858e-44c1-8282-f29f8a023435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934828517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2934828517
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1381415475
Short name T392
Test name
Test status
Simulation time 5942121747 ps
CPU time 14.72 seconds
Started Aug 02 05:24:22 PM PDT 24
Finished Aug 02 05:24:37 PM PDT 24
Peak memory 201404 kb
Host smart-1da711ef-cafc-4940-9d45-98e425d0e20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381415475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1381415475
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3053298215
Short name T252
Test name
Test status
Simulation time 450523417348 ps
CPU time 1388.31 seconds
Started Aug 02 05:24:30 PM PDT 24
Finished Aug 02 05:47:38 PM PDT 24
Peak memory 201852 kb
Host smart-60575948-3301-4cc7-97fa-99f43c68d44d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053298215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3053298215
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1989975440
Short name T217
Test name
Test status
Simulation time 437410864 ps
CPU time 1.55 seconds
Started Aug 02 05:24:36 PM PDT 24
Finished Aug 02 05:24:37 PM PDT 24
Peak memory 201284 kb
Host smart-6b7afceb-66ab-4718-a545-26be9ec18f5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989975440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1989975440
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1738119047
Short name T708
Test name
Test status
Simulation time 356377577246 ps
CPU time 814.45 seconds
Started Aug 02 05:24:37 PM PDT 24
Finished Aug 02 05:38:12 PM PDT 24
Peak memory 201508 kb
Host smart-ea7d189a-ab76-46aa-8c6c-9f3d04763b27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738119047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1738119047
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2037689144
Short name T344
Test name
Test status
Simulation time 163790441705 ps
CPU time 402.06 seconds
Started Aug 02 05:24:30 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 201512 kb
Host smart-8e00a9aa-09eb-4d5c-af11-9ca3df3ec985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037689144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2037689144
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1102017938
Short name T428
Test name
Test status
Simulation time 167260374335 ps
CPU time 102.8 seconds
Started Aug 02 05:24:30 PM PDT 24
Finished Aug 02 05:26:13 PM PDT 24
Peak memory 201508 kb
Host smart-08731896-1b6d-4080-955f-a0daaa3007fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102017938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1102017938
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1414673427
Short name T612
Test name
Test status
Simulation time 158408899231 ps
CPU time 170.19 seconds
Started Aug 02 05:24:32 PM PDT 24
Finished Aug 02 05:27:22 PM PDT 24
Peak memory 201504 kb
Host smart-bea5c4f5-f1c5-4e63-9f82-05fc76f39a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414673427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1414673427
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3166602752
Short name T521
Test name
Test status
Simulation time 332184548426 ps
CPU time 84.14 seconds
Started Aug 02 05:24:30 PM PDT 24
Finished Aug 02 05:25:55 PM PDT 24
Peak memory 201504 kb
Host smart-a787a61f-5e9e-4447-b4f2-da413a2821f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166602752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3166602752
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.4090308967
Short name T782
Test name
Test status
Simulation time 589525863259 ps
CPU time 653.17 seconds
Started Aug 02 05:24:39 PM PDT 24
Finished Aug 02 05:35:32 PM PDT 24
Peak memory 201440 kb
Host smart-c6efc9e2-9d40-43b9-8d7e-c92952a45d73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090308967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.4090308967
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3958972828
Short name T9
Test name
Test status
Simulation time 76311969250 ps
CPU time 408.76 seconds
Started Aug 02 05:24:38 PM PDT 24
Finished Aug 02 05:31:27 PM PDT 24
Peak memory 201832 kb
Host smart-bba62a2b-08cf-4f80-8695-4a8447ab2fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958972828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3958972828
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.108037027
Short name T548
Test name
Test status
Simulation time 30023376656 ps
CPU time 8.15 seconds
Started Aug 02 05:24:39 PM PDT 24
Finished Aug 02 05:24:47 PM PDT 24
Peak memory 201380 kb
Host smart-57b33cee-d22a-4470-a6c2-36f64fc57cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108037027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.108037027
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.357074136
Short name T664
Test name
Test status
Simulation time 4369949902 ps
CPU time 1.18 seconds
Started Aug 02 05:24:37 PM PDT 24
Finished Aug 02 05:24:39 PM PDT 24
Peak memory 201412 kb
Host smart-538eb291-3530-4c94-85c6-460bff19f29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357074136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.357074136
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.869616459
Short name T420
Test name
Test status
Simulation time 5812694287 ps
CPU time 13.4 seconds
Started Aug 02 05:24:30 PM PDT 24
Finished Aug 02 05:24:44 PM PDT 24
Peak memory 201392 kb
Host smart-3373c156-3852-4877-97f8-5cf541f51693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869616459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.869616459
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3761116490
Short name T309
Test name
Test status
Simulation time 504035153474 ps
CPU time 277.04 seconds
Started Aug 02 05:24:36 PM PDT 24
Finished Aug 02 05:29:13 PM PDT 24
Peak memory 201432 kb
Host smart-21ebba2e-6cad-4d2f-ac57-5aee63c18d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761116490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3761116490
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1966098675
Short name T24
Test name
Test status
Simulation time 226698629207 ps
CPU time 131.16 seconds
Started Aug 02 05:24:38 PM PDT 24
Finished Aug 02 05:26:49 PM PDT 24
Peak memory 210200 kb
Host smart-5078bbd6-4369-468f-9355-5b65a13c4cb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966098675 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1966098675
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1968726946
Short name T694
Test name
Test status
Simulation time 399877118 ps
CPU time 0.95 seconds
Started Aug 02 05:22:40 PM PDT 24
Finished Aug 02 05:22:41 PM PDT 24
Peak memory 201316 kb
Host smart-899b9ad5-b6e3-4fdd-bf86-ce01c1fb0345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968726946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1968726946
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3880621458
Short name T308
Test name
Test status
Simulation time 558117306505 ps
CPU time 296.94 seconds
Started Aug 02 05:22:40 PM PDT 24
Finished Aug 02 05:27:37 PM PDT 24
Peak memory 201528 kb
Host smart-dd8b7d16-f0e5-46f0-b635-9cf885034227
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880621458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3880621458
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.473055832
Short name T569
Test name
Test status
Simulation time 173554677770 ps
CPU time 96.8 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:24:26 PM PDT 24
Peak memory 201488 kb
Host smart-170c2fc0-7579-4ce4-8398-20375a467ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473055832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.473055832
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1004568901
Short name T665
Test name
Test status
Simulation time 162128443079 ps
CPU time 184.54 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:25:50 PM PDT 24
Peak memory 201468 kb
Host smart-71986868-b76b-4952-8b88-637951954651
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004568901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1004568901
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1892529186
Short name T550
Test name
Test status
Simulation time 160134008148 ps
CPU time 353.51 seconds
Started Aug 02 05:22:36 PM PDT 24
Finished Aug 02 05:28:29 PM PDT 24
Peak memory 201504 kb
Host smart-ff18b1f4-9a3a-4ea2-9c52-e053938fdfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892529186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1892529186
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2223714734
Short name T573
Test name
Test status
Simulation time 160623019116 ps
CPU time 350.74 seconds
Started Aug 02 05:22:36 PM PDT 24
Finished Aug 02 05:28:27 PM PDT 24
Peak memory 201376 kb
Host smart-bfc007b8-3c18-4c63-bd79-8003b6d3fc4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223714734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2223714734
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2129519937
Short name T284
Test name
Test status
Simulation time 179425230021 ps
CPU time 187.01 seconds
Started Aug 02 05:22:34 PM PDT 24
Finished Aug 02 05:25:41 PM PDT 24
Peak memory 201476 kb
Host smart-cd259b19-ef65-4109-ab8c-d9fb25c4df42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129519937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2129519937
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1712860006
Short name T774
Test name
Test status
Simulation time 597703417286 ps
CPU time 331.84 seconds
Started Aug 02 05:22:51 PM PDT 24
Finished Aug 02 05:28:23 PM PDT 24
Peak memory 201452 kb
Host smart-65d135e4-efe3-4fd0-a735-1cdcda4c3705
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712860006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1712860006
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3774234687
Short name T522
Test name
Test status
Simulation time 80289197530 ps
CPU time 456.57 seconds
Started Aug 02 05:22:50 PM PDT 24
Finished Aug 02 05:30:27 PM PDT 24
Peak memory 201936 kb
Host smart-9cc9b7c7-5aa5-4b1a-839f-922034fc11e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774234687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3774234687
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.822735890
Short name T776
Test name
Test status
Simulation time 33965542327 ps
CPU time 17.59 seconds
Started Aug 02 05:22:39 PM PDT 24
Finished Aug 02 05:22:57 PM PDT 24
Peak memory 201360 kb
Host smart-94a0f6ce-d36f-4443-a740-e4362b2d3ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822735890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.822735890
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2837117236
Short name T375
Test name
Test status
Simulation time 4907014519 ps
CPU time 3.28 seconds
Started Aug 02 05:22:38 PM PDT 24
Finished Aug 02 05:22:41 PM PDT 24
Peak memory 201420 kb
Host smart-dfe8a051-f86d-42d0-97b3-ca0790d79bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837117236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2837117236
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3111952518
Short name T64
Test name
Test status
Simulation time 8000130421 ps
CPU time 9.29 seconds
Started Aug 02 05:22:46 PM PDT 24
Finished Aug 02 05:22:55 PM PDT 24
Peak memory 218192 kb
Host smart-d1dffe2c-b18b-4c91-84e8-65e9b6ac5f4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111952518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3111952518
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.254623955
Short name T627
Test name
Test status
Simulation time 5916153868 ps
CPU time 4.81 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:22:42 PM PDT 24
Peak memory 201364 kb
Host smart-516f8604-cd8c-4f8b-a4c5-c32213d2af55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254623955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.254623955
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2268006993
Short name T121
Test name
Test status
Simulation time 185662543062 ps
CPU time 164.25 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:25:29 PM PDT 24
Peak memory 210196 kb
Host smart-675f69b9-01a3-408a-907c-9d6c4122b19b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268006993 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2268006993
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1838696099
Short name T586
Test name
Test status
Simulation time 336245979 ps
CPU time 1.39 seconds
Started Aug 02 05:24:45 PM PDT 24
Finished Aug 02 05:24:46 PM PDT 24
Peak memory 201260 kb
Host smart-a6b5acda-8cba-439c-877f-1dbb1960f915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838696099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1838696099
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.84706941
Short name T295
Test name
Test status
Simulation time 165490221020 ps
CPU time 82.29 seconds
Started Aug 02 05:24:45 PM PDT 24
Finished Aug 02 05:26:08 PM PDT 24
Peak memory 201556 kb
Host smart-db8facef-2996-4459-84aa-c25685224062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84706941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.84706941
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1822958571
Short name T489
Test name
Test status
Simulation time 492135937310 ps
CPU time 496.62 seconds
Started Aug 02 05:24:39 PM PDT 24
Finished Aug 02 05:32:56 PM PDT 24
Peak memory 201432 kb
Host smart-824d93de-5838-463f-bd4e-d4a381059d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822958571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1822958571
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1901246609
Short name T167
Test name
Test status
Simulation time 162003380974 ps
CPU time 71.27 seconds
Started Aug 02 05:24:43 PM PDT 24
Finished Aug 02 05:25:55 PM PDT 24
Peak memory 201260 kb
Host smart-f68cbe4b-9b99-4bb1-ad8d-d31ba113a55d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901246609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1901246609
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.304495303
Short name T488
Test name
Test status
Simulation time 329439549760 ps
CPU time 44.36 seconds
Started Aug 02 05:24:38 PM PDT 24
Finished Aug 02 05:25:22 PM PDT 24
Peak memory 201540 kb
Host smart-53f2cfbf-5318-44bd-af6d-c9f17bb950d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304495303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.304495303
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.4255581192
Short name T384
Test name
Test status
Simulation time 164325852944 ps
CPU time 358.18 seconds
Started Aug 02 05:24:39 PM PDT 24
Finished Aug 02 05:30:38 PM PDT 24
Peak memory 201464 kb
Host smart-62061956-0f38-4324-8dee-b16009cc7052
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255581192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.4255581192
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2863224383
Short name T610
Test name
Test status
Simulation time 631637349640 ps
CPU time 354.31 seconds
Started Aug 02 05:24:45 PM PDT 24
Finished Aug 02 05:30:40 PM PDT 24
Peak memory 201540 kb
Host smart-b4064a76-b745-4806-ab69-b54a7bc5e168
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863224383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2863224383
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2662821007
Short name T581
Test name
Test status
Simulation time 85037888516 ps
CPU time 405.42 seconds
Started Aug 02 05:24:48 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 201844 kb
Host smart-a94e0d41-bfa7-4e62-b5bf-a3b5666b24df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662821007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2662821007
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2510100718
Short name T444
Test name
Test status
Simulation time 43129547071 ps
CPU time 9.37 seconds
Started Aug 02 05:24:45 PM PDT 24
Finished Aug 02 05:24:55 PM PDT 24
Peak memory 201348 kb
Host smart-63f5e492-0b33-4ff5-862b-293dd4573dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510100718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2510100718
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1785835220
Short name T448
Test name
Test status
Simulation time 5248685490 ps
CPU time 6.68 seconds
Started Aug 02 05:24:46 PM PDT 24
Finished Aug 02 05:24:53 PM PDT 24
Peak memory 200748 kb
Host smart-7714d3e3-89d5-4515-a362-1fc2b18bc8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785835220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1785835220
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2099180149
Short name T722
Test name
Test status
Simulation time 5937262399 ps
CPU time 13.41 seconds
Started Aug 02 05:24:38 PM PDT 24
Finished Aug 02 05:24:52 PM PDT 24
Peak memory 201404 kb
Host smart-ab8d0e88-4521-431f-9b65-3ec48d2879ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099180149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2099180149
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1115697559
Short name T289
Test name
Test status
Simulation time 223328764930 ps
CPU time 504.22 seconds
Started Aug 02 05:24:46 PM PDT 24
Finished Aug 02 05:33:10 PM PDT 24
Peak memory 200896 kb
Host smart-6488751a-96dc-4ae1-8401-be0d7739411e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115697559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1115697559
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2521371359
Short name T293
Test name
Test status
Simulation time 149692819110 ps
CPU time 259.7 seconds
Started Aug 02 05:24:45 PM PDT 24
Finished Aug 02 05:29:05 PM PDT 24
Peak memory 217508 kb
Host smart-4fd7c03e-67f7-49f7-bbc3-bac0fd493be4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521371359 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2521371359
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3687026553
Short name T632
Test name
Test status
Simulation time 455405658 ps
CPU time 1.59 seconds
Started Aug 02 05:24:55 PM PDT 24
Finished Aug 02 05:24:56 PM PDT 24
Peak memory 201172 kb
Host smart-84e7b2ad-6d22-45ba-bf82-55450c4db6b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687026553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3687026553
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2081202124
Short name T723
Test name
Test status
Simulation time 496760922559 ps
CPU time 355.21 seconds
Started Aug 02 05:24:55 PM PDT 24
Finished Aug 02 05:30:50 PM PDT 24
Peak memory 201448 kb
Host smart-0394ff4a-93fc-4896-80c4-6ca457ff0902
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081202124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2081202124
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1238379014
Short name T536
Test name
Test status
Simulation time 325851126314 ps
CPU time 820.83 seconds
Started Aug 02 05:24:55 PM PDT 24
Finished Aug 02 05:38:36 PM PDT 24
Peak memory 201424 kb
Host smart-70b49d2d-4d95-47b8-9525-e203ecd70137
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238379014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1238379014
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.132751255
Short name T698
Test name
Test status
Simulation time 323944332087 ps
CPU time 195.65 seconds
Started Aug 02 05:24:44 PM PDT 24
Finished Aug 02 05:27:59 PM PDT 24
Peak memory 201380 kb
Host smart-b0e3534d-22e9-4271-998d-af4e09287d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132751255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.132751255
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1032873566
Short name T423
Test name
Test status
Simulation time 162427854142 ps
CPU time 163.17 seconds
Started Aug 02 05:24:48 PM PDT 24
Finished Aug 02 05:27:32 PM PDT 24
Peak memory 201468 kb
Host smart-b5e135bf-1ac2-4b1a-88ca-5e94be9aceb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032873566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1032873566
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.4180058772
Short name T342
Test name
Test status
Simulation time 430180541579 ps
CPU time 311.39 seconds
Started Aug 02 05:24:52 PM PDT 24
Finished Aug 02 05:30:04 PM PDT 24
Peak memory 201480 kb
Host smart-94efbddc-fe60-4426-80d8-b54db710bf38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180058772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.4180058772
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.568434706
Short name T727
Test name
Test status
Simulation time 401335160049 ps
CPU time 445.74 seconds
Started Aug 02 05:24:55 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 201456 kb
Host smart-efc1cf2b-525f-4572-9112-8616f535083d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568434706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.568434706
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.7994150
Short name T28
Test name
Test status
Simulation time 128840423999 ps
CPU time 414.9 seconds
Started Aug 02 05:24:54 PM PDT 24
Finished Aug 02 05:31:49 PM PDT 24
Peak memory 201960 kb
Host smart-733e8f27-fc3f-44c4-97df-3e5f5626b5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7994150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.7994150
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.333429980
Short name T435
Test name
Test status
Simulation time 32160853756 ps
CPU time 15.97 seconds
Started Aug 02 05:24:53 PM PDT 24
Finished Aug 02 05:25:09 PM PDT 24
Peak memory 201420 kb
Host smart-674cad85-dde3-4a9b-9589-87aa36c568a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333429980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.333429980
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1874412659
Short name T654
Test name
Test status
Simulation time 4616522581 ps
CPU time 2.99 seconds
Started Aug 02 05:24:53 PM PDT 24
Finished Aug 02 05:24:57 PM PDT 24
Peak memory 201328 kb
Host smart-099a35f1-7a6a-4172-8042-dca8d96cdd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874412659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1874412659
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2568203515
Short name T592
Test name
Test status
Simulation time 6010973524 ps
CPU time 14.51 seconds
Started Aug 02 05:24:46 PM PDT 24
Finished Aug 02 05:25:01 PM PDT 24
Peak memory 201388 kb
Host smart-8a155eec-24bf-43fa-b553-b4d89fa37a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568203515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2568203515
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2085951636
Short name T235
Test name
Test status
Simulation time 466374855682 ps
CPU time 801.79 seconds
Started Aug 02 05:24:55 PM PDT 24
Finished Aug 02 05:38:17 PM PDT 24
Peak memory 209988 kb
Host smart-aa6f6bf0-3f06-4525-bdeb-8675e2366430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085951636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2085951636
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.404767640
Short name T161
Test name
Test status
Simulation time 60983797919 ps
CPU time 130.52 seconds
Started Aug 02 05:24:53 PM PDT 24
Finished Aug 02 05:27:04 PM PDT 24
Peak memory 209808 kb
Host smart-dd0b9bca-0ebe-449e-b74c-19afde892516
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404767640 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.404767640
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3528344596
Short name T14
Test name
Test status
Simulation time 304997118 ps
CPU time 1.24 seconds
Started Aug 02 05:25:02 PM PDT 24
Finished Aug 02 05:25:03 PM PDT 24
Peak memory 201260 kb
Host smart-88d87256-6b57-47f6-86b9-ae0b5df52253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528344596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3528344596
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.796456338
Short name T332
Test name
Test status
Simulation time 366127288472 ps
CPU time 789.53 seconds
Started Aug 02 05:25:03 PM PDT 24
Finished Aug 02 05:38:13 PM PDT 24
Peak memory 201504 kb
Host smart-2e10079c-1e5b-4cea-80c4-d04df5ff824c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796456338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.796456338
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2998851681
Short name T736
Test name
Test status
Simulation time 192013014467 ps
CPU time 458.29 seconds
Started Aug 02 05:25:01 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 201496 kb
Host smart-23331c14-0e79-4399-9ebc-ab56e6fa0696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998851681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2998851681
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.604432472
Short name T594
Test name
Test status
Simulation time 489453941464 ps
CPU time 1047.59 seconds
Started Aug 02 05:24:55 PM PDT 24
Finished Aug 02 05:42:23 PM PDT 24
Peak memory 201476 kb
Host smart-8c187446-9c39-4022-aad5-195c3a48459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604432472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.604432472
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.662621505
Short name T619
Test name
Test status
Simulation time 163916087016 ps
CPU time 113.23 seconds
Started Aug 02 05:24:55 PM PDT 24
Finished Aug 02 05:26:49 PM PDT 24
Peak memory 201456 kb
Host smart-377c0217-240d-4b94-b792-955537203350
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=662621505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.662621505
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.428198655
Short name T13
Test name
Test status
Simulation time 169536559221 ps
CPU time 374.52 seconds
Started Aug 02 05:24:54 PM PDT 24
Finished Aug 02 05:31:09 PM PDT 24
Peak memory 201468 kb
Host smart-7835da6f-d21d-423b-ad32-7d3d5cfea323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428198655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.428198655
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3995813313
Short name T447
Test name
Test status
Simulation time 489915062267 ps
CPU time 588.32 seconds
Started Aug 02 05:24:53 PM PDT 24
Finished Aug 02 05:34:42 PM PDT 24
Peak memory 201440 kb
Host smart-956752bc-630f-4916-9ba7-562a35b275bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995813313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3995813313
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2340841081
Short name T301
Test name
Test status
Simulation time 180318771479 ps
CPU time 398.73 seconds
Started Aug 02 05:24:53 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 201540 kb
Host smart-5f1633ae-9fed-4efe-93e3-702c7f98ea56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340841081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2340841081
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2572623051
Short name T491
Test name
Test status
Simulation time 202475627876 ps
CPU time 429.89 seconds
Started Aug 02 05:24:54 PM PDT 24
Finished Aug 02 05:32:04 PM PDT 24
Peak memory 201488 kb
Host smart-1e5fc977-2f85-4659-ba47-cdb70ded9004
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572623051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2572623051
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3248372553
Short name T49
Test name
Test status
Simulation time 137043286168 ps
CPU time 672.56 seconds
Started Aug 02 05:25:03 PM PDT 24
Finished Aug 02 05:36:15 PM PDT 24
Peak memory 201900 kb
Host smart-241f7267-2849-49a1-97ad-9cc9068e14aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248372553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3248372553
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1726780852
Short name T715
Test name
Test status
Simulation time 28256391584 ps
CPU time 61.45 seconds
Started Aug 02 05:25:01 PM PDT 24
Finished Aug 02 05:26:03 PM PDT 24
Peak memory 201396 kb
Host smart-0e390e15-2e59-4282-89b7-5f4a939c4efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726780852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1726780852
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3564909615
Short name T33
Test name
Test status
Simulation time 3051204053 ps
CPU time 3.21 seconds
Started Aug 02 05:25:03 PM PDT 24
Finished Aug 02 05:25:06 PM PDT 24
Peak memory 201364 kb
Host smart-6e7b7034-cd31-4f6f-86fe-4c51a17eb2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564909615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3564909615
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.778354265
Short name T599
Test name
Test status
Simulation time 5914876191 ps
CPU time 3.05 seconds
Started Aug 02 05:24:53 PM PDT 24
Finished Aug 02 05:24:56 PM PDT 24
Peak memory 201392 kb
Host smart-d53f8674-de08-4042-9bcc-d61099550ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778354265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.778354265
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2682869671
Short name T272
Test name
Test status
Simulation time 368816266558 ps
CPU time 852.07 seconds
Started Aug 02 05:25:00 PM PDT 24
Finished Aug 02 05:39:12 PM PDT 24
Peak memory 201484 kb
Host smart-54dbeee9-f4b6-41eb-bc2f-d69528ee792c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682869671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2682869671
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.4133274027
Short name T797
Test name
Test status
Simulation time 24662461029 ps
CPU time 35.03 seconds
Started Aug 02 05:25:03 PM PDT 24
Finished Aug 02 05:25:38 PM PDT 24
Peak memory 210240 kb
Host smart-b95831d5-5ca1-44af-82a8-5a8f1b0963ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133274027 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.4133274027
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3158471877
Short name T503
Test name
Test status
Simulation time 398080689 ps
CPU time 0.87 seconds
Started Aug 02 05:25:13 PM PDT 24
Finished Aug 02 05:25:14 PM PDT 24
Peak memory 201268 kb
Host smart-e2a47dc7-93bd-4e67-b7b4-f130ae004758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158471877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3158471877
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1369295691
Short name T346
Test name
Test status
Simulation time 489530181482 ps
CPU time 276.52 seconds
Started Aug 02 05:25:03 PM PDT 24
Finished Aug 02 05:29:40 PM PDT 24
Peak memory 201444 kb
Host smart-c073b971-b867-4c0d-b8d4-8e8eee4969e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369295691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1369295691
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1226992926
Short name T613
Test name
Test status
Simulation time 503104147297 ps
CPU time 281.09 seconds
Started Aug 02 05:25:01 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 201488 kb
Host smart-12cdc2be-863a-43d9-ac99-d1f0030d7dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226992926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1226992926
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.372550753
Short name T443
Test name
Test status
Simulation time 492994786999 ps
CPU time 1182.27 seconds
Started Aug 02 05:25:00 PM PDT 24
Finished Aug 02 05:44:43 PM PDT 24
Peak memory 201484 kb
Host smart-52b9d4a4-46f3-40d2-bbb1-9d956e4c9d3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=372550753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.372550753
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3260811653
Short name T670
Test name
Test status
Simulation time 171702349395 ps
CPU time 328.89 seconds
Started Aug 02 05:25:00 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 201500 kb
Host smart-a5421f61-df9f-4657-957f-694d79eaf48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260811653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3260811653
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.311436301
Short name T496
Test name
Test status
Simulation time 331412645220 ps
CPU time 203.02 seconds
Started Aug 02 05:25:01 PM PDT 24
Finished Aug 02 05:28:24 PM PDT 24
Peak memory 201500 kb
Host smart-d05d6d16-d152-47e2-9630-1cf5095aec24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=311436301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.311436301
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2140173354
Short name T275
Test name
Test status
Simulation time 184767589323 ps
CPU time 398.38 seconds
Started Aug 02 05:25:04 PM PDT 24
Finished Aug 02 05:31:43 PM PDT 24
Peak memory 201452 kb
Host smart-2cbaa2a0-96a6-4383-9e11-a6251844c03a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140173354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2140173354
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.14579002
Short name T498
Test name
Test status
Simulation time 188657872090 ps
CPU time 418.27 seconds
Started Aug 02 05:25:02 PM PDT 24
Finished Aug 02 05:32:00 PM PDT 24
Peak memory 201448 kb
Host smart-7775081e-526c-4b85-a469-52c87a8a3892
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14579002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
dc_ctrl_filters_wakeup_fixed.14579002
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1896577376
Short name T380
Test name
Test status
Simulation time 35348953751 ps
CPU time 75.7 seconds
Started Aug 02 05:25:04 PM PDT 24
Finished Aug 02 05:26:19 PM PDT 24
Peak memory 201340 kb
Host smart-519b1f89-eb15-4e36-b3c1-6f51d34b8ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896577376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1896577376
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2207042239
Short name T430
Test name
Test status
Simulation time 3374051754 ps
CPU time 4.29 seconds
Started Aug 02 05:25:02 PM PDT 24
Finished Aug 02 05:25:07 PM PDT 24
Peak memory 201356 kb
Host smart-cea2fe4f-d600-4523-b077-d19821d2da25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207042239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2207042239
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1334073896
Short name T123
Test name
Test status
Simulation time 5567323467 ps
CPU time 13.34 seconds
Started Aug 02 05:25:02 PM PDT 24
Finished Aug 02 05:25:15 PM PDT 24
Peak memory 201420 kb
Host smart-f23b8f3a-7256-4f44-b13b-3545b61f65fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334073896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1334073896
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1171876080
Short name T539
Test name
Test status
Simulation time 319784009951 ps
CPU time 784.41 seconds
Started Aug 02 05:25:03 PM PDT 24
Finished Aug 02 05:38:07 PM PDT 24
Peak memory 212660 kb
Host smart-0254950b-fef4-44d5-9dc3-bc6bb55c6e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171876080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1171876080
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.500653816
Short name T640
Test name
Test status
Simulation time 54324425961 ps
CPU time 67.35 seconds
Started Aug 02 05:25:04 PM PDT 24
Finished Aug 02 05:26:11 PM PDT 24
Peak memory 210140 kb
Host smart-67f6aebc-1573-4bb0-ad66-f6ce234252e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500653816 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.500653816
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.464538522
Short name T650
Test name
Test status
Simulation time 420032560 ps
CPU time 1.57 seconds
Started Aug 02 05:25:19 PM PDT 24
Finished Aug 02 05:25:21 PM PDT 24
Peak memory 201296 kb
Host smart-2da52128-2a54-487a-8577-f7409a01248b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464538522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.464538522
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1982017251
Short name T277
Test name
Test status
Simulation time 488279143037 ps
CPU time 397.03 seconds
Started Aug 02 05:25:13 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 201468 kb
Host smart-13cdf094-8c16-45d2-8753-2d31d93446dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982017251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1982017251
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.765162480
Short name T248
Test name
Test status
Simulation time 557585184755 ps
CPU time 334.54 seconds
Started Aug 02 05:25:09 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 201508 kb
Host smart-1bd6bcb8-0300-4bd1-a7f7-89dc01d793db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765162480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.765162480
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.477795393
Short name T656
Test name
Test status
Simulation time 166565787876 ps
CPU time 412.3 seconds
Started Aug 02 05:25:11 PM PDT 24
Finished Aug 02 05:32:03 PM PDT 24
Peak memory 201472 kb
Host smart-855d1365-e652-4cac-97cb-1aaae0ffa1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477795393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.477795393
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2377877739
Short name T784
Test name
Test status
Simulation time 162915484392 ps
CPU time 102.05 seconds
Started Aug 02 05:25:12 PM PDT 24
Finished Aug 02 05:26:54 PM PDT 24
Peak memory 201492 kb
Host smart-0cfa8686-436b-43af-a2a2-daeb748135a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377877739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2377877739
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.4050776033
Short name T777
Test name
Test status
Simulation time 496995651403 ps
CPU time 272.71 seconds
Started Aug 02 05:25:12 PM PDT 24
Finished Aug 02 05:29:45 PM PDT 24
Peak memory 201480 kb
Host smart-c77ba2b4-572a-4a74-af40-4c52e43783c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050776033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.4050776033
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3615709777
Short name T704
Test name
Test status
Simulation time 172655870203 ps
CPU time 191.69 seconds
Started Aug 02 05:25:11 PM PDT 24
Finished Aug 02 05:28:23 PM PDT 24
Peak memory 201464 kb
Host smart-71f049f1-0f52-4063-b99f-27b9ab55a93d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615709777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3615709777
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1315161359
Short name T608
Test name
Test status
Simulation time 361627031672 ps
CPU time 753.57 seconds
Started Aug 02 05:25:12 PM PDT 24
Finished Aug 02 05:37:46 PM PDT 24
Peak memory 201476 kb
Host smart-246e12e1-e806-4ba9-a375-cd25e99e4146
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315161359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1315161359
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3549768042
Short name T607
Test name
Test status
Simulation time 402820553638 ps
CPU time 171.95 seconds
Started Aug 02 05:25:12 PM PDT 24
Finished Aug 02 05:28:04 PM PDT 24
Peak memory 201472 kb
Host smart-04862d1e-39b0-4dbe-86c8-8a36cdd972de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549768042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3549768042
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3184163281
Short name T240
Test name
Test status
Simulation time 85738525697 ps
CPU time 447.7 seconds
Started Aug 02 05:25:11 PM PDT 24
Finished Aug 02 05:32:38 PM PDT 24
Peak memory 201876 kb
Host smart-ea8e6774-6c98-4446-a877-577c256a0f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184163281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3184163281
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.239622472
Short name T618
Test name
Test status
Simulation time 22716414394 ps
CPU time 51.61 seconds
Started Aug 02 05:25:12 PM PDT 24
Finished Aug 02 05:26:03 PM PDT 24
Peak memory 201304 kb
Host smart-290eef39-b63e-4cac-bea0-266428f7f7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239622472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.239622472
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3563549302
Short name T780
Test name
Test status
Simulation time 4012922250 ps
CPU time 2.95 seconds
Started Aug 02 05:25:11 PM PDT 24
Finished Aug 02 05:25:14 PM PDT 24
Peak memory 201376 kb
Host smart-6b214df8-d671-4226-a837-c818963cd3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563549302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3563549302
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3799501015
Short name T520
Test name
Test status
Simulation time 5996476235 ps
CPU time 3.46 seconds
Started Aug 02 05:25:09 PM PDT 24
Finished Aug 02 05:25:13 PM PDT 24
Peak memory 201368 kb
Host smart-d0ead4a4-6c8b-47ff-b9b4-b86a054c3962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799501015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3799501015
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.973577415
Short name T179
Test name
Test status
Simulation time 233063289885 ps
CPU time 189.32 seconds
Started Aug 02 05:25:13 PM PDT 24
Finished Aug 02 05:28:23 PM PDT 24
Peak memory 201520 kb
Host smart-71b16591-9770-428d-8af9-e840f77c54c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973577415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
973577415
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1714142803
Short name T225
Test name
Test status
Simulation time 159443333908 ps
CPU time 269.74 seconds
Started Aug 02 05:25:11 PM PDT 24
Finished Aug 02 05:29:41 PM PDT 24
Peak memory 212332 kb
Host smart-81e01a37-bc45-462f-91d3-b5134e57febb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714142803 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1714142803
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.579422410
Short name T634
Test name
Test status
Simulation time 517334447 ps
CPU time 1.18 seconds
Started Aug 02 05:25:25 PM PDT 24
Finished Aug 02 05:25:26 PM PDT 24
Peak memory 201232 kb
Host smart-16e9fabe-a983-4246-b3f8-8ad35bc6c6a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579422410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.579422410
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3211063930
Short name T290
Test name
Test status
Simulation time 161853203188 ps
CPU time 369.49 seconds
Started Aug 02 05:25:19 PM PDT 24
Finished Aug 02 05:31:29 PM PDT 24
Peak memory 201552 kb
Host smart-54fceff2-b973-463a-a5fc-5bf775b9abe1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211063930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3211063930
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4014678438
Short name T693
Test name
Test status
Simulation time 384567727215 ps
CPU time 877.85 seconds
Started Aug 02 05:25:17 PM PDT 24
Finished Aug 02 05:39:56 PM PDT 24
Peak memory 201444 kb
Host smart-2594a8ca-34c8-4a99-bcfd-006fb6d4c899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014678438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4014678438
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3542064660
Short name T89
Test name
Test status
Simulation time 496672401533 ps
CPU time 310.95 seconds
Started Aug 02 05:25:16 PM PDT 24
Finished Aug 02 05:30:27 PM PDT 24
Peak memory 201468 kb
Host smart-4cf336f1-fc64-4a49-9b66-6bfcf8fa3b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542064660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3542064660
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3062278200
Short name T44
Test name
Test status
Simulation time 327926579141 ps
CPU time 413.96 seconds
Started Aug 02 05:25:17 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 201468 kb
Host smart-a2aee557-604c-43fd-9f8f-79f253f4d595
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062278200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3062278200
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3878506331
Short name T150
Test name
Test status
Simulation time 169373892067 ps
CPU time 220.58 seconds
Started Aug 02 05:25:17 PM PDT 24
Finished Aug 02 05:28:58 PM PDT 24
Peak memory 201484 kb
Host smart-dbf9c6bd-bf26-4f94-8d65-1e1ebdec1fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878506331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3878506331
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2988183752
Short name T728
Test name
Test status
Simulation time 176955850054 ps
CPU time 209.96 seconds
Started Aug 02 05:25:17 PM PDT 24
Finished Aug 02 05:28:47 PM PDT 24
Peak memory 201488 kb
Host smart-be727506-9782-4862-aa99-06eeb026949f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988183752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2988183752
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4294796893
Short name T765
Test name
Test status
Simulation time 395357941338 ps
CPU time 212.91 seconds
Started Aug 02 05:25:16 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 201432 kb
Host smart-d6fbbc34-3d7e-402d-9051-fa0efc015bab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294796893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4294796893
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3448938436
Short name T767
Test name
Test status
Simulation time 122694056817 ps
CPU time 658.12 seconds
Started Aug 02 05:25:17 PM PDT 24
Finished Aug 02 05:36:15 PM PDT 24
Peak memory 201848 kb
Host smart-5b27be1c-a4f8-42fe-a9b4-ae9f31d1eeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448938436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3448938436
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2376928281
Short name T633
Test name
Test status
Simulation time 47340526880 ps
CPU time 10.73 seconds
Started Aug 02 05:25:18 PM PDT 24
Finished Aug 02 05:25:29 PM PDT 24
Peak memory 201388 kb
Host smart-a4a2dd3f-212b-4e52-a119-fc4219562b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376928281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2376928281
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1594813491
Short name T407
Test name
Test status
Simulation time 3463656971 ps
CPU time 1.44 seconds
Started Aug 02 05:25:19 PM PDT 24
Finished Aug 02 05:25:20 PM PDT 24
Peak memory 201412 kb
Host smart-eda4586e-1cb1-4f83-8a87-918d2202f8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594813491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1594813491
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1708889920
Short name T464
Test name
Test status
Simulation time 5914115549 ps
CPU time 14.18 seconds
Started Aug 02 05:25:17 PM PDT 24
Finished Aug 02 05:25:31 PM PDT 24
Peak memory 201420 kb
Host smart-71c6e24d-4597-40e4-8e6b-eef561050c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708889920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1708889920
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.4216482407
Short name T497
Test name
Test status
Simulation time 205867581375 ps
CPU time 143.53 seconds
Started Aug 02 05:25:17 PM PDT 24
Finished Aug 02 05:27:40 PM PDT 24
Peak memory 201512 kb
Host smart-883cfdd9-25a0-4dba-a760-19ad6bc5d051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216482407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.4216482407
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.257256227
Short name T59
Test name
Test status
Simulation time 18414835565 ps
CPU time 32.72 seconds
Started Aug 02 05:25:21 PM PDT 24
Finished Aug 02 05:25:54 PM PDT 24
Peak memory 209828 kb
Host smart-9a857c88-4153-43a1-bc83-ab81dc03e000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257256227 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.257256227
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1785900853
Short name T684
Test name
Test status
Simulation time 292640765 ps
CPU time 0.96 seconds
Started Aug 02 05:25:30 PM PDT 24
Finished Aug 02 05:25:31 PM PDT 24
Peak memory 201236 kb
Host smart-e7f61f21-0154-4c7a-8487-5e97d5ff7db4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785900853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1785900853
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.70608508
Short name T732
Test name
Test status
Simulation time 168415955882 ps
CPU time 143.9 seconds
Started Aug 02 05:25:24 PM PDT 24
Finished Aug 02 05:27:48 PM PDT 24
Peak memory 201412 kb
Host smart-88ed40b1-9301-4817-9142-c69818f7af42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70608508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gatin
g.70608508
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1674080577
Short name T678
Test name
Test status
Simulation time 523613981556 ps
CPU time 641.28 seconds
Started Aug 02 05:25:25 PM PDT 24
Finished Aug 02 05:36:07 PM PDT 24
Peak memory 201440 kb
Host smart-2b0fdc86-6f0f-46f8-b99f-b68987a48617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674080577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1674080577
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4107691385
Short name T198
Test name
Test status
Simulation time 330521253919 ps
CPU time 184.64 seconds
Started Aug 02 05:25:24 PM PDT 24
Finished Aug 02 05:28:29 PM PDT 24
Peak memory 201472 kb
Host smart-ec6cfcc7-0551-4f16-87c3-43f3ff9ff053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107691385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4107691385
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1028753762
Short name T564
Test name
Test status
Simulation time 334712601287 ps
CPU time 199.78 seconds
Started Aug 02 05:25:26 PM PDT 24
Finished Aug 02 05:28:46 PM PDT 24
Peak memory 201472 kb
Host smart-4486532e-b657-4204-b143-9f8abedbd3d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028753762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1028753762
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1017669513
Short name T628
Test name
Test status
Simulation time 495684125546 ps
CPU time 1180.57 seconds
Started Aug 02 05:25:26 PM PDT 24
Finished Aug 02 05:45:07 PM PDT 24
Peak memory 201476 kb
Host smart-b709dec8-846e-448d-9731-d0c1e46e126a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017669513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1017669513
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2086957532
Short name T431
Test name
Test status
Simulation time 325812740904 ps
CPU time 174.21 seconds
Started Aug 02 05:25:26 PM PDT 24
Finished Aug 02 05:28:21 PM PDT 24
Peak memory 201440 kb
Host smart-55c52af5-5af9-43d3-85ba-0e2ed51c37b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086957532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2086957532
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3629861119
Short name T339
Test name
Test status
Simulation time 613107040556 ps
CPU time 888.67 seconds
Started Aug 02 05:25:25 PM PDT 24
Finished Aug 02 05:40:14 PM PDT 24
Peak memory 201540 kb
Host smart-59720112-76e1-4ee4-8477-301afda66280
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629861119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3629861119
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1701933649
Short name T787
Test name
Test status
Simulation time 400121339185 ps
CPU time 226.69 seconds
Started Aug 02 05:25:23 PM PDT 24
Finished Aug 02 05:29:10 PM PDT 24
Peak memory 201604 kb
Host smart-59f85c27-ee19-4b7f-82a8-8cc167b5cfec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701933649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1701933649
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4154919014
Short name T549
Test name
Test status
Simulation time 110213483909 ps
CPU time 570.39 seconds
Started Aug 02 05:25:26 PM PDT 24
Finished Aug 02 05:34:56 PM PDT 24
Peak memory 201852 kb
Host smart-dcdbdcec-86d1-404e-bba0-0eefc12cc170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154919014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4154919014
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3121002847
Short name T477
Test name
Test status
Simulation time 30194504036 ps
CPU time 16.44 seconds
Started Aug 02 05:25:25 PM PDT 24
Finished Aug 02 05:25:41 PM PDT 24
Peak memory 201280 kb
Host smart-80bd4fb7-1b72-4d40-9be6-942258adcb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121002847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3121002847
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.4022369905
Short name T7
Test name
Test status
Simulation time 4284695401 ps
CPU time 1.49 seconds
Started Aug 02 05:25:26 PM PDT 24
Finished Aug 02 05:25:27 PM PDT 24
Peak memory 201372 kb
Host smart-57829129-601c-4b1a-a29b-3457f2bc126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022369905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4022369905
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.492093082
Short name T202
Test name
Test status
Simulation time 5884913575 ps
CPU time 1.75 seconds
Started Aug 02 05:25:27 PM PDT 24
Finished Aug 02 05:25:28 PM PDT 24
Peak memory 201392 kb
Host smart-eca08a0e-0b65-44a7-8266-56ed66096007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492093082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.492093082
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.817295242
Short name T566
Test name
Test status
Simulation time 242940907543 ps
CPU time 102.94 seconds
Started Aug 02 05:25:26 PM PDT 24
Finished Aug 02 05:27:09 PM PDT 24
Peak memory 201464 kb
Host smart-29cd1536-eaff-4152-a45b-c417a6f2b75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817295242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
817295242
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.212525157
Short name T45
Test name
Test status
Simulation time 25764733793 ps
CPU time 62.5 seconds
Started Aug 02 05:25:25 PM PDT 24
Finished Aug 02 05:26:28 PM PDT 24
Peak memory 209768 kb
Host smart-2e566396-cb9d-420b-bb64-d470d38499bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212525157 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.212525157
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3694432553
Short name T675
Test name
Test status
Simulation time 587217325 ps
CPU time 0.72 seconds
Started Aug 02 05:25:35 PM PDT 24
Finished Aug 02 05:25:36 PM PDT 24
Peak memory 201232 kb
Host smart-ba17bb92-b727-4041-8c2f-59ad1ca04704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694432553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3694432553
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3978744497
Short name T343
Test name
Test status
Simulation time 483699425348 ps
CPU time 272.75 seconds
Started Aug 02 05:25:36 PM PDT 24
Finished Aug 02 05:30:09 PM PDT 24
Peak memory 201500 kb
Host smart-feb1482b-4b12-44b5-b49c-fc9e49bf9de8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978744497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3978744497
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.592589144
Short name T195
Test name
Test status
Simulation time 366478565688 ps
CPU time 215.85 seconds
Started Aug 02 05:25:32 PM PDT 24
Finished Aug 02 05:29:09 PM PDT 24
Peak memory 201468 kb
Host smart-804b4be5-eb4c-4303-86c2-b090cd9d6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592589144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.592589144
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.262339215
Short name T643
Test name
Test status
Simulation time 324350482207 ps
CPU time 49.06 seconds
Started Aug 02 05:25:39 PM PDT 24
Finished Aug 02 05:26:28 PM PDT 24
Peak memory 201492 kb
Host smart-e4757fd8-cda8-44b0-b854-d2887a759812
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=262339215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.262339215
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3969991927
Short name T207
Test name
Test status
Simulation time 170933996391 ps
CPU time 396.74 seconds
Started Aug 02 05:25:34 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 201472 kb
Host smart-950b115e-0917-4857-8604-d47119e5e9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969991927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3969991927
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3261767068
Short name T417
Test name
Test status
Simulation time 323820557659 ps
CPU time 367.01 seconds
Started Aug 02 05:25:34 PM PDT 24
Finished Aug 02 05:31:41 PM PDT 24
Peak memory 201468 kb
Host smart-2f31f24e-d954-4468-878b-03f1e8d7d2b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261767068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3261767068
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2307536902
Short name T625
Test name
Test status
Simulation time 349474159099 ps
CPU time 273.33 seconds
Started Aug 02 05:25:35 PM PDT 24
Finished Aug 02 05:30:09 PM PDT 24
Peak memory 201460 kb
Host smart-eaccef8a-19b7-40d1-84bc-f2633647c4ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307536902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2307536902
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2000201444
Short name T399
Test name
Test status
Simulation time 614042020008 ps
CPU time 1303.01 seconds
Started Aug 02 05:25:38 PM PDT 24
Finished Aug 02 05:47:21 PM PDT 24
Peak memory 201540 kb
Host smart-c3d2e442-2016-4299-9fab-8b06c9a3f134
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000201444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2000201444
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2057845673
Short name T647
Test name
Test status
Simulation time 82484839599 ps
CPU time 326.04 seconds
Started Aug 02 05:25:31 PM PDT 24
Finished Aug 02 05:30:57 PM PDT 24
Peak memory 201864 kb
Host smart-56059943-4b48-4b1c-b760-1983b553f20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057845673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2057845673
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3933557407
Short name T395
Test name
Test status
Simulation time 43913366303 ps
CPU time 26.63 seconds
Started Aug 02 05:25:33 PM PDT 24
Finished Aug 02 05:26:00 PM PDT 24
Peak memory 201384 kb
Host smart-e5e41d12-0ffc-4d79-afb5-79cd5e68201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933557407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3933557407
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3553803827
Short name T408
Test name
Test status
Simulation time 4625487856 ps
CPU time 11.69 seconds
Started Aug 02 05:25:34 PM PDT 24
Finished Aug 02 05:25:46 PM PDT 24
Peak memory 201332 kb
Host smart-d96c3c1f-e5dd-46ed-9e06-56597df856dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553803827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3553803827
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.154130188
Short name T204
Test name
Test status
Simulation time 5966395771 ps
CPU time 7.5 seconds
Started Aug 02 05:25:25 PM PDT 24
Finished Aug 02 05:25:32 PM PDT 24
Peak memory 201388 kb
Host smart-675a2bf7-1b47-4a7e-bf2d-f6dbe21ef204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154130188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.154130188
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2882976153
Short name T337
Test name
Test status
Simulation time 325771929065 ps
CPU time 768.89 seconds
Started Aug 02 05:25:33 PM PDT 24
Finished Aug 02 05:38:22 PM PDT 24
Peak memory 201492 kb
Host smart-688278c8-baa6-4f1e-9a2b-ef894a51514c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882976153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2882976153
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4102605527
Short name T554
Test name
Test status
Simulation time 428575143 ps
CPU time 1.61 seconds
Started Aug 02 05:25:41 PM PDT 24
Finished Aug 02 05:25:43 PM PDT 24
Peak memory 201316 kb
Host smart-2a392d11-aac0-43fa-a5a6-3c2086ca430d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102605527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4102605527
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3844396337
Short name T758
Test name
Test status
Simulation time 677131579446 ps
CPU time 334.78 seconds
Started Aug 02 05:25:44 PM PDT 24
Finished Aug 02 05:31:19 PM PDT 24
Peak memory 201480 kb
Host smart-aa10ec9d-61a0-4e71-ab78-2d2dbcbcbde0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844396337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3844396337
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.562806118
Short name T479
Test name
Test status
Simulation time 162415242938 ps
CPU time 197.44 seconds
Started Aug 02 05:25:41 PM PDT 24
Finished Aug 02 05:28:59 PM PDT 24
Peak memory 201464 kb
Host smart-c88bf741-3668-468f-863f-42717bba93d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562806118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.562806118
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1019429143
Short name T490
Test name
Test status
Simulation time 163514633150 ps
CPU time 377.56 seconds
Started Aug 02 05:25:41 PM PDT 24
Finished Aug 02 05:31:59 PM PDT 24
Peak memory 201452 kb
Host smart-6f4f676a-af22-4ae7-89cd-ad287495b784
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019429143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1019429143
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.753120052
Short name T257
Test name
Test status
Simulation time 163702194652 ps
CPU time 382.75 seconds
Started Aug 02 05:25:33 PM PDT 24
Finished Aug 02 05:31:56 PM PDT 24
Peak memory 201476 kb
Host smart-09c89538-5ccb-4446-a90a-d4dfe1a0e484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753120052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.753120052
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2499827521
Short name T512
Test name
Test status
Simulation time 318783855132 ps
CPU time 113.79 seconds
Started Aug 02 05:25:41 PM PDT 24
Finished Aug 02 05:27:35 PM PDT 24
Peak memory 201440 kb
Host smart-b11169d3-bcc1-438a-9c74-be8a45e8063d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499827521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2499827521
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1842423832
Short name T199
Test name
Test status
Simulation time 545639604638 ps
CPU time 73.14 seconds
Started Aug 02 05:25:42 PM PDT 24
Finished Aug 02 05:26:55 PM PDT 24
Peak memory 201532 kb
Host smart-d206cd8c-c6a7-4348-adf6-fc5e58509ee4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842423832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1842423832
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.995022111
Short name T426
Test name
Test status
Simulation time 207406985051 ps
CPU time 147.12 seconds
Started Aug 02 05:25:44 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 201432 kb
Host smart-c4b0b826-f18b-4ca7-94c7-2f54b7ee056a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995022111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.995022111
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.199290047
Short name T361
Test name
Test status
Simulation time 67093861927 ps
CPU time 268.17 seconds
Started Aug 02 05:25:40 PM PDT 24
Finished Aug 02 05:30:08 PM PDT 24
Peak memory 201844 kb
Host smart-fa6e66a9-21b3-4677-a43e-fb0d9f296388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199290047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.199290047
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.696509930
Short name T434
Test name
Test status
Simulation time 30956014927 ps
CPU time 18.29 seconds
Started Aug 02 05:25:40 PM PDT 24
Finished Aug 02 05:25:59 PM PDT 24
Peak memory 201400 kb
Host smart-6b4c6de8-a43b-49aa-bf42-79cdd795e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696509930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.696509930
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1487821915
Short name T371
Test name
Test status
Simulation time 4628842124 ps
CPU time 1.41 seconds
Started Aug 02 05:25:42 PM PDT 24
Finished Aug 02 05:25:44 PM PDT 24
Peak memory 201328 kb
Host smart-1039cf99-bb61-45dd-8e14-cc1542e5754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487821915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1487821915
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3086898640
Short name T630
Test name
Test status
Simulation time 5842578134 ps
CPU time 13.95 seconds
Started Aug 02 05:25:36 PM PDT 24
Finished Aug 02 05:25:50 PM PDT 24
Peak memory 201364 kb
Host smart-7fe33004-3e6c-4496-9379-e2f6085ea419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086898640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3086898640
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2299256389
Short name T735
Test name
Test status
Simulation time 421529602372 ps
CPU time 458.83 seconds
Started Aug 02 05:25:41 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 210020 kb
Host smart-f55b9356-56f7-4dcf-855a-d4f34a70a957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299256389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2299256389
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1369012052
Short name T422
Test name
Test status
Simulation time 381524177 ps
CPU time 1.42 seconds
Started Aug 02 05:25:47 PM PDT 24
Finished Aug 02 05:25:49 PM PDT 24
Peak memory 201284 kb
Host smart-fa82ad40-741a-4a29-aba1-4337bcfd6f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369012052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1369012052
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3322015325
Short name T164
Test name
Test status
Simulation time 331001405148 ps
CPU time 759.58 seconds
Started Aug 02 05:25:48 PM PDT 24
Finished Aug 02 05:38:28 PM PDT 24
Peak memory 201488 kb
Host smart-18e5dbdd-f87c-4c0e-a594-1c49c5ae3f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322015325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3322015325
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.528751301
Short name T165
Test name
Test status
Simulation time 163141260161 ps
CPU time 186.55 seconds
Started Aug 02 05:25:43 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 201488 kb
Host smart-fc96033e-fde4-45af-aaf1-ccc0e21ab946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528751301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.528751301
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3361448730
Short name T743
Test name
Test status
Simulation time 332551396722 ps
CPU time 763.53 seconds
Started Aug 02 05:25:50 PM PDT 24
Finished Aug 02 05:38:34 PM PDT 24
Peak memory 201456 kb
Host smart-18d397cc-1d7d-4d38-a9e5-cdd334b45bea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361448730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3361448730
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2350314442
Short name T636
Test name
Test status
Simulation time 162580994926 ps
CPU time 332.55 seconds
Started Aug 02 05:25:42 PM PDT 24
Finished Aug 02 05:31:14 PM PDT 24
Peak memory 201348 kb
Host smart-986a52b2-195c-4870-a141-a28ba9117ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350314442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2350314442
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1029602969
Short name T597
Test name
Test status
Simulation time 492434696356 ps
CPU time 1085.78 seconds
Started Aug 02 05:25:41 PM PDT 24
Finished Aug 02 05:43:47 PM PDT 24
Peak memory 201464 kb
Host smart-3ad9bc68-54c9-489f-8f34-c7baadbeaf70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029602969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1029602969
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.403582163
Short name T1
Test name
Test status
Simulation time 410416188050 ps
CPU time 131.98 seconds
Started Aug 02 05:25:47 PM PDT 24
Finished Aug 02 05:27:59 PM PDT 24
Peak memory 201504 kb
Host smart-e442fea8-5ac0-4707-8d86-86f660c346ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403582163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.403582163
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1868761529
Short name T729
Test name
Test status
Simulation time 105201618377 ps
CPU time 606.18 seconds
Started Aug 02 05:25:49 PM PDT 24
Finished Aug 02 05:35:55 PM PDT 24
Peak memory 201872 kb
Host smart-77688a74-97c6-4dcb-8588-89f4a0d35c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868761529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1868761529
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.725420952
Short name T540
Test name
Test status
Simulation time 26041339194 ps
CPU time 16.21 seconds
Started Aug 02 05:25:51 PM PDT 24
Finished Aug 02 05:26:08 PM PDT 24
Peak memory 201368 kb
Host smart-d894e769-f1e0-4f8d-86c6-0c02ede8bc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725420952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.725420952
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.409408441
Short name T389
Test name
Test status
Simulation time 4694445321 ps
CPU time 6.87 seconds
Started Aug 02 05:25:47 PM PDT 24
Finished Aug 02 05:25:54 PM PDT 24
Peak memory 201360 kb
Host smart-fe1a0f47-7baa-406a-9b4c-0252ffdad9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409408441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.409408441
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3001973037
Short name T584
Test name
Test status
Simulation time 5910745542 ps
CPU time 13.94 seconds
Started Aug 02 05:25:41 PM PDT 24
Finished Aug 02 05:25:55 PM PDT 24
Peak memory 201420 kb
Host smart-66cd629a-71ec-4d9c-a706-4bd42d811d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001973037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3001973037
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3832523161
Short name T38
Test name
Test status
Simulation time 35271724115 ps
CPU time 74.88 seconds
Started Aug 02 05:25:47 PM PDT 24
Finished Aug 02 05:27:02 PM PDT 24
Peak memory 201364 kb
Host smart-f202d503-9e08-4146-ac2c-dd1784c0631b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832523161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3832523161
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.494015748
Short name T759
Test name
Test status
Simulation time 385623992 ps
CPU time 0.86 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:22:45 PM PDT 24
Peak memory 201192 kb
Host smart-b26fdda6-e619-41e7-b729-7b1285777571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494015748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.494015748
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2793839288
Short name T307
Test name
Test status
Simulation time 475952758402 ps
CPU time 920.44 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:37:57 PM PDT 24
Peak memory 201512 kb
Host smart-cc3b79b4-463c-4872-a616-451f57a445bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793839288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2793839288
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.4214403914
Short name T245
Test name
Test status
Simulation time 163524304808 ps
CPU time 387.13 seconds
Started Aug 02 05:22:42 PM PDT 24
Finished Aug 02 05:29:09 PM PDT 24
Peak memory 201476 kb
Host smart-ba0b0c4c-a1c0-447c-835d-19409da2109d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214403914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.4214403914
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.89907732
Short name T368
Test name
Test status
Simulation time 323033561768 ps
CPU time 218.79 seconds
Started Aug 02 05:22:36 PM PDT 24
Finished Aug 02 05:26:15 PM PDT 24
Peak memory 201560 kb
Host smart-be8d31b1-6f67-477f-aee9-fde4f903d491
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=89907732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_
fixed.89907732
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2532211563
Short name T171
Test name
Test status
Simulation time 492498917621 ps
CPU time 1159.12 seconds
Started Aug 02 05:22:47 PM PDT 24
Finished Aug 02 05:42:06 PM PDT 24
Peak memory 201540 kb
Host smart-64febf5f-bc9c-4b1f-9510-51f8d27ae154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532211563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2532211563
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2479964916
Short name T763
Test name
Test status
Simulation time 484075515424 ps
CPU time 276.89 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:27:22 PM PDT 24
Peak memory 201396 kb
Host smart-4058de8f-4e99-4186-80ad-d2cfcee6d45d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479964916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2479964916
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1047749136
Short name T189
Test name
Test status
Simulation time 368781426759 ps
CPU time 190.91 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:25:48 PM PDT 24
Peak memory 201476 kb
Host smart-f576b6ab-90bc-443e-bf4c-cd02834715ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047749136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1047749136
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3653706272
Short name T415
Test name
Test status
Simulation time 202118184406 ps
CPU time 127.36 seconds
Started Aug 02 05:22:53 PM PDT 24
Finished Aug 02 05:25:00 PM PDT 24
Peak memory 201444 kb
Host smart-81717a8c-c8ad-48ea-a0fc-51d9f7deac2a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653706272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3653706272
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2280554174
Short name T425
Test name
Test status
Simulation time 89330875296 ps
CPU time 508.24 seconds
Started Aug 02 05:22:47 PM PDT 24
Finished Aug 02 05:31:16 PM PDT 24
Peak memory 201912 kb
Host smart-f3e7ce33-ab8c-4d2f-8f81-a5e86d7e9ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280554174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2280554174
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.4248756940
Short name T391
Test name
Test status
Simulation time 30556393381 ps
CPU time 12.31 seconds
Started Aug 02 05:22:36 PM PDT 24
Finished Aug 02 05:22:48 PM PDT 24
Peak memory 201384 kb
Host smart-41c93759-204c-4be8-9c83-4cb14cdd0b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248756940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.4248756940
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1890824901
Short name T445
Test name
Test status
Simulation time 4746774612 ps
CPU time 2.96 seconds
Started Aug 02 05:22:42 PM PDT 24
Finished Aug 02 05:22:45 PM PDT 24
Peak memory 201372 kb
Host smart-c4b49763-1dc5-499f-8a6d-f3df47b4be9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890824901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1890824901
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3112159640
Short name T473
Test name
Test status
Simulation time 5797323222 ps
CPU time 13.98 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:22:51 PM PDT 24
Peak memory 201360 kb
Host smart-09e5e601-426c-4b5a-bf08-3076b643a3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112159640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3112159640
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3602503097
Short name T291
Test name
Test status
Simulation time 361710322037 ps
CPU time 91.29 seconds
Started Aug 02 05:22:46 PM PDT 24
Finished Aug 02 05:24:17 PM PDT 24
Peak memory 201448 kb
Host smart-16118d1d-1392-4678-8170-6d294cc35ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602503097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3602503097
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3111667501
Short name T686
Test name
Test status
Simulation time 406881212 ps
CPU time 1.56 seconds
Started Aug 02 05:22:39 PM PDT 24
Finished Aug 02 05:22:40 PM PDT 24
Peak memory 201256 kb
Host smart-2efa92af-2697-4d12-8d84-f84f30421379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111667501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3111667501
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1835650507
Short name T565
Test name
Test status
Simulation time 170979585025 ps
CPU time 346.16 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:28:36 PM PDT 24
Peak memory 201432 kb
Host smart-3685c377-5a4f-449c-a128-d2fb6a699429
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835650507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1835650507
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3040251907
Short name T535
Test name
Test status
Simulation time 323737903981 ps
CPU time 142.65 seconds
Started Aug 02 05:22:40 PM PDT 24
Finished Aug 02 05:25:03 PM PDT 24
Peak memory 201452 kb
Host smart-c26d4a32-7272-404d-90bb-8d892b7b92b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040251907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3040251907
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.393199625
Short name T669
Test name
Test status
Simulation time 488617329073 ps
CPU time 1046.01 seconds
Started Aug 02 05:22:40 PM PDT 24
Finished Aug 02 05:40:06 PM PDT 24
Peak memory 201504 kb
Host smart-b5d74e87-ed06-499b-88ed-6b41c6316cfe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=393199625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.393199625
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1680164622
Short name T288
Test name
Test status
Simulation time 159723111134 ps
CPU time 332.16 seconds
Started Aug 02 05:22:38 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 201476 kb
Host smart-c45129c6-8c9f-4da1-91bd-8a667942b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680164622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1680164622
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2805773744
Short name T794
Test name
Test status
Simulation time 167995073150 ps
CPU time 74.78 seconds
Started Aug 02 05:22:37 PM PDT 24
Finished Aug 02 05:23:52 PM PDT 24
Peak memory 201452 kb
Host smart-6a31f60d-93fa-42e6-94dd-6ba293b85bf6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805773744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2805773744
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.945211694
Short name T262
Test name
Test status
Simulation time 357882439266 ps
CPU time 69.92 seconds
Started Aug 02 05:22:40 PM PDT 24
Finished Aug 02 05:23:50 PM PDT 24
Peak memory 201448 kb
Host smart-c17f3056-fcc1-420b-8670-ae1ea7578973
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945211694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.945211694
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.342571172
Short name T106
Test name
Test status
Simulation time 591052769186 ps
CPU time 362.78 seconds
Started Aug 02 05:22:54 PM PDT 24
Finished Aug 02 05:28:57 PM PDT 24
Peak memory 201460 kb
Host smart-2ec933e4-478d-41e3-a5e5-88454551e52f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342571172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.342571172
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2766003553
Short name T231
Test name
Test status
Simulation time 84371249074 ps
CPU time 285.51 seconds
Started Aug 02 05:22:50 PM PDT 24
Finished Aug 02 05:27:36 PM PDT 24
Peak memory 201860 kb
Host smart-19724237-990c-4448-92d0-0c8159614208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766003553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2766003553
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1634106613
Short name T402
Test name
Test status
Simulation time 44440887191 ps
CPU time 53.13 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:23:42 PM PDT 24
Peak memory 201360 kb
Host smart-401c001b-cc99-48f2-bcae-1e69b14a0669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634106613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1634106613
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4203894463
Short name T572
Test name
Test status
Simulation time 3619039815 ps
CPU time 9.35 seconds
Started Aug 02 05:22:46 PM PDT 24
Finished Aug 02 05:22:56 PM PDT 24
Peak memory 201364 kb
Host smart-b2742d6c-b297-47e9-a8c2-2ea740ec8fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203894463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4203894463
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.603337810
Short name T747
Test name
Test status
Simulation time 5732582036 ps
CPU time 13.68 seconds
Started Aug 02 05:22:42 PM PDT 24
Finished Aug 02 05:22:56 PM PDT 24
Peak memory 201396 kb
Host smart-c7531f4b-3264-4bb5-b768-4fd7f5b8f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603337810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.603337810
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4074263470
Short name T166
Test name
Test status
Simulation time 415735237243 ps
CPU time 1145.74 seconds
Started Aug 02 05:22:39 PM PDT 24
Finished Aug 02 05:41:45 PM PDT 24
Peak memory 212452 kb
Host smart-036c4ac9-98d7-46ff-90a4-7d9d82f91de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074263470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4074263470
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4131107818
Short name T631
Test name
Test status
Simulation time 362783372 ps
CPU time 1.44 seconds
Started Aug 02 05:22:53 PM PDT 24
Finished Aug 02 05:22:55 PM PDT 24
Peak memory 201224 kb
Host smart-ae92074a-246e-48de-9d29-6a9b20a494e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131107818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4131107818
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2720036407
Short name T534
Test name
Test status
Simulation time 498711574401 ps
CPU time 1090.65 seconds
Started Aug 02 05:22:38 PM PDT 24
Finished Aug 02 05:40:49 PM PDT 24
Peak memory 201524 kb
Host smart-ca9ff1dd-57b2-4134-a51e-2d107f51535b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720036407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2720036407
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2136015362
Short name T617
Test name
Test status
Simulation time 492168245813 ps
CPU time 825.97 seconds
Started Aug 02 05:22:48 PM PDT 24
Finished Aug 02 05:36:35 PM PDT 24
Peak memory 201496 kb
Host smart-e6593df3-8ece-4275-8803-a893d985aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136015362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2136015362
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.367200082
Short name T611
Test name
Test status
Simulation time 493966986417 ps
CPU time 1150.49 seconds
Started Aug 02 05:22:42 PM PDT 24
Finished Aug 02 05:41:53 PM PDT 24
Peak memory 201564 kb
Host smart-302501d7-5115-49f9-aca7-4198d6ffde60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=367200082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.367200082
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2226988129
Short name T326
Test name
Test status
Simulation time 490610023670 ps
CPU time 267.05 seconds
Started Aug 02 05:22:39 PM PDT 24
Finished Aug 02 05:27:06 PM PDT 24
Peak memory 201524 kb
Host smart-6f7f7f00-06d5-49b9-9546-61c841f41fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226988129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2226988129
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1949827099
Short name T733
Test name
Test status
Simulation time 167237861579 ps
CPU time 278.62 seconds
Started Aug 02 05:22:40 PM PDT 24
Finished Aug 02 05:27:19 PM PDT 24
Peak memory 201476 kb
Host smart-48ab309f-c571-4fe3-8eea-b2915ed9823c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949827099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1949827099
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1805491650
Short name T518
Test name
Test status
Simulation time 612126197258 ps
CPU time 340.8 seconds
Started Aug 02 05:22:38 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 201464 kb
Host smart-ffcc479d-7c3f-4e2e-87e5-bb40c6fbadbe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805491650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1805491650
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1659842196
Short name T739
Test name
Test status
Simulation time 139437045715 ps
CPU time 441.37 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:30:11 PM PDT 24
Peak memory 201840 kb
Host smart-f3ec59f5-4147-40bf-8d42-7d3d347e6958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659842196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1659842196
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1186441654
Short name T653
Test name
Test status
Simulation time 42858657593 ps
CPU time 104.99 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:24:34 PM PDT 24
Peak memory 200668 kb
Host smart-acf06da0-7019-4a9a-b7b2-37158055b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186441654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1186441654
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.4212358155
Short name T646
Test name
Test status
Simulation time 5406504167 ps
CPU time 3.94 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:22:48 PM PDT 24
Peak memory 201388 kb
Host smart-e350cbc2-57be-4b3d-ae77-980f8706d1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212358155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.4212358155
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2455693159
Short name T122
Test name
Test status
Simulation time 5601428798 ps
CPU time 4.41 seconds
Started Aug 02 05:22:51 PM PDT 24
Finished Aug 02 05:22:56 PM PDT 24
Peak memory 201388 kb
Host smart-ea1251f4-0da5-4ddf-b6c8-5fb4ec8cd383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455693159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2455693159
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.277786113
Short name T744
Test name
Test status
Simulation time 184417476930 ps
CPU time 230.41 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:26:34 PM PDT 24
Peak memory 217560 kb
Host smart-18562cf3-42b7-4de7-b67b-497adc311536
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277786113 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.277786113
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.601723480
Short name T439
Test name
Test status
Simulation time 471906779 ps
CPU time 1.02 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:22:45 PM PDT 24
Peak memory 201156 kb
Host smart-fe053b55-4f3b-4fbd-975e-86d0bea43917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601723480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.601723480
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3000040900
Short name T318
Test name
Test status
Simulation time 167299998266 ps
CPU time 209.89 seconds
Started Aug 02 05:22:42 PM PDT 24
Finished Aug 02 05:26:12 PM PDT 24
Peak memory 201476 kb
Host smart-caa993d2-e5c6-4bcd-a483-2a951895f858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000040900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3000040900
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2112401420
Short name T587
Test name
Test status
Simulation time 168185002287 ps
CPU time 387.11 seconds
Started Aug 02 05:22:48 PM PDT 24
Finished Aug 02 05:29:16 PM PDT 24
Peak memory 201516 kb
Host smart-9e33acbe-a7a7-4a92-891d-ccd707a420b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112401420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2112401420
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2692761964
Short name T210
Test name
Test status
Simulation time 323032702724 ps
CPU time 187.15 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:25:56 PM PDT 24
Peak memory 200812 kb
Host smart-2f261eb8-e7fa-43df-98c0-3c905208bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692761964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2692761964
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2535327514
Short name T93
Test name
Test status
Simulation time 493481935714 ps
CPU time 1129.14 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:41:46 PM PDT 24
Peak memory 201488 kb
Host smart-6e3919b0-a113-4dc4-9d3f-0f9c801baac4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535327514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2535327514
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.4274321832
Short name T458
Test name
Test status
Simulation time 200884585992 ps
CPU time 223.4 seconds
Started Aug 02 05:23:00 PM PDT 24
Finished Aug 02 05:26:43 PM PDT 24
Peak memory 201460 kb
Host smart-6f0c1851-a275-46d3-a58c-685302d45929
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274321832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.4274321832
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3539549787
Short name T651
Test name
Test status
Simulation time 119814380319 ps
CPU time 444.73 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 201856 kb
Host smart-09efa8dd-b1fe-4fd3-a154-72d0a7f69648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539549787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3539549787
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3111133695
Short name T463
Test name
Test status
Simulation time 33646092437 ps
CPU time 71.98 seconds
Started Aug 02 05:22:57 PM PDT 24
Finished Aug 02 05:24:09 PM PDT 24
Peak memory 201380 kb
Host smart-54f6f849-26c5-40c5-a4bc-d74594b0f6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111133695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3111133695
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3150334058
Short name T570
Test name
Test status
Simulation time 4602795269 ps
CPU time 1.99 seconds
Started Aug 02 05:22:53 PM PDT 24
Finished Aug 02 05:22:56 PM PDT 24
Peak memory 201368 kb
Host smart-3c6b85f7-6510-4ab3-ba3f-49b909348332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150334058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3150334058
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2457239402
Short name T115
Test name
Test status
Simulation time 5960678733 ps
CPU time 4 seconds
Started Aug 02 05:22:52 PM PDT 24
Finished Aug 02 05:22:56 PM PDT 24
Peak memory 201332 kb
Host smart-6929e77d-978c-4edc-abf5-294ead8b40bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457239402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2457239402
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.4223301322
Short name T725
Test name
Test status
Simulation time 152620501116 ps
CPU time 152.94 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:25:22 PM PDT 24
Peak memory 217520 kb
Host smart-8006dfac-cc67-4b4c-93c4-a6a65cc70b3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223301322 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.4223301322
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3350677311
Short name T493
Test name
Test status
Simulation time 311098048 ps
CPU time 0.81 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:22:45 PM PDT 24
Peak memory 201232 kb
Host smart-46530bd9-49a1-473c-8dfe-dfb7bc7e0304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350677311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3350677311
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.4064739049
Short name T688
Test name
Test status
Simulation time 172854799969 ps
CPU time 101.97 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:24:26 PM PDT 24
Peak memory 201580 kb
Host smart-5a937982-34c5-452b-8787-03df98c63bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064739049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.4064739049
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1080409909
Short name T271
Test name
Test status
Simulation time 485407451406 ps
CPU time 281.18 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:27:26 PM PDT 24
Peak memory 201512 kb
Host smart-4976ea28-b6b2-44ca-8e30-e1e69b2226e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080409909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1080409909
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2276971506
Short name T695
Test name
Test status
Simulation time 325661559587 ps
CPU time 201.23 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:26:11 PM PDT 24
Peak memory 201476 kb
Host smart-cd781c0d-14f7-43ea-8ee6-8d0b0cc26c47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276971506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2276971506
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4139370923
Short name T154
Test name
Test status
Simulation time 163964345855 ps
CPU time 91.79 seconds
Started Aug 02 05:22:49 PM PDT 24
Finished Aug 02 05:24:21 PM PDT 24
Peak memory 201432 kb
Host smart-b24613ac-67e0-4f43-8e3c-fcca4f0b3711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139370923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4139370923
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4014246503
Short name T178
Test name
Test status
Simulation time 496252123064 ps
CPU time 68.18 seconds
Started Aug 02 05:22:54 PM PDT 24
Finished Aug 02 05:24:02 PM PDT 24
Peak memory 201460 kb
Host smart-16f4e5f3-ebb0-4d56-bc85-18b694d9c55a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014246503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.4014246503
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3336698712
Short name T87
Test name
Test status
Simulation time 164702919363 ps
CPU time 345.09 seconds
Started Aug 02 05:22:48 PM PDT 24
Finished Aug 02 05:28:33 PM PDT 24
Peak memory 201484 kb
Host smart-c598cd96-7946-419e-b327-f802b72de472
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336698712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3336698712
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4265349275
Short name T480
Test name
Test status
Simulation time 405492122851 ps
CPU time 495.63 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:31:00 PM PDT 24
Peak memory 201444 kb
Host smart-21313795-e485-4b12-bd4a-f234d8d78485
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265349275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.4265349275
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2789495323
Short name T600
Test name
Test status
Simulation time 74862680808 ps
CPU time 248.67 seconds
Started Aug 02 05:22:56 PM PDT 24
Finished Aug 02 05:27:04 PM PDT 24
Peak memory 201828 kb
Host smart-2dd1744d-a504-49dc-acff-227f2f87449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789495323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2789495323
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4006656916
Short name T515
Test name
Test status
Simulation time 39688797996 ps
CPU time 20.4 seconds
Started Aug 02 05:22:44 PM PDT 24
Finished Aug 02 05:23:04 PM PDT 24
Peak memory 201380 kb
Host smart-83164a40-bcf9-4be3-b14d-2ba8e1943263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006656916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4006656916
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3324939942
Short name T751
Test name
Test status
Simulation time 3523931384 ps
CPU time 8.64 seconds
Started Aug 02 05:23:00 PM PDT 24
Finished Aug 02 05:23:09 PM PDT 24
Peak memory 201424 kb
Host smart-aca2a432-3166-403d-908c-437e1784e617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324939942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3324939942
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2844671433
Short name T482
Test name
Test status
Simulation time 5772123620 ps
CPU time 14.43 seconds
Started Aug 02 05:22:55 PM PDT 24
Finished Aug 02 05:23:09 PM PDT 24
Peak memory 201348 kb
Host smart-43bc7067-c4d9-41b2-8578-f5fe609e8d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844671433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2844671433
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2025439501
Short name T738
Test name
Test status
Simulation time 43688302579 ps
CPU time 96.88 seconds
Started Aug 02 05:22:45 PM PDT 24
Finished Aug 02 05:24:22 PM PDT 24
Peak memory 201404 kb
Host smart-ad0ed1c4-73fc-43f7-b440-50a74fa5a116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025439501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2025439501
Directory /workspace/9.adc_ctrl_stress_all/latest
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