Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6960	1			T5	32		T7	41		T10	58
testmodes[AdcCtrlTestmodeNormal]	5122	1			T1	1		T5	9		T7	30
testmodes[AdcCtrlTestmodeLowpower]	5453	1			T1	1		T2	20		T3	13
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3879	1			T5	25		T7	14		T10	27
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1653	1			T5	6		T7	10		T10	18
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1313	1			T5	1		T7	16		T10	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1691	1			T5	6		T7	12		T10	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1843	1			T5	3		T7	11		T10	24
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1257	1			T1	1		T7	7		T10	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1279	1			T7	14		T10	12		T53	19
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1288	1			T7	9		T10	14		T53	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2633	1			T2	19		T3	12		T5	17