Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22158

1

T1

15

T2

20

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3763

1

T1

22

T6

43

T12

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19971

1

T1

37

T2

20

T3

13

auto[1]

5950

1

T6

52

T8

25

T9

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	30	1			T87	13		T211	6		T212	11
values[1]	682	1			T6	43		T15	1		T138	7
values[2]	753	1			T30	22		T213	3		T142	23
values[3]	666	1			T12	20		T55	1		T26	7
values[4]	823	1			T5	12		T29	9		T165	1
values[5]	2808	1			T6	23		T8	25		T9	27
values[6]	738	1			T6	9		T14	27		T15	1
values[7]	670	1			T1	15		T36	7		T140	13
values[8]	703	1			T1	22		T14	13		T50	5
values[9]	1434	1			T12	3		T15	1		T138	1
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	941	1			T6	43		T15	1		T55	1
values[1]	704	1			T138	7		T30	22		T213	3
values[2]	668	1			T12	20		T55	1		T28	11
values[3]	2930	1			T5	12		T8	25		T9	27
values[4]	703	1			T6	23		T10	15		T14	11
values[5]	774	1			T1	15		T6	9		T14	16
values[6]	588	1			T36	7		T214	1		T150	11
values[7]	758	1			T1	22		T14	13		T15	1
values[8]	978	1			T12	3		T138	1		T148	36
values[9]	238	1			T214	1		T30	4		T33	11
minimum	16639	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T214	1		T16	5		T162	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T6	21		T15	1		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T49	1		T215	1		T216	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T138	1		T30	8		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T55	1		T28	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	10		T29	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T5	3		T8	25		T9	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T29	1		T218	12		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	17		T10	8		T14	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T219	1		T220	1		T221	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	9		T6	5		T140	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	16		T15	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T36	7		T222	11		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T214	1		T150	1		T151	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T50	5		T223	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	10		T14	13		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T138	1		T148	22		T143	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	3		T139	12		T171	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T30	2		T172	10		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T214	1		T33	6		T224	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16486	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T157	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T16	2		T162	10		T154	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	22		T17	7		T142	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T216	5		T225	2		T226	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T138	6		T30	14		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T28	10		T227	8		T228	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	10		T29	9		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T5	9		T159	8		T230	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	8		T18	4		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	6		T10	7		T150	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T220	7		T231	12		T232	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	6		T6	4		T142	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T29	11		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T222	12		T145	3		T234	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T150	10		T151	13		T235	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T223	11		T28	4		T227	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	12		T138	7		T28	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T148	14		T220	19		T236	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T171	4		T38	9		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T30	2		T173	14		T238	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T33	5		T207	2		T237	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T10	1		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T157	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T87	1		T211	6		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T214	1		T16	5		T162	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	21		T15	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T239	16		T215	1		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T30	8		T213	1		T142	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T55	1		T26	7		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	10		T29	1		T141	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	3		T37	14		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T29	1		T165	1		T18	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1535	1			T6	17		T8	25		T9	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T218	12		T220	1		T221	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	5		T14	11		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	16		T15	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	9		T36	7		T140	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T214	1		T150	1		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	5		T223	1		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	10		T14	13		T138	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	445	1			T138	1		T148	22		T30	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T12	3		T15	1		T55	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T87	12		T212	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	2		T162	10		T154	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	22		T138	6		T17	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T239	12		T240	12		T241	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	14		T213	2		T142	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T28	10		T227	8		T228	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	10		T29	9		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	9		T37	6		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T29	8		T18	4		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T6	6		T10	7		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T220	7		T231	25		T232	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	4		T150	13		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T16	1		T29	11		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	6		T142	20		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T150	10		T235	2		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T223	11		T28	4		T227	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	12		T138	7		T28	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T148	14		T30	2		T220	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T171	4		T33	5		T162	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T214	1		T16	4		T162	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	23		T15	1		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T49	1		T215	1		T216	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T138	7		T30	15		T213	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T55	1		T28	11		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	11		T29	10		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T5	10		T8	2		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T29	9		T218	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	7		T10	8		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T219	1		T220	8		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	7		T6	5		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	1		T15	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T36	1		T222	13		T145	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T214	1		T150	11		T151	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T50	1		T223	12		T16	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T1	13		T14	1		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T138	1		T148	16		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T139	1		T171	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T30	3		T172	1		T173	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T214	1		T33	6		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16623	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T157	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	3		T162	12		T154	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	20		T17	1		T142	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T216	6		T225	7		T226	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	7		T141	10		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T228	14		T244	7		T93	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	9		T245	12		T246	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T5	2		T8	23		T9	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T218	11		T18	12		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	16		T10	7		T14	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T221	11		T232	13		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	8		T6	4		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	15		T16	1		T38	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T36	6		T222	10		T234	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T151	10		T141	7		T221	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T50	4		T16	1		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	9		T14	12		T138	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T148	20		T143	2		T248	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	2		T139	11		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T30	1		T172	9		T249	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T33	5		T224	8		T207	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T250	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T157	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	9	39	81.25	9

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T87	13		T211	1		T212	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T214	1		T16	4		T162	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	23		T15	1		T138	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T239	13		T215	1		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T30	15		T213	3		T142	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T55	1		T26	1		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	11		T29	10		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T5	10		T37	7		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T29	9		T165	1		T18	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T6	7		T8	2		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T218	1		T220	8		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	5		T14	1		T150	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T14	1		T15	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	7		T36	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T214	1		T150	11		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T50	1		T223	12		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	13		T14	1		T138	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T138	1		T148	16		T30	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T12	1		T15	1		T55	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T211	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T16	3		T162	12		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	20		T17	1		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T239	15		T241	5		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T30	7		T142	12		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T26	6		T228	14		T244	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	9		T141	10		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	2		T37	13		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	12		T245	12		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T6	16		T8	23		T9	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T218	11		T221	11		T232	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	4		T14	10		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	15		T16	1		T38	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	8		T36	6		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T141	7		T221	3		T235	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T50	4		T16	1		T182	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	9		T14	12		T138	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	373	1			T148	20		T30	1		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T12	2		T139	11		T171	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22061

1

T1

22

T2

20

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3860

1

T1

15

T6

52

T10

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19882

1

T1

37

T2

20

T3

13

auto[1]

6039

1

T5

12

T6

23

T8

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32	1			T36	7		T236	10		T251	12
values[1]	666	1			T12	20		T14	16		T138	14
values[2]	690	1			T5	12		T6	9		T10	15
values[3]	695	1			T15	1		T16	2		T26	7
values[4]	779	1			T1	22		T15	1		T33	11
values[5]	850	1			T1	15		T6	43		T12	3
values[6]	778	1			T214	1		T16	7		T142	38
values[7]	825	1			T14	13		T55	1		T148	23
values[8]	2778	1			T8	25		T9	27		T13	35
values[9]	1214	1			T6	23		T14	11		T15	1
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	811	1			T5	12		T6	9		T12	20
values[1]	647	1			T10	15		T55	1		T30	4
values[2]	872	1			T1	22		T15	1		T16	2
values[3]	521	1			T15	1		T28	5		T165	1
values[4]	976	1			T1	15		T6	43		T12	3
values[5]	849	1			T55	1		T139	12		T214	1
values[6]	2944	1			T8	25		T9	27		T13	35
values[7]	621	1			T28	10		T30	22		T252	1
values[8]	863	1			T6	23		T14	11		T15	1
values[9]	168	1			T138	7		T214	1		T38	13
minimum	16649	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	3		T12	10		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	5		T14	16		T138	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T55	1		T30	2		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	8		T17	5		T151	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	10		T26	7		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T15	1		T16	2		T151	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	1		T28	1		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T165	1		T38	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T50	5		T55	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T1	9		T6	21		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T55	1		T139	12		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T152	1		T142	18		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T8	25		T9	27		T13	35
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	13		T214	1		T218	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	1		T165	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	8		T252	1		T37	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	17		T15	1		T143	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T14	11		T138	1		T148	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T138	1		T38	8		T236	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T214	1		T229	1		T224	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16481	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T157	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	9		T12	10		T29	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	4		T138	7		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T30	2		T155	11		T20	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	7		T17	7		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	12		T28	10		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T151	14		T19	4		T227	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T28	4		T153	12		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T38	9		T173	14		T46	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T155	1		T253	12		T247	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	6		T6	22		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T19	2		T227	8		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T142	20		T178	12		T254	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T159	8		T148	11		T230	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T45	13		T255	13		T254	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T28	9		T145	3		T235	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	14		T37	6		T162	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	6		T220	19		T239	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T148	3		T171	4		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T138	6		T38	5		T236	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T229	11		T48	5		T256	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T157	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T36	7		T236	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T251	1		T257	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	10		T29	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	16		T138	7		T17	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	3		T55	1		T258	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	5		T10	8		T140	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T26	7		T28	1		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	1		T16	2		T151	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	10		T15	1		T33	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T165	1		T152	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T50	5		T55	1		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	9		T6	21		T12	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T214	1		T19	3		T227	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T16	5		T142	18		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T55	1		T148	12		T139	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	13		T214	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T8	25		T9	27		T13	35
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	8		T218	12		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	17		T15	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	458	1			T14	11		T138	1		T148	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T236	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T251	11		T257	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	10		T29	8		T150	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	7		T17	7		T233	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T5	9		T157	2		T259	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	4		T10	7		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T28	10		T29	11		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T151	14		T244	3		T21	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	12		T33	5		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	9		T19	4		T227	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T28	4		T155	1		T235	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	6		T6	22		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T19	2		T227	8		T260	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	2		T142	20		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T148	11		T223	11		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T45	13		T255	13		T85	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T159	8		T230	21		T28	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T30	14		T237	29		T23	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	6		T138	6		T38	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T148	3		T171	4		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3