Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21955

1

T2

20

T3

13

T5

59

auto[ADC_CTRL_FILTER_COND_OUT]

3966

1

T1

37

T5

12

T6

66

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19671

1

T1

15

T2

20

T3

13

auto[1]

6250

1

T1

22

T8

25

T9

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	263	1			T28	11		T30	26		T18	20
values[0]	15	1			T287	14		T314	1		-	-
values[1]	608	1			T14	11		T15	1		T36	7
values[2]	2853	1			T6	9		T8	25		T9	27
values[3]	754	1			T1	15		T12	20		T139	12
values[4]	749	1			T12	3		T138	14		T148	23
values[5]	796	1			T1	22		T6	43		T36	1
values[6]	727	1			T14	13		T15	1		T55	1
values[7]	729	1			T50	5		T138	1		T150	11
values[8]	848	1			T14	16		T55	2		T16	3
values[9]	965	1			T5	12		T6	23		T10	15
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	662	1			T14	11		T15	1		T16	7
values[1]	2890	1			T1	15		T6	9		T8	25
values[2]	701	1			T12	23		T138	14		T148	23
values[3]	795	1			T6	43		T36	1		T223	12
values[4]	756	1			T1	22		T14	13		T55	1
values[5]	721	1			T15	1		T138	1		T171	7
values[6]	824	1			T50	5		T16	3		T150	11
values[7]	743	1			T10	15		T14	16		T138	7
values[8]	953	1			T6	23		T28	11		T30	4
values[9]	120	1			T5	12		T30	22		T144	22
minimum	16756	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	1		T16	5		T213	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	11		T165	1		T233	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T6	5		T8	25		T9	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	9		T214	1		T141	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	10		T16	2		T17	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	3		T138	7		T148	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T162	13		T38	1		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	21		T36	1		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T55	1		T28	1		T141	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	10		T14	13		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T138	1		T214	2		T26	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T15	1		T171	3		T153	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T16	2		T44	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T50	5		T150	1		T142	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	16		T138	1		T33	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	8		T55	2		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T28	1		T151	12		T252	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	17		T30	2		T19	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T30	8		T144	10		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T5	3		T273	15		T261	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16519	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T36	7		T224	11		T286	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	2		T213	2		T172	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T233	18		T227	8		T235	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T6	4		T159	8		T148	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	6		T142	20		T19	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	10		T17	7		T207	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T138	7		T148	11		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T162	10		T38	9		T220	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	22		T223	11		T150	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	4		T37	6		T162	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	12		T28	9		T29	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T153	12		T242	7		T290	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T171	4		T153	12		T45	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T16	1		T162	11		T154	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T150	10		T142	10		T235	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T138	6		T33	5		T154	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	7		T157	12		T244	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	10		T151	14		T18	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	6		T30	2		T19	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T30	14		T144	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T5	9		T273	11		T113	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	1		T10	1		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T286	14		T294	2		T87	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T28	1		T30	8		T18	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T30	2		T271	1		T313	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T287	8		T314	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	1		T213	1		T155	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	11		T36	7		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T6	5		T8	25		T9	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T214	1		T142	18		T143	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	10		T139	12		T16	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	9		T29	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T162	13		T245	13		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	3		T138	7		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	1		T37	14		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	10		T6	21		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T55	1		T214	2		T26	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	13		T15	1		T171	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T138	1		T154	11		T221	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T50	5		T150	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	16		T16	2		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T55	2		T152	2		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T138	1		T151	12		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	3		T6	17		T10	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T28	10		T30	14		T18	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T30	2		T271	8		T273	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T287	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T213	2		T228	3		T24	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T233	18		T227	8		T235	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T6	4		T159	8		T148	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T142	20		T19	2		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	10		T17	7		T207	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	6		T29	11		T19	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T162	10		T38	9		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T138	7		T148	11		T223	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T28	4		T37	6		T162	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	12		T6	22		T28	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T153	12		T242	7		T271	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T171	4		T29	8		T45	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T154	14		T316	7		T317	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T150	10		T153	12		T142	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T16	1		T33	5		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T239	12		T157	12		T244	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T138	6		T151	14		T220	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	9		T6	6		T10	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T15	1		T16	4		T213	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	1		T165	1		T233	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T6	5		T8	2		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	7		T214	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	11		T16	1		T17	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T12	1		T138	8		T148	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T162	11		T38	10		T220	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	23		T36	1		T223	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T55	1		T28	5		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	13		T14	1		T28	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T138	1		T214	2		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T15	1		T171	5		T153	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	2		T44	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T50	1		T150	11		T142	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	1		T138	7		T33	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	8		T55	2		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T28	11		T151	15		T252	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T6	7		T30	3		T19	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T30	15		T144	13		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T5	10		T273	12		T261	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16646	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T36	1		T224	1		T286	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T16	3		T155	2		T246	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	10		T143	11		T235	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T6	4		T8	23		T9	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	8		T141	10		T142	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	9		T16	1		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	2		T138	6		T148	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T162	12		T246	8		T182	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	20		T140	12		T38	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T141	7		T37	13		T48	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	9		T14	12		T151	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T26	6		T153	11		T318	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T171	2		T153	10		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	1		T162	13		T154	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T50	4		T142	12		T235	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	15		T33	5		T218	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	7		T141	9		T157	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T151	11		T18	12		T155	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	16		T30	1		T19	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T30	7		T144	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T5	2		T273	14		T261	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T228	7		T24	1		T294	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T36	6		T224	10		T294	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T28	11		T30	15		T18	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T30	3		T271	9		T313	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T287	7		T314	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T213	3		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	1		T36	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T6	5		T8	2		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T214	1		T142	21		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	11		T139	1		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	7		T29	12		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T162	11		T245	1		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	1		T138	8		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T28	5		T37	7		T162	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	13		T6	23		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T55	1		T214	2		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T14	1		T15	1		T171	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T138	1		T154	15		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T50	1		T150	11		T153	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	1		T16	2		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T55	2		T152	2		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T138	7		T151	15		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	10		T6	7		T10	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T30	7		T18	12		T155	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T30	1		T313	4		T273	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T287	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T155	2		T246	11		T224	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	10		T36	6		T235	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T6	4		T8	23		T9	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T142	17		T143	11		T19	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	9		T139	11		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	8		T141	10		T235	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T162	12		T245	12		T246	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	2		T138	6		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T37	13		T48	4		T275	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	9		T6	20		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	6		T141	7		T153	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	12		T171	2		T143	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T154	10		T221	3		T276	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T50	4		T153	10		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	15		T16	1		T33	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T239	15		T157	14		T244	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T151	11		T154	9		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	2		T6	16		T10	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40