Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22131

1

T1

37

T2

20

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3790

1

T6

43

T12

23

T14

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19991

1

T1

37

T2

20

T3

13

auto[1]

5930

1

T6

52

T8

25

T9

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	323	1			T12	3		T138	1		T171	7
values[0]	17	1			T307	11		T211	6		-	-
values[1]	749	1			T6	43		T15	1		T138	7
values[2]	733	1			T30	22		T213	3		T233	9
values[3]	577	1			T12	20		T55	1		T28	11
values[4]	871	1			T5	12		T26	7		T18	20
values[5]	2811	1			T6	23		T8	25		T9	27
values[6]	750	1			T6	9		T14	16		T15	1
values[7]	650	1			T1	15		T36	7		T140	13
values[8]	724	1			T1	22		T14	13		T50	5
values[9]	1102	1			T15	1		T55	1		T148	36
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	800	1			T6	43		T15	1		T138	7
values[1]	673	1			T30	22		T213	3		T233	9
values[2]	746	1			T12	20		T55	1		T28	11
values[3]	2880	1			T5	12		T8	25		T9	27
values[4]	681	1			T6	23		T10	15		T14	11
values[5]	801	1			T6	9		T14	16		T15	1
values[6]	573	1			T1	15		T36	8		T150	11
values[7]	759	1			T1	22		T14	13		T15	1
values[8]	1115	1			T12	3		T138	1		T148	36
values[9]	109	1			T152	1		T220	11		T224	9
minimum	16784	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	5		T143	12		T246	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T6	21		T15	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	12		T157	15		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T30	8		T213	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T55	1		T28	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	10		T29	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T5	3		T8	25		T9	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	1		T165	1		T18	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	17		T10	8		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	11		T219	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	5		T14	16		T140	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T15	1		T214	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	9		T36	7		T222	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T36	1		T150	1		T151	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	10		T50	5		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	13		T15	1		T138	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T138	1		T148	22		T30	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T12	3		T139	12		T171	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T220	1		T173	1		T319	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T152	1		T224	9		T237	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16496	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T55	1		T155	4		T320	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	2		T274	2		T280	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	22		T138	6		T17	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	12		T157	12		T225	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	14		T213	2		T233	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T28	10		T227	8		T228	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	10		T29	9		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T5	9		T159	8		T230	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T29	8		T18	4		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	6		T10	7		T150	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T220	7		T231	12		T232	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	4		T38	5		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T16	1		T29	11		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	6		T222	12		T145	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T150	10		T151	13		T235	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	12		T223	11		T28	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T138	7		T28	9		T233	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T148	14		T30	2		T220	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T171	4		T33	5		T38	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T220	10		T173	14		T238	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T237	15		T184	5		T93	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	1		T10	1		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T155	1		T157	2		T21	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T138	1		T37	1		T166	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T12	3		T171	3		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T307	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T211	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	5		T143	12		T260	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	21		T15	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T246	12		T157	15		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T30	8		T213	1		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T55	1		T28	1		T153	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	10		T29	1		T141	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	3		T26	7		T37	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T18	16		T152	1		T245	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1532	1			T6	17		T8	25		T9	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	11		T29	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	5		T14	16		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T15	1		T214	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	9		T36	7		T140	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T150	1		T44	1		T141	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	10		T50	5		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	13		T138	7		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T148	22		T30	2		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T15	1		T55	1		T139	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T220	10		T192	14		T321	23
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T171	4		T207	2		T93	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T307	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	2		T260	10		T274	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	22		T138	6		T17	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T157	12		T240	12		T322	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	14		T213	2		T233	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T28	10		T153	12		T227	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	10		T29	9		T19	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	9		T37	6		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T18	4		T154	9		T20	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T6	6		T10	7		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	8		T220	7		T231	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	4		T150	13		T38	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	1		T29	11		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	6		T222	12		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T150	10		T142	20		T235	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	12		T223	11		T28	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T138	7		T28	9		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T148	14		T30	2		T220	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T33	5		T162	11		T38	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T16	4		T143	1		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	23		T15	1		T138	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T153	13		T157	13		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T30	15		T213	3		T233	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T55	1		T28	11		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	11		T29	10		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T5	10		T8	2		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	9		T165	1		T18	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	7		T10	8		T150	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	1		T219	1		T220	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	5		T14	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T15	1		T214	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	7		T36	1		T222	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T36	1		T150	11		T151	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	13		T50	1		T223	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	1		T15	1		T138	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T138	1		T148	16		T30	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T12	1		T139	1		T171	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T220	11		T173	15		T319	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T152	1		T224	1		T237	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16686	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T55	1		T155	2		T320	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	3		T143	11		T246	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	20		T17	1		T162	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T153	11		T157	14		T225	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T30	7		T141	10		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T228	14		T244	7		T216	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	9		T245	12		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T5	2		T8	23		T9	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T18	12		T154	9		T246	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	16		T10	7		T151	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	10		T221	11		T232	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	4		T14	15		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T16	1		T142	17		T19	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	8		T36	6		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T151	10		T141	7		T221	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	9		T50	4		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	12		T138	6		T141	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T148	20		T30	1		T143	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	2		T139	11		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T224	8		T184	6		T93	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T264	1		T49	1		T272	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T155	3		T157	2		T21	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T138	1		T37	1		T166	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T12	1		T171	5		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T307	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T211	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T16	4		T143	1		T260	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	23		T15	1		T138	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T246	1		T157	13		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T30	15		T213	3		T233	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T55	1		T28	11		T153	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	11		T29	10		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T5	10		T26	1		T37	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T18	8		T152	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T6	7		T8	2		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	1		T29	9		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	5		T14	1		T150	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T15	1		T214	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	7		T36	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T150	11		T44	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	13		T50	1		T223	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	1		T138	8		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T148	16		T30	3		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T15	1		T55	1		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T248	2		T192	14		T321	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T12	2		T171	2		T224	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T211	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	3		T143	11		T239	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	20		T17	1		T162	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T246	11		T157	14		T322	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T30	7		T142	12		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T153	11		T228	14		T216	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	9		T141	10		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	2		T26	6		T37	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T18	12		T245	12		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T6	16		T8	23		T9	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	10		T221	11		T232	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	4		T14	15		T38	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T16	1		T19	4		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	8		T36	6		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T141	7		T142	17		T221	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	9		T50	4		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	12		T138	6		T151	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T148	20		T30	1		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T139	11		T33	5		T162	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40