Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22097

1

T1

22

T2

20

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3824

1

T1

15

T6

52

T10

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19930

1

T1

37

T2

20

T3

13

auto[1]

5991

1

T5

12

T8

25

T9

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	308	1			T14	11		T138	7		T38	13
values[0]	17	1			T36	7		T141	10		-	-
values[1]	691	1			T12	20		T14	16		T138	14
values[2]	622	1			T5	12		T6	9		T10	15
values[3]	767	1			T1	22		T15	1		T16	2
values[4]	744	1			T33	11		T165	1		T141	11
values[5]	759	1			T1	15		T6	43		T12	3
values[6]	889	1			T139	12		T214	1		T16	7
values[7]	824	1			T14	13		T55	1		T223	12
values[8]	2785	1			T8	25		T9	27		T13	35
values[9]	901	1			T6	23		T15	1		T138	1
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	638	1			T5	12		T6	9		T14	16
values[1]	563	1			T10	15		T55	1		T30	4
values[2]	891	1			T1	22		T15	1		T16	2
values[3]	562	1			T15	1		T28	5		T165	1
values[4]	972	1			T1	15		T6	43		T12	3
values[5]	868	1			T14	13		T55	1		T139	12
values[6]	2913	1			T8	25		T9	27		T13	35
values[7]	629	1			T28	10		T30	22		T252	1
values[8]	894	1			T6	23		T14	11		T15	1
values[9]	132	1			T138	7		T214	1		T38	13
minimum	16859	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	3		T36	7		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	5		T14	16		T140	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T55	1		T30	2		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	8		T151	11		T246	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	10		T26	7		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T15	1		T16	2		T151	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	1		T28	1		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T165	1		T38	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T50	5		T55	1		T16	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T1	9		T6	21		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T55	1		T139	12		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T14	13		T152	1		T142	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T8	25		T9	27		T13	35
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T214	1		T218	12		T45	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T28	1		T165	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	8		T252	1		T37	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	17		T15	1		T143	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T14	11		T138	1		T148	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T138	1		T38	8		T236	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T214	1		T229	1		T48	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16538	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T138	7		T141	10		T221	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	9		T29	8		T150	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	4		T17	7		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T30	2		T155	11		T20	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	7		T151	13		T207	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	12		T28	10		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T151	14		T19	4		T227	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T28	4		T162	10		T235	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	9		T173	14		T87	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	2		T155	1		T260	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	6		T6	22		T29	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T233	10		T19	2		T227	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T142	20		T178	12		T254	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T159	8		T148	11		T230	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T45	13		T255	13		T254	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T28	9		T145	3		T235	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	14		T37	6		T162	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	6		T220	9		T239	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T148	3		T171	4		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T138	6		T38	5		T236	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T229	11		T48	5		T256	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	1		T10	1		T12	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T138	7		T157	12		T323	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T138	1		T38	8		T143	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T14	11		T48	6		T183	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T36	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T141	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	10		T29	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	16		T138	7		T17	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T55	1		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	5		T10	8		T140	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	10		T26	7		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T15	1		T16	2		T151	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T33	6		T141	11		T153	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T165	1		T152	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	1		T50	5		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	9		T6	21		T12	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T139	12		T214	1		T16	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T142	18		T143	12		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T55	1		T223	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	13		T214	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T8	25		T9	27		T13	35
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T30	8		T218	12		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	17		T15	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T138	1		T148	10		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T138	6		T38	5		T215	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T48	5		T305	9		T324	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	10		T29	8		T150	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	7		T17	7		T233	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	9		T155	11		T20	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	4		T10	7		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	12		T28	10		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T151	14		T227	8		T244	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T33	5		T153	12		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T38	9		T19	4		T222	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T28	4		T155	1		T235	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	6		T6	22		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T16	2		T19	2		T227	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T142	20		T47	1		T234	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T223	11		T150	10		T213	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T45	13		T255	13		T254	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T159	8		T148	11		T230	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T30	14		T37	6		T237	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	6		T220	9		T145	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T148	3		T171	4		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	10		T36	1		T29	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	5		T14	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T55	1		T30	3		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	8		T151	14		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	13		T26	1		T28	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	1		T16	1		T151	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	1		T28	5		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T165	1		T38	10		T173	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T50	1		T55	1		T16	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T1	7		T6	23		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T55	1		T139	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	1		T152	1		T142	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T8	2		T9	3		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T214	1		T218	1		T45	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T28	10		T165	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T30	15		T252	1		T37	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	7		T15	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T14	1		T138	1		T148	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T138	7		T38	6		T236	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T214	1		T229	12		T48	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16692	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T138	8		T141	1		T221	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	2		T36	6		T172	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	4		T14	15		T140	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T30	1		T155	12		T20	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	7		T151	10		T246	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	9		T26	6		T33	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T16	1		T151	11		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T141	10		T162	12		T235	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T87	7		T261	11		T99	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T50	4		T16	3		T245	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T1	8		T6	20		T12	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T139	11		T19	1		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	12		T142	17		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T8	23		T9	24		T13	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T218	11		T45	13		T248	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T235	4		T224	16		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T30	7		T37	13		T143	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	16		T143	2		T239	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T14	10		T148	9		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T38	7		T236	4		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T48	4		T263	1		T325	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T12	9		T154	10		T241	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T138	6		T141	9		T221	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T138	7		T38	6		T143	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T14	1		T48	7		T183	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T36	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T141	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	11		T29	9		T150	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	1		T138	8		T17	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	10		T55	1		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	5		T10	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	13		T26	1		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	1		T16	1		T151	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T33	6		T141	1		T153	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T165	1		T152	1		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	1		T50	1		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	7		T6	23		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T139	1		T214	1		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T142	21		T143	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T55	1		T223	12		T150	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	1		T214	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T8	2		T9	3		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T30	15		T218	1		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	7		T15	1		T220	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T138	1		T148	4		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T38	7		T143	2		T215	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T14	10		T48	4		T324	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T36	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T141	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	9		T154	10		T172	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	15		T138	6		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	2		T155	12		T20	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	4		T10	7		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	9		T26	6		T30	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T16	1		T151	11		T244	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	5		T141	10		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T222	10		T172	17		T46	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	4		T245	12		T155	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	8		T6	20		T12	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T139	11		T16	3		T19	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T142	17		T143	11		T246	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T18	12		T154	9		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	12		T45	13		T49	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T8	23		T9	24		T13	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T30	7		T218	11		T37	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	16		T239	15		T248	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T148	9		T171	2		T16	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40