Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22061

1

T2

20

T3

13

T5

59

auto[ADC_CTRL_FILTER_COND_OUT]

3860

1

T1

37

T5

12

T12

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T2

20

T3

13

T5

71

auto[1]

6428

1

T1

37

T6

52

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	635	1			T6	23		T7	1		T10	5
values[0]	68	1			T154	19		T231	13		T271	16
values[1]	722	1			T15	1		T138	7		T171	7
values[2]	3128	1			T1	22		T8	25		T9	27
values[3]	873	1			T12	20		T139	12		T26	7
values[4]	545	1			T15	1		T55	1		T214	1
values[5]	625	1			T1	15		T14	11		T55	1
values[6]	775	1			T6	52		T10	15		T50	5
values[7]	825	1			T5	12		T12	3		T14	13
values[8]	564	1			T14	16		T233	20		T37	20
values[9]	924	1			T15	1		T165	1		T233	5
minimum	16237	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	721	1			T171	7		T214	1		T28	16
values[1]	3139	1			T1	22		T8	25		T9	27
values[2]	669	1			T139	12		T28	10		T165	1
values[3]	663	1			T15	1		T55	1		T223	12
values[4]	666	1			T1	15		T10	15		T14	11
values[5]	761	1			T6	52		T14	13		T50	5
values[6]	725	1			T5	12		T12	3		T138	1
values[7]	647	1			T14	16		T18	20		T37	20
values[8]	792	1			T15	1		T33	11		T151	26
values[9]	212	1			T6	23		T140	13		T173	15
minimum	16926	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T171	3		T29	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T214	1		T28	2		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T8	25		T9	27		T13	35
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T1	10		T12	10		T16	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T28	1		T162	13		T19	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T139	12		T165	1		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T15	1		T214	1		T30	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T55	1		T223	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T10	8		T55	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	9		T14	11		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	26		T14	13		T138	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T50	5		T245	13		T142	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T12	3		T17	5		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	3		T138	1		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	16		T18	16		T37	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	1		T19	1		T235	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T165	1		T233	1		T154	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T15	1		T33	6		T151	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T6	17		T173	1		T318	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T140	13		T232	14		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16551	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T138	1		T141	11		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T171	4		T29	9		T150	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T28	14		T29	11		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T159	8		T230	21		T281	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	12		T12	10		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T28	9		T162	10		T19	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T236	9		T184	5		T326	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T30	14		T150	13		T145	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T223	11		T213	2		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	7		T29	8		T234	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	6		T148	11		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	26		T138	7		T148	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T142	10		T173	14		T178	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	7		T233	8		T142	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T5	9		T233	10		T239	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T18	4		T37	6		T38	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T19	4		T235	12		T21	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T233	4		T154	14		T157	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T33	5		T151	14		T222	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T6	6		T173	14		T318	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T232	12		T271	8		T273	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T10	1		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T138	6		T154	9		T231	25

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	450	1			T6	17		T7	1		T10	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T140	13		T33	6		T151	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T271	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T154	10		T231	1		T209	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	1		T171	3		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T138	1		T214	1		T28	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T8	25		T9	27		T13	35
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T1	10		T16	7		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T26	7		T28	1		T162	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	10		T139	12		T218	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T214	1		T30	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	1		T213	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	1		T29	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	9		T14	11		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	26		T10	8		T138	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T50	5		T148	12		T245	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T12	3		T14	13		T148	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	3		T138	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	16		T233	1		T37	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T233	1		T152	1		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T165	1		T233	1		T18	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T15	1		T222	11		T232	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16096	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T6	6		T173	14		T193	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T33	5		T151	14		T182	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T271	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T154	9		T231	12		T209	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T171	4		T150	10		T162	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T138	6		T28	14		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T159	8		T230	21		T29	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T1	12		T16	2		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T28	9		T162	10		T19	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	10		T220	9		T242	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T30	14		T150	13		T145	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T213	2		T38	9		T155	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T29	8		T247	9		T323	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	6		T223	11		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	26		T10	7		T138	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T148	11		T142	10		T168	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T148	3		T17	7		T142	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	9		T173	14		T239	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T233	8		T37	6		T260	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T233	10		T19	4		T235	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T233	4		T18	4		T38	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T222	12		T232	12		T228	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T171	5		T29	10		T150	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T214	1		T28	16		T29	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T8	2		T9	3		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T1	13		T12	11		T16	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T28	10		T162	11		T19	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T139	1		T165	1		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	1		T214	1		T30	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T55	1		T223	12		T213	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	8		T55	1		T29	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	7		T14	1		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	28		T14	1		T138	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T50	1		T245	1		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	1		T17	11		T233	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	10		T138	1		T233	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	1		T18	8		T37	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T152	1		T19	5		T235	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T165	1		T233	5		T154	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T15	1		T33	6		T151	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T6	7		T173	15		T318	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T140	1		T232	13		T271	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16679	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T138	7		T141	1		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T171	2		T155	3		T246	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T144	9		T276	9		T244	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T8	23		T9	24		T13	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	9		T12	9		T16	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T162	12		T19	4		T246	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T139	11		T262	13		T184	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T30	7		T221	3		T259	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T143	11		T155	12		T172	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	7		T234	11		T247	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	8		T14	10		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	24		T14	12		T138	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T50	4		T245	12		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	2		T17	1		T141	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T5	2		T143	2		T239	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	15		T18	12		T37	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T235	9		T224	10		T21	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T154	10		T157	2		T174	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T33	5		T151	11		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T6	16		T318	10		T327	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T140	12		T232	13		T273	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T162	13		T92	11		T192	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T141	10		T154	9		T180	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	456	1			T6	7		T7	1		T10	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T140	1		T33	6		T151	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T271	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T154	10		T231	13		T209	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	1		T171	5		T150	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T138	7		T214	1		T28	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T8	2		T9	3		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T1	13		T16	5		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T26	1		T28	10		T162	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T12	11		T139	1		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	1		T214	1		T30	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T55	1		T213	3		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T55	1		T29	9		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	7		T14	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	28		T10	8		T138	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T50	1		T148	12		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T14	1		T148	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	10		T138	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	1		T233	9		T37	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T233	11		T152	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T165	1		T233	5		T18	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T15	1		T222	13		T232	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16237	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T6	16		T193	13		T327	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T140	12		T33	5		T151	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T154	9		T209	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T171	2		T162	13		T155	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T141	10		T276	9		T169	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T8	23		T9	24		T13	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	9		T16	4		T30	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T26	6		T162	12		T19	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	9		T139	11		T218	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T30	7		T221	3		T224	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T155	12		T172	9		T157	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T247	11		T225	7		T313	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	8		T14	10		T151	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	24		T10	7		T138	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	4		T148	11		T245	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	2		T14	12		T148	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	2		T239	15		T276	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	15		T37	13		T172	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T143	2		T235	9		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T18	12		T38	7		T143	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T222	10		T232	13		T228	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40