Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22158

1

T1

15

T2

20

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3763

1

T1

22

T5

12

T6

43

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19550

1

T2

20

T3

13

T5

59

auto[1]

6371

1

T1

37

T5

12

T6

75

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	361	1			T50	5		T223	12		T233	11
values[0]	62	1			T36	7		T271	9		T319	1
values[1]	614	1			T6	23		T138	21		T16	2
values[2]	692	1			T1	22		T5	12		T138	1
values[3]	902	1			T10	15		T55	1		T140	13
values[4]	571	1			T6	9		T15	1		T36	1
values[5]	748	1			T1	15		T6	43		T12	20
values[6]	791	1			T14	11		T15	1		T26	7
values[7]	650	1			T214	1		T29	9		T150	11
values[8]	757	1			T148	23		T44	1		T217	1
values[9]	3159	1			T8	25		T9	27		T12	3
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	657	1			T1	22		T6	23		T138	14
values[1]	696	1			T5	12		T138	1		T55	1
values[2]	851	1			T10	15		T15	1		T55	1
values[3]	538	1			T6	9		T14	13		T36	1
values[4]	748	1			T1	15		T6	43		T12	20
values[5]	857	1			T14	11		T15	1		T165	1
values[6]	2752	1			T8	25		T9	27		T13	35
values[7]	790	1			T14	16		T55	1		T148	23
values[8]	958	1			T12	3		T50	5		T148	13
values[9]	207	1			T150	14		T44	1		T233	11
minimum	16867	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	17		T153	12		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	10		T138	7		T222	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T138	1		T55	1		T139	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T5	3		T214	1		T16	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T10	8		T55	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T15	1		T140	13		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	5		T14	13		T16	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T36	1		T172	10		T239	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	9		T12	10		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	21		T15	1		T26	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T165	1		T19	3		T246	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	11		T15	1		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T8	25		T9	27		T13	35
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T214	1		T29	1		T151	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T55	1		T235	3		T45	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T14	16		T148	12		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T12	3		T50	5		T171	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T148	10		T223	1		T142	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T233	1		T284	11		T278	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T150	1		T44	1		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16521	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T235	5		T237	1		T49	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	6		T153	12		T162	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	12		T138	7		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T155	1		T242	7		T157	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	9		T16	1		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	7		T29	11		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	7		T227	8		T173	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	4		T16	2		T233	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T239	12		T178	12		T23	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	6		T12	10		T18	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	22		T28	4		T29	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T19	2		T144	12		T182	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T37	6		T38	9		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T159	8		T230	21		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	8		T151	13		T227	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T235	2		T45	13		T228	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T148	11		T19	7		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T171	4		T28	19		T30	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T148	3		T223	11		T142	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T233	10		T284	13		T278	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T150	13		T226	9		T328	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	1		T10	1		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T235	6		T237	14		T271	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T50	5		T233	1		T145	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T223	1		T142	18		T217	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T36	7		T271	1		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T186	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	17		T138	1		T16	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T138	7		T222	11		T235	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T138	1		T55	1		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	10		T5	3		T16	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	8		T55	1		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T140	13		T214	1		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	5		T16	5		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T15	1		T36	1		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	9		T12	10		T14	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	21		T15	1		T218	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T165	1		T162	13		T19	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	11		T15	1		T26	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T150	1		T233	1		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T214	1		T29	1		T151	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T167	1		T235	3		T45	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T148	12		T44	1		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T8	25		T9	27		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	16		T148	10		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T233	10		T145	3		T243	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T223	11		T142	20		T282	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T271	8		T329	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T186	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	6		T138	6		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T138	7		T222	12		T235	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T231	13		T242	7		T157	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	12		T5	9		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	7		T213	2		T38	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T17	7		T153	12		T173	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	4		T16	2		T29	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T227	8		T237	2		T23	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	6		T12	10		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	22		T142	10		T231	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T162	10		T19	2		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T28	4		T29	9		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T150	10		T233	4		T162	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	8		T151	13		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T235	2		T45	13		T228	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T148	11		T19	4		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1102	1			T159	8		T230	21		T171	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T148	3		T150	13		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	7		T153	13		T162	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	13		T138	8		T222	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T138	1		T55	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	10		T214	1		T16	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T10	8		T55	1		T29	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	1		T140	1		T17	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	5		T14	1		T16	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T36	1		T172	1		T239	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	7		T12	11		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	23		T15	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T165	1		T19	4		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T14	1		T15	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T8	2		T9	3		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T214	1		T29	9		T151	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T55	1		T235	3		T45	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T14	1		T148	12		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T12	1		T50	1		T171	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T148	4		T223	12		T142	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T233	11		T284	14		T278	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T150	14		T44	1		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16690	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T235	7		T237	15		T49	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	16		T153	11		T224	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	9		T138	6		T222	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T139	11		T141	7		T155	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	2		T16	1		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	7		T38	7		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T140	12		T17	1		T224	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	4		T14	12		T16	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T172	9		T239	15		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	8		T12	9		T18	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	20		T26	6		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T19	1		T246	3		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	10		T141	10		T37	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T8	23		T9	24		T13	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T151	10		T276	13		T311	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T235	2		T45	13		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	15		T148	11		T19	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	2		T50	4		T171	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T148	9		T142	17		T221	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T284	10		T278	2		T330	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T264	1		T226	12		T328	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T36	6		T16	1		T259	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T235	4		T184	12		T92	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T50	1		T233	11		T145	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T223	12		T142	21		T217	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T36	1		T271	9		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T186	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	7		T138	7		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T138	8		T222	13		T235	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T138	1		T55	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	13		T5	10		T16	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	8		T55	1		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T140	1		T214	1		T17	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	5		T16	4		T29	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T15	1		T36	1		T227	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	7		T12	11		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	23		T15	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T165	1		T162	11		T19	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T14	1		T15	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T150	11		T233	5		T162	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T214	1		T29	9		T151	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T167	1		T235	3		T45	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T148	12		T44	1		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T8	2		T9	3		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T14	1		T148	4		T150	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T50	4		T243	11		T168	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T142	17		T264	4		T331	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T36	6		T329	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	16		T16	1		T153	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T138	6		T222	10		T235	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T139	11		T221	3		T157	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	9		T5	2		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	7		T141	7		T38	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T140	12		T17	1		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	4		T16	3		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T172	9		T168	11		T294	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	8		T12	9		T14	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	20		T218	11		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T162	12		T19	1		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	10		T26	6		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T162	13		T246	3		T182	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T151	10		T143	11		T155	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T235	2		T45	13		T228	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T148	11		T246	19		T221	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T8	23		T9	24		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	15		T148	9		T19	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40