Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20133

1

T2

20

T3

13

T5

71

auto[ADC_CTRL_FILTER_COND_OUT]

5788

1

T1

37

T6

52

T8

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19924

1

T1

15

T2

20

T3

13

auto[1]

5997

1

T1

22

T6

66

T8

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	251	1			T15	1		T50	5		T148	13
values[0]	81	1			T10	15		T151	24		T157	9
values[1]	768	1			T55	1		T258	1		T162	1
values[2]	792	1			T1	37		T138	1		T36	8
values[3]	843	1			T5	12		T16	3		T29	9
values[4]	738	1			T6	43		T14	13		T15	1
values[5]	720	1			T148	23		T30	22		T150	14
values[6]	624	1			T12	3		T138	7		T30	4
values[7]	526	1			T14	16		T138	14		T171	7
values[8]	759	1			T6	9		T26	7		T29	10
values[9]	3205	1			T6	23		T8	25		T9	27
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	779	1			T55	1		T36	1		T16	9
values[1]	2991	1			T1	37		T8	25		T9	27
values[2]	691	1			T5	12		T16	3		T44	1
values[3]	817	1			T6	43		T14	13		T15	1
values[4]	650	1			T138	7		T148	23		T30	22
values[5]	546	1			T12	3		T14	16		T138	14
values[6]	598	1			T171	7		T214	1		T26	7
values[7]	679	1			T6	9		T29	10		T165	1
values[8]	1075	1			T6	23		T12	20		T14	11
values[9]	115	1			T15	1		T140	13		T39	1
minimum	16980	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T36	1		T16	5		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T55	1		T16	2		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T138	1		T252	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1550	1			T1	19		T8	25		T9	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	3		T16	2		T228	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T44	1		T152	1		T38	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	1		T28	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	21		T14	13		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T148	12		T30	8		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T138	1		T252	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	3		T138	7		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	16		T141	8		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T171	3		T214	1		T26	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T19	3		T144	10		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T29	1		T165	1		T37	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	5		T167	1		T239	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T6	17		T12	10		T14	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T15	1		T55	2		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T15	1		T39	1		T277	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T140	13		T262	14		T273	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16567	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T276	10		T157	4		T318	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	2		T154	9		T235	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T28	9		T227	8		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T233	4		T162	11		T280	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1066	1			T1	18		T159	8		T230	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	9		T16	1		T228	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T38	14		T231	13		T254	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	10		T150	13		T233	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	22		T150	10		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T148	11		T30	14		T17	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T138	6		T162	4		T220	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T138	7		T30	2		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T173	14		T234	4		T157	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T171	4		T28	4		T29	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T19	2		T144	12		T260	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T29	9		T37	6		T225	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	4		T239	12		T182	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	6		T12	10		T148	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T223	11		T33	5		T19	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T277	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T273	1		T301	14		T336	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	1		T10	8		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T157	5		T318	12		T331	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T15	1		T50	5		T148	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T143	12		T274	1		T262	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T10	8		T151	11		T248	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T157	4		T318	11		T298	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T162	1		T217	1		T154	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T55	1		T258	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T138	1		T36	1		T16	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	19		T36	7		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	3		T16	2		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T29	1		T152	1		T38	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	1		T28	1		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	21		T14	13		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T148	12		T30	8		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T252	1		T152	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	3		T30	2		T162	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	1		T152	1		T246	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T138	7		T171	3		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	16		T141	8		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T26	7		T29	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	5		T19	3		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	17		T12	10		T14	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1663	1			T8	25		T9	27		T13	35
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T148	3		T18	4		T184	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T274	2		T247	9		T301	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T10	7		T151	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T157	5		T318	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T154	14		T235	6		T173	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T227	8		T222	12		T242	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	2		T233	4		T154	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	18		T28	9		T172	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	9		T16	1		T162	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T29	8		T38	14		T142	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	10		T233	10		T19	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	22		T150	10		T286	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T148	11		T30	14		T150	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T162	4		T220	7		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	2		T162	10		T220	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	6		T173	14		T234	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	7		T171	4		T28	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T144	12		T260	10		T244	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T29	9		T37	6		T225	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	4		T19	2		T239	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	6		T12	10		T182	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1097	1			T159	8		T230	21		T223	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T36	1		T16	4		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T55	1		T16	1		T28	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T138	1		T252	1		T233	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1413	1			T1	20		T8	2		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	10		T16	2		T228	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T44	1		T152	1		T38	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T15	1		T28	11		T150	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	23		T14	1		T150	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T148	12		T30	15		T17	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T138	7		T252	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T138	8		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	1		T141	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T171	5		T214	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T19	4		T144	13		T260	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T29	10		T165	1		T37	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	5		T167	1		T239	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	7		T12	11		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T15	1		T55	2		T223	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T15	1		T39	1		T277	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T140	1		T262	1		T273	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16734	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T276	1		T157	6		T318	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	3		T154	9		T235	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	1		T222	10		T275	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T162	13		T207	9		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1203	1			T1	17		T8	23		T9	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	2		T16	1		T228	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T38	7		T143	11		T155	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T155	3		T221	11		T172	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	20		T14	12		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T148	11		T30	7		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T246	11		T172	9		T224	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	2		T138	6		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T14	15		T141	7		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T171	2		T26	6		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	1		T144	9		T244	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T37	13		T246	3		T264	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	4		T239	15		T182	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	16		T12	9		T14	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T33	5		T218	11		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T277	2		T337	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T140	12		T262	13		T273	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T10	7		T151	10		T154	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T276	9		T157	3		T318	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T15	1		T50	1		T148	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T143	1		T274	3		T262	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T10	8		T151	14		T248	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T157	6		T318	13		T298	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T162	1		T217	1		T154	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T55	1		T258	1		T227	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T138	1		T36	1		T16	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	20		T36	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	10		T16	2		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T29	9		T152	1		T38	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	1		T28	11		T233	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	23		T14	1		T150	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T148	12		T30	15		T150	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T252	1		T152	1		T162	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	1		T30	3		T162	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	7		T152	1		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T138	8		T171	5		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	1		T141	1		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T26	1		T29	10		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	5		T19	4		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	7		T12	11		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1456	1			T8	2		T9	3		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T50	4		T148	9		T18	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T143	11		T262	13		T247	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T10	7		T151	10		T248	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T157	3		T318	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T154	10		T235	4		T239	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T222	10		T276	9		T275	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	3		T154	9		T207	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	17		T36	6		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	2		T16	1		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	7		T142	17		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T155	3		T172	5		T174	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	20		T14	12		T264	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T148	11		T30	7		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T155	12		T20	11		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	2		T30	1		T162	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T246	11		T224	8		T234	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T138	6		T171	2		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	15		T141	7		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T26	6		T37	13		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	4		T19	1		T239	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	16		T12	9		T14	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1304	1			T8	23		T9	24		T13	32

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40