Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	10		T12	11		T29	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	5		T14	1		T138	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T55	1		T30	3		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	8		T17	11		T151	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	13		T26	1		T28	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	1		T16	1		T151	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	1		T28	5		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T165	1		T38	10		T173	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T50	1		T55	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T1	7		T6	23		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T55	1		T139	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T152	1		T142	21		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T8	2		T9	3		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	1		T214	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T28	10		T165	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T30	15		T252	1		T37	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	7		T15	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T14	1		T138	1		T148	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T138	7		T38	6		T236	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T214	1		T229	12		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16616	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T157	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	2		T12	9		T154	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	4		T14	15		T138	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T30	1		T155	12		T20	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	7		T17	1		T151	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	9		T26	6		T33	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T16	1		T151	11		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T141	10		T153	10		T162	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T46	1		T261	11		T99	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T50	4		T245	12		T155	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T1	8		T6	20		T12	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T139	11		T19	1		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T142	17		T143	11		T246	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T8	23		T9	24		T13	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	12		T218	11		T45	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T235	4		T224	16		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T30	7		T37	13		T143	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	16		T143	2		T239	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T14	10		T148	9		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T38	7		T236	4		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T224	10		T48	4		T263	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T36	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T157	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T36	1		T236	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T251	12		T257	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	11		T29	9		T150	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	1		T138	8		T17	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	10		T55	1		T258	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	5		T10	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T26	1		T28	11		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	1		T16	1		T151	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	13		T15	1		T33	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T165	1		T152	1		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T50	1		T55	1		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T1	7		T6	23		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T214	1		T19	4		T227	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T16	4		T142	21		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T55	1		T148	12		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	1		T214	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T8	2		T9	3		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T30	15		T218	1		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T6	7		T15	1		T138	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T14	1		T138	1		T148	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T36	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	9		T154	10		T155	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	15		T138	6		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	2		T157	2		T264	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	4		T10	7		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	6		T30	1		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T16	1		T151	11		T244	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	9		T33	5		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T222	10		T46	1		T250	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T50	4		T245	12		T155	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	8		T6	20		T12	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T19	1		T244	14		T174	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T16	3		T142	17		T143	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T148	11		T139	11		T18	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	12		T45	13		T49	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T8	23		T9	24		T13	32
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T30	7		T218	11		T143	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	16		T38	7		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T14	10		T148	9		T171	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40