Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22536

1

T1

37

T2

20

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3385

1

T6

66

T10

15

T12

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20189

1

T1

15

T2

20

T3

13

auto[1]

5732

1

T1

22

T5

12

T6

66

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T265	16		-	-		-	-
values[0]	25	1			T99	17		T266	8		-	-
values[1]	880	1			T1	15		T6	9		T14	11
values[2]	643	1			T214	1		T28	11		T219	1
values[3]	737	1			T55	1		T214	1		T151	24
values[4]	2718	1			T1	22		T8	25		T9	27
values[5]	819	1			T5	12		T223	12		T16	2
values[6]	702	1			T12	20		T55	1		T139	12
values[7]	741	1			T6	23		T12	3		T14	13
values[8]	642	1			T6	43		T55	1		T214	1
values[9]	1384	1			T14	16		T15	1		T138	7
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1130	1			T6	9		T14	11		T50	5
values[1]	565	1			T55	1		T28	11		T18	20
values[2]	781	1			T10	15		T151	24		T141	18
values[3]	2724	1			T1	22		T8	25		T9	27
values[4]	791	1			T5	12		T12	20		T15	1
values[5]	702	1			T6	23		T15	1		T36	1
values[6]	620	1			T12	3		T14	13		T55	1
values[7]	846	1			T6	43		T138	7		T214	1
values[8]	949	1			T15	1		T140	13		T16	7
values[9]	159	1			T14	16		T267	1		T207	12
minimum	16654	1			T1	15		T2	20		T3	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T6	5		T50	5		T214	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T14	11		T150	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T55	1		T162	1		T143	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T28	1		T18	16		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T217	2		T220	2		T155	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	8		T151	11		T141	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T1	10		T8	25		T9	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	1		T152	1		T221	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	3		T12	10		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T55	1		T16	2		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	1		T36	1		T143	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	17		T139	12		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T36	7		T33	6		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	3		T14	13		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T214	1		T26	7		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	21		T138	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T15	1		T30	8		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T140	13		T16	5		T30	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T14	16		T267	1		T207	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T237	1		T268	1		T226	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16483	1			T1	9		T2	20		T3	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T269	1		T270	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T6	4		T233	12		T153	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T150	10		T155	1		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T157	5		T271	8		T272	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T28	10		T18	4		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T220	19		T239	11		T232	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	7		T151	13		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T1	12		T159	8		T138	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T29	9		T47	1		T273	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	9		T12	10		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T29	11		T17	7		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T155	11		T231	25		T173	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	6		T16	1		T274	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T33	5		T233	10		T38	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T148	11		T171	4		T28	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	8		T19	9		T154	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	22		T138	6		T213	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T30	14		T150	13		T142	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	2		T30	2		T38	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T207	2		T48	5		T275	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T237	2		T226	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	6		T5	1		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T269	12		T270	3		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T265	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T99	8		T266	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	9		T6	5		T50	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	11		T150	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T214	1		T143	12		T262	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T28	1		T219	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T55	1		T214	1		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T151	11		T141	18		T18	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T1	10		T8	25		T9	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	8		T29	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	3		T223	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T16	2		T17	5		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	10		T162	14		T245	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T55	1		T139	12		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	1		T36	8		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	17		T12	3		T14	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T214	1		T26	7		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	21		T55	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	446	1			T14	16		T15	1		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T138	1		T140	13		T16	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T99	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T1	6		T6	4		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T150	10		T178	6		T87	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T157	5		T271	8		T21	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T28	10		T155	1		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T220	10		T239	11		T244	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T151	13		T18	4		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T1	12		T159	8		T138	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T10	7		T29	9		T25	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	9		T223	11		T173	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	7		T151	14		T37	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	10		T162	11		T220	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	1		T29	11		T20	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T38	9		T144	12		T235	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	6		T148	11		T171	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T33	5		T233	10		T19	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	22		T28	9		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T29	8		T30	14		T150	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T138	6		T16	2		T38	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T6	5		T50	1		T214	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T14	1		T150	11		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T55	1		T162	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T28	11		T18	8		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T217	2		T220	21		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	8		T151	14		T141	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T1	13		T8	2		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T29	10		T152	1		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	10		T12	11		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T55	1		T16	1		T29	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	1		T36	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	7		T139	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T36	1		T33	6		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	1		T14	1		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T214	1		T26	1		T29	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	23		T138	7		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T15	1		T30	15		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T140	1		T16	4		T30	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T14	1		T267	1		T207	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T237	3		T268	1		T226	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16629	1			T1	7		T2	20		T3	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T269	13		T270	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	4		T50	4		T153	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	10		T155	3		T221	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T143	11		T246	3		T262	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T18	12		T234	11		T228	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T155	2		T239	11		T232	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	7		T151	10		T141	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T1	9		T8	23		T9	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T221	3		T248	2		T264	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	2		T12	9		T162	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	1		T17	1		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T143	11		T155	12		T248	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	16		T139	11		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T36	6		T33	5		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	2		T14	12		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T26	6		T19	5		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	20		T45	13		T239	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T30	7		T142	12		T172	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T140	12		T16	3		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T14	15		T207	9		T48	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T226	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T1	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T265	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T99	10		T266	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T1	7		T6	5		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	1		T150	11		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T214	1		T143	1		T262	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T28	11		T219	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T55	1		T214	1		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T151	14		T141	2		T18	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T1	13		T8	2		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T10	8		T29	10		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	10		T223	12		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T16	1		T17	11		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	11		T162	12		T245	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T55	1		T139	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	1		T36	2		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	7		T12	1		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T214	1		T26	1		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	23		T55	1		T28	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	442	1			T14	1		T15	1		T29	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T138	7		T140	1		T16	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T265	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T99	7		T266	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	8		T6	4		T50	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	10		T276	13		T21	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T143	11		T262	13		T276	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T155	3		T221	11		T234	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T155	2		T246	3		T239	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T151	10		T141	16		T18	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1163	1			T1	9		T8	23		T9	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	7		T248	2		T264	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	2		T246	11		T176	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	1		T17	1		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	9		T162	13		T245	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T139	11		T16	1		T218	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T36	6		T144	9		T235	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	16		T12	2		T14	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	6		T33	5		T19	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	20		T30	1		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T14	15		T30	7		T142	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T140	12		T16	3		T38	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40