Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22152

1

T1

15

T2

20

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3769

1

T1

22

T5

12

T6

43

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19672

1

T2

20

T3

13

T5

59

auto[1]

6249

1

T1

37

T5

12

T6

75

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	38	1			T217	1		T277	7		T278	15
values[0]	51	1			T271	9		T92	12		T279	19
values[1]	620	1			T6	23		T138	21		T36	7
values[2]	659	1			T1	22		T5	12		T138	1
values[3]	876	1			T10	15		T140	13		T214	1
values[4]	662	1			T1	15		T6	9		T15	1
values[5]	709	1			T6	43		T12	20		T14	13
values[6]	678	1			T14	11		T15	1		T26	7
values[7]	816	1			T214	1		T29	9		T150	11
values[8]	707	1			T55	1		T148	23		T217	1
values[9]	3491	1			T8	25		T9	27		T12	3
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	822	1			T1	22		T6	23		T138	7
values[1]	688	1			T5	12		T138	15		T55	1
values[2]	926	1			T15	1		T55	1		T140	13
values[3]	526	1			T6	9		T10	15		T12	20
values[4]	750	1			T1	15		T6	43		T15	1
values[5]	869	1			T14	11		T15	1		T29	10
values[6]	2784	1			T8	25		T9	27		T13	35
values[7]	847	1			T14	16		T55	1		T148	36
values[8]	788	1			T12	3		T50	5		T223	12
values[9]	279	1			T171	7		T150	14		T44	1
minimum	16642	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	17		T138	1		T36	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	10		T222	11		T235	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T138	1		T55	1		T139	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T5	3		T138	7		T214	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T55	1		T213	1		T258	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T15	1		T140	13		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	5		T10	8		T12	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T36	1		T172	10		T239	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	9		T214	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	21		T15	1		T26	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T150	1		T165	1		T37	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	11		T15	1		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1514	1			T8	25		T9	27		T13	35
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T214	1		T151	11		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T55	1		T28	1		T154	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T14	16		T148	22		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T12	3		T50	5		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T223	1		T142	18		T220	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T171	3		T165	1		T260	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T150	1		T44	1		T233	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T184	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	6		T138	6		T153	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	12		T222	12		T235	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T155	1		T242	7		T157	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	9		T138	7		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T213	2		T38	5		T280	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T29	11		T17	7		T227	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	4		T10	7		T12	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T239	12		T178	12		T23	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	6		T28	4		T18	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	22		T142	10		T182	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T150	10		T37	6		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T29	9		T30	2		T38	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T159	8		T230	21		T281	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T151	13		T227	8		T271	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T28	10		T154	14		T172	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T148	14		T29	8		T19	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T28	9		T30	14		T33	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T223	11		T142	20		T220	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T171	4		T260	10		T145	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T150	13		T233	10		T282	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T184	15		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T217	1		T277	4		T278	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T271	1		T92	12		T279	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	17		T138	1		T36	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	7		T222	11		T235	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T138	1		T55	1		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	10		T5	3		T16	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	8		T252	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T140	13		T214	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	9		T6	5		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	1		T36	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	10		T14	13		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	21		T15	1		T218	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T28	1		T165	1		T37	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	11		T15	1		T26	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T150	1		T233	1		T162	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T214	1		T29	1		T151	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T55	1		T167	1		T221	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T148	12		T217	1		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1729	1			T8	25		T9	27		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T14	16		T148	10		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T277	3		T278	8		T283	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T271	8		T279	9		T212	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T6	6		T138	6		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T138	7		T222	12		T235	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T231	13		T242	7		T157	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	12		T5	9		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	7		T213	2		T38	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T153	12		T178	12		T272	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	6		T6	4		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	11		T17	7		T227	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	10		T16	2		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	22		T142	10		T239	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T28	4		T37	6		T162	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T29	9		T30	2		T38	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T150	10		T233	4		T162	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	8		T151	13		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T235	2		T45	13		T228	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	11		T19	4		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T159	8		T230	21		T171	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T148	3		T223	11		T150	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	7		T138	7		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	13		T222	13		T235	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T138	1		T55	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	10		T138	8		T214	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T55	1		T213	3		T258	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T15	1		T140	1		T29	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	5		T10	8		T12	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T36	1		T172	1		T239	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	7		T214	1		T28	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	23		T15	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T150	11		T165	1		T37	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T14	1		T15	1		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T8	2		T9	3		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T214	1		T151	14		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T55	1		T28	11		T154	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	1		T148	16		T29	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	1		T50	1		T28	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T223	12		T142	21		T220	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T171	5		T165	1		T260	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T150	14		T44	1		T233	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T184	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	16		T36	6		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	9		T222	10		T235	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T139	11		T141	7		T155	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	2		T138	6		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T38	7		T224	10		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T140	12		T17	1		T272	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	4		T10	7		T12	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T172	9		T239	15		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	8		T18	12		T162	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	20		T26	6		T218	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	13		T246	3		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	10		T30	1		T141	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T8	23		T9	24		T13	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T151	10		T143	11		T276	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T154	10		T221	11		T172	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	15		T148	20		T19	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	2		T50	4		T30	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T142	17		T48	4		T264	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T171	2		T25	1		T284	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T264	1		T56	6		T226	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T184	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T217	1		T277	5		T278	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T271	9		T92	1		T279	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	7		T138	7		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T138	8		T222	13		T235	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T138	1		T55	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	13		T5	10		T16	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T10	8		T252	1		T213	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T140	1		T214	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	7		T6	5		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T15	1		T36	1		T29	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	11		T14	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	23		T15	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	5		T165	1		T37	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T14	1		T15	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T150	11		T233	5		T162	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T214	1		T29	9		T151	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T55	1		T167	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T148	12		T217	1		T19	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T8	2		T9	3		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T14	1		T148	4		T223	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T277	2		T278	2		T283	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T92	11		T279	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	16		T36	6		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T138	6		T222	10		T235	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T139	11		T221	3		T157	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	9		T5	2		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	7		T141	7		T38	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T140	12		T153	10		T272	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	8		T6	4		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	1		T172	9		T275	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	9		T14	12		T16	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	20		T218	11		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T37	13		T162	12		T19	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	10		T26	6		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T162	13		T246	3		T182	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T151	10		T143	11		T155	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T221	11		T235	2		T45	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T148	11		T246	19		T21	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T8	23		T9	24		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	15		T148	9		T142	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40