Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22005

1

T2

20

T3

13

T5

59

auto[ADC_CTRL_FILTER_COND_OUT]

3916

1

T1

37

T5

12

T6

66

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19668

1

T1

15

T2

20

T3

13

auto[1]

6253

1

T1

22

T6

9

T8

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	38	1			T89	33		T285	5		-	-
values[0]	81	1			T286	15		T287	14		T288	17
values[1]	573	1			T15	1		T36	7		T16	7
values[2]	2804	1			T6	9		T8	25		T9	27
values[3]	747	1			T1	15		T12	20		T148	13
values[4]	807	1			T1	22		T12	3		T138	14
values[5]	791	1			T6	43		T36	1		T223	12
values[6]	678	1			T14	13		T15	1		T55	1
values[7]	773	1			T50	5		T138	1		T150	11
values[8]	765	1			T14	16		T55	2		T16	3
values[9]	1250	1			T5	12		T6	23		T10	15
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	786	1			T14	11		T15	1		T36	7
values[1]	2918	1			T1	15		T6	9		T8	25
values[2]	666	1			T12	23		T138	14		T148	23
values[3]	815	1			T6	43		T36	1		T223	12
values[4]	748	1			T1	22		T14	13		T55	1
values[5]	682	1			T15	1		T50	5		T138	1
values[6]	897	1			T150	11		T44	1		T165	1
values[7]	723	1			T14	16		T138	7		T55	2
values[8]	850	1			T10	15		T28	11		T30	4
values[9]	202	1			T5	12		T6	23		T30	22
minimum	16634	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T15	1		T16	5		T213	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	11		T36	7		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T6	5		T8	25		T9	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	9		T142	18		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	10		T16	2		T17	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	3		T138	7		T148	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T162	13		T38	1		T246	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	21		T36	1		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T55	1		T28	1		T37	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	10		T14	13		T29	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T138	1		T214	2		T26	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	1		T50	5		T171	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T44	1		T165	1		T162	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T150	1		T142	13		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	16		T138	1		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T55	2		T141	10		T152	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T28	1		T151	12		T252	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	8		T30	2		T19	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T30	8		T262	14		T248	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T5	3		T6	17		T289	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16484	1			T2	20		T3	13		T5	58
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	2		T213	2		T172	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T233	18		T227	8		T235	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T6	4		T159	8		T148	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	6		T142	20		T19	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	10		T17	7		T207	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T138	7		T148	11		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T162	10		T38	9		T182	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	22		T223	11		T28	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T28	4		T37	6		T162	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	12		T29	17		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T153	24		T242	7		T290	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T171	4		T45	13		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T162	11		T154	16		T234	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T150	10		T142	10		T235	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T138	6		T16	1		T33	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T157	12		T244	14		T174	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	10		T151	14		T18	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	7		T30	2		T19	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T30	14		T253	12		T291	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T5	9		T6	6		T273	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T10	1		T74	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T89	13		T285	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T288	8		T292	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T286	1		T287	8		T293	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	1		T16	5		T213	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	7		T165	1		T233	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1523	1			T6	5		T8	25		T9	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	11		T214	1		T143	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	10		T148	10		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	9		T29	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T37	14		T162	13		T245	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	10		T12	3		T138	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T28	1		T162	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	21		T36	1		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T55	1		T214	2		T26	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	13		T15	1		T171	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T138	1		T153	12		T154	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T50	5		T150	1		T142	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	16		T16	2		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T55	2		T152	2		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T138	1		T28	1		T30	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T5	3		T6	17		T10	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T89	20		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T288	9		T292	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T286	14		T287	6		T293	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T16	2		T213	2		T228	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T233	18		T142	20		T227	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T6	4		T159	8		T230	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T19	2		T155	11		T228	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	10		T148	3		T17	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	6		T29	11		T19	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	6		T162	10		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	12		T138	7		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T28	4		T162	4		T220	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	22		T223	11		T28	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T153	12		T271	15		T290	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T171	4		T29	8		T45	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T153	12		T154	14		T272	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T150	10		T142	10		T235	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	1		T33	5		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T239	12		T157	12		T236	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T138	6		T28	10		T30	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T5	9		T6	6		T10	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	1		T16	4		T213	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	1		T36	1		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T6	5		T8	2		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T1	7		T142	21		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	11		T16	1		T17	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	1		T138	8		T148	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T162	11		T38	10		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T6	23		T36	1		T223	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T55	1		T28	5		T37	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	13		T14	1		T29	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	1		T214	2		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T15	1		T50	1		T171	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T44	1		T165	1		T162	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T150	11		T142	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T138	7		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T55	2		T141	1		T152	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T28	11		T151	15		T252	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T10	8		T30	3		T19	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T30	15		T262	1		T248	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T5	10		T6	7		T289	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16625	1			T2	20		T3	13		T5	59
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	3		T155	2		T246	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	10		T36	6		T143	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T6	4		T8	23		T9	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	8		T142	17		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	9		T16	1		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	2		T138	6		T148	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T162	12		T246	8		T182	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	20		T140	12		T38	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	13		T48	4		T275	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	9		T14	12		T151	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	6		T141	7		T153	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T50	4		T171	2		T224	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T162	13		T154	22		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T142	12		T143	11		T235	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	15		T16	1		T33	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T141	9		T157	14		T244	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T151	11		T18	12		T155	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	7		T30	1		T19	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T30	7		T262	13		T248	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T5	2		T6	16		T273	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T294	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T89	21		T285	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T288	10		T292	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T286	15		T287	7		T293	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T15	1		T16	4		T213	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T36	1		T165	1		T233	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T6	5		T8	2		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	1		T214	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	11		T148	4		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	7		T29	12		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	7		T162	11		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	13		T12	1		T138	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T28	5		T162	5		T220	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	23		T36	1		T223	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T55	1		T214	2		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T14	1		T15	1		T171	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T138	1		T153	13		T154	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T50	1		T150	11		T142	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	1		T16	2		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T55	2		T152	2		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T138	7		T28	11		T30	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T5	10		T6	7		T10	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T89	12		T285	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T288	7		T292	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T287	7		T293	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T16	3		T155	2		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	6		T142	17		T235	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T6	4		T8	23		T9	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	10		T143	11		T19	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	9		T148	9		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	8		T141	10		T235	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T37	13		T162	12		T245	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	9		T12	2		T138	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	4		T275	2		T295	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	20		T140	12		T151	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T26	6		T141	7		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	12		T171	2		T143	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T153	11		T154	10		T221	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T50	4		T142	12		T235	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	15		T16	1		T33	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T239	15		T157	14		T236	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T30	7		T151	11		T18	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T5	2		T6	16		T10	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40