Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20122

1

T2

20

T3

13

T5

71

auto[ADC_CTRL_FILTER_COND_OUT]

5799

1

T1

37

T6

52

T8

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19915

1

T1

15

T2

20

T3

13

auto[1]

6006

1

T1

22

T6

66

T8

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T15	1		T296	1		T297	3
values[0]	65	1			T10	15		T157	9		T298	1
values[1]	815	1			T55	1		T151	24		T258	1
values[2]	783	1			T1	37		T138	1		T36	8
values[3]	854	1			T16	3		T29	9		T252	1
values[4]	734	1			T5	12		T6	43		T14	13
values[5]	692	1			T148	23		T30	22		T150	14
values[6]	594	1			T12	3		T138	7		T30	4
values[7]	500	1			T14	16		T138	14		T171	7
values[8]	833	1			T6	9		T26	7		T29	10
values[9]	3432	1			T6	23		T8	25		T9	27
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1141	1			T10	15		T55	1		T36	1
values[1]	2979	1			T1	37		T8	25		T9	27
values[2]	650	1			T5	12		T16	3		T44	1
values[3]	823	1			T6	43		T14	13		T15	1
values[4]	660	1			T138	7		T148	23		T30	22
values[5]	545	1			T12	3		T14	16		T138	14
values[6]	620	1			T171	7		T214	1		T26	7
values[7]	700	1			T29	10		T165	1		T37	20
values[8]	1006	1			T6	32		T12	20		T14	11
values[9]	181	1			T140	13		T218	12		T39	1
minimum	16616	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T10	8		T36	1		T16	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T55	1		T28	1		T258	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T138	1		T252	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1533	1			T1	19		T8	25		T9	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	3		T16	2		T228	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T44	1		T152	1		T38	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	1		T28	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	21		T14	13		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T148	12		T30	8		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T138	1		T252	1		T152	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	3		T138	7		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	16		T173	1		T299	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T171	3		T214	1		T26	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T141	8		T19	3		T144	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T29	1		T165	1		T37	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T167	1		T239	16		T182	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T6	17		T12	10		T14	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	5		T15	1		T55	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T39	1		T35	3		T277	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T140	13		T218	12		T262	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16475	1			T2	20		T3	13		T5	58
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T10	7		T16	2		T151	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T28	9		T227	8		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T233	4		T162	11		T235	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1044	1			T1	18		T159	8		T230	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	9		T16	1		T228	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T38	14		T231	13		T21	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T28	10		T233	18		T19	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	22		T150	10		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T148	11		T30	14		T150	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T138	6		T162	4		T220	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T138	7		T30	2		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T173	14		T234	4		T157	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T171	4		T28	4		T29	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	2		T144	12		T260	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	9		T37	6		T225	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T239	12		T182	13		T253	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	6		T12	10		T148	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	4		T223	11		T33	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T35	2		T277	3		T300	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T273	1		T301	14		T302	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T15	1		T297	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T296	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T10	8		T87	8		T303	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T157	4		T298	1		T99	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T151	11		T162	1		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T55	1		T258	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T138	1		T36	1		T16	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	19		T36	7		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T16	2		T252	1		T162	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T29	1		T152	1		T38	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	3		T15	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	21		T14	13		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T148	12		T30	8		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T252	1		T152	1		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	3		T30	2		T153	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T138	1		T152	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T138	7		T171	3		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	16		T141	8		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T26	7		T29	1		T151	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	5		T19	3		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T6	17		T12	10		T14	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1715	1			T8	25		T9	27		T13	35
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T297	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T10	7		T87	8		T303	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T157	5		T99	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T151	13		T154	14		T235	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T227	8		T222	12		T242	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T16	2		T233	4		T154	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	18		T28	9		T172	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	1		T162	11		T280	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T29	8		T38	14		T142	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	9		T28	10		T17	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	22		T150	10		T286	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T148	11		T30	14		T150	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T220	7		T155	11		T20	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	2		T153	12		T162	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T138	6		T162	4		T173	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T138	7		T171	4		T28	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T144	12		T260	10		T244	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T29	9		T151	14		T37	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	4		T19	2		T239	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T6	6		T12	10		T148	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1124	1			T159	8		T230	21		T223	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T10	8		T36	1		T16	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T55	1		T28	10		T258	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T138	1		T252	1		T233	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1385	1			T1	20		T8	2		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	10		T16	2		T228	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	1		T152	1		T38	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	1		T28	11		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T6	23		T14	1		T150	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T148	12		T30	15		T150	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T138	7		T252	1		T152	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T138	8		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	1		T173	15		T299	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T171	5		T214	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T141	1		T19	4		T144	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T29	10		T165	1		T37	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T167	1		T239	13		T182	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T6	7		T12	11		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T6	5		T15	1		T55	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T39	1		T35	4		T277	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T140	1		T218	1		T262	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16616	1			T2	20		T3	13		T5	59
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T10	7		T16	3		T151	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T222	10		T276	9		T157	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T162	13		T235	4		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1192	1			T1	17		T8	23		T9	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	2		T16	1		T228	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T38	7		T143	11		T155	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T155	3		T172	5		T174	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	20		T14	12		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T148	11		T30	7		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T246	11		T172	9		T224	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	2		T138	6		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T14	15		T234	2		T157	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T171	2		T26	6		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T141	7		T19	1		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T37	13		T246	3		T264	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T239	15		T182	8		T89	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	16		T12	9		T14	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	4		T33	5		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T35	1		T277	2		T304	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T140	12		T218	11		T262	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T15	1		T297	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T296	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T10	8		T87	9		T303	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T157	6		T298	1		T99	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T151	14		T162	1		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T55	1		T258	1		T227	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T138	1		T36	1		T16	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T1	20		T36	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T16	2		T252	1		T162	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T29	9		T152	1		T38	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	10		T15	1		T28	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	23		T14	1		T150	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T148	12		T30	15		T150	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T252	1		T152	1		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	1		T30	3		T153	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T138	7		T152	1		T162	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	8		T171	5		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	1		T141	1		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T26	1		T29	10		T151	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	5		T19	4		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T6	7		T12	11		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1490	1			T8	2		T9	3		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T10	7		T87	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T157	3		T99	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T151	10		T154	10		T235	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T222	10		T276	9		T275	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	3		T154	9		T207	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	17		T36	6		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T16	1		T162	13		T232	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T38	7		T142	17		T155	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	2		T17	1		T155	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	20		T14	12		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T148	11		T30	7		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T155	12		T20	11		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	2		T30	1		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T246	11		T224	8		T234	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T138	6		T171	2		T142	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T14	15		T141	7		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T26	6		T151	11		T37	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	4		T19	1		T239	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	16		T12	9		T14	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1349	1			T8	23		T9	24		T13	32

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40