Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21879

1

T1

15

T2

20

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

4042

1

T1

22

T6

43

T10

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19705

1

T1

15

T2

20

T3

13

auto[1]

6216

1

T1

22

T6

9

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	388	1			T7	1		T10	5		T53	4
values[0]	58	1			T28	5		T152	1		T231	13
values[1]	715	1			T1	22		T15	1		T138	7
values[2]	3127	1			T8	25		T9	27		T13	35
values[3]	864	1			T12	20		T139	12		T26	7
values[4]	592	1			T15	1		T55	1		T214	1
values[5]	612	1			T1	15		T14	11		T55	1
values[6]	785	1			T6	52		T10	15		T50	5
values[7]	850	1			T5	12		T12	3		T14	13
values[8]	532	1			T233	20		T37	20		T152	1
values[9]	1161	1			T6	23		T14	16		T15	1
minimum	16237	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1040	1			T15	1		T138	7		T171	7
values[1]	3104	1			T1	22		T8	25		T9	27
values[2]	681	1			T139	12		T28	10		T150	14
values[3]	660	1			T15	1		T55	1		T223	12
values[4]	658	1			T1	15		T10	15		T14	11
values[5]	744	1			T6	9		T14	13		T50	5
values[6]	790	1			T5	12		T6	43		T12	3
values[7]	551	1			T14	16		T18	20		T37	20
values[8]	867	1			T15	1		T33	11		T151	26
values[9]	194	1			T6	23		T140	13		T173	15
minimum	16632	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	1		T138	1		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T171	3		T214	1		T28	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T8	25		T9	27		T13	35
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	10		T12	10		T16	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	1		T162	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T139	12		T150	1		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	1		T223	1		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T55	1		T213	1		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	9		T55	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	8		T14	11		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T6	5		T50	5		T148	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	13		T138	7		T245	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T5	3		T12	3		T17	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	21		T138	1		T233	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	16		T37	14		T38	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T18	16		T152	1		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T151	12		T165	1		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T15	1		T33	6		T222	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T6	17		T173	1		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T140	13		T232	14		T273	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16482	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T211	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T138	6		T29	9		T150	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T171	4		T28	14		T29	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T159	8		T230	21		T281	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T1	12		T12	10		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	9		T172	17		T286	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T150	13		T19	3		T236	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T223	11		T30	14		T38	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T213	2		T155	11		T145	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T1	6		T29	8		T244	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	7		T148	11		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T6	4		T148	3		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T138	7		T173	14		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	9		T17	7		T142	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T6	22		T233	18		T48	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T37	6		T38	5		T235	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T18	4		T19	4		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T151	14		T233	4		T154	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T33	5		T222	12		T182	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T6	6		T173	14		T309	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T232	12		T273	11		T305	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T10	1		T74	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T7	1		T10	5		T53	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T307	1		T193	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T28	1		T152	1		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	1		T138	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	10		T171	3		T214	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T8	25		T9	27		T13	35
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T16	5		T28	1		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T26	7		T28	1		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T12	10		T139	12		T218	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	1		T214	1		T30	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T55	1		T150	1		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	9		T55	1		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	11		T36	1		T151	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T6	5		T50	5		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	21		T10	8		T138	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T5	3		T12	3		T148	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	13		T138	1		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T37	14		T267	1		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T233	2		T152	1		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	17		T14	16		T151	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T15	1		T140	13		T33	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16096	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T310	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T307	10		T193	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T28	4		T231	12		T209	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	6		T150	10		T162	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	12		T171	4		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T159	8		T230	21		T29	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T16	2		T28	10		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T28	9		T162	10		T172	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	10		T19	3		T220	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T30	14		T38	9		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T150	13		T155	11		T157	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T1	6		T223	11		T29	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T151	13		T213	2		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	4		T16	1		T153	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	22		T10	7		T138	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	9		T148	3		T17	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T173	14		T178	12		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T37	6		T260	10		T172	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T233	18		T19	4		T234	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	6		T151	14		T233	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T33	5		T18	4		T222	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T15	1		T138	7		T29	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T171	5		T214	1		T28	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T8	2		T9	3		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T1	13		T12	11		T16	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	10		T162	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T139	1		T150	14		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	1		T223	12		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T55	1		T213	3		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	7		T55	1		T29	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	8		T14	1		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	5		T50	1		T148	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	1		T138	8		T245	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	10		T12	1		T17	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	23		T138	1		T233	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	1		T37	7		T38	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	8		T152	1		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T151	15		T165	1		T233	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T15	1		T33	6		T222	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T6	7		T173	15		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T140	1		T232	13		T273	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16623	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T211	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T162	13		T155	3		T246	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T171	2		T141	10		T154	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T8	23		T9	24		T13	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	9		T12	9		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T246	11		T172	17		T224	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T139	11		T19	4		T172	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T30	7		T221	3		T311	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T143	11		T155	12		T262	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	8		T244	10		T275	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	7		T14	10		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	4		T50	4		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	12		T138	6		T245	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	2		T12	2		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	20		T141	9		T143	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	15		T37	13		T38	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T18	12		T224	10		T234	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T151	11		T154	10		T157	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T33	5		T222	10		T182	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T6	16		T312	6		T265	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T140	12		T232	13		T273	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T46	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T211	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T7	1		T10	5		T53	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T307	11		T193	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T28	5		T152	1		T231	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	1		T138	7		T150	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	13		T171	5		T214	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T8	2		T9	3		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T16	4		T28	11		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T26	1		T28	10		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T12	11		T139	1		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	1		T214	1		T30	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T55	1		T150	14		T155	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	7		T55	1		T223	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	1		T36	1		T151	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	5		T50	1		T16	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	23		T10	8		T138	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	10		T12	1		T148	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T138	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	7		T267	1		T260	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T233	20		T152	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	7		T14	1		T151	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T15	1		T140	1		T33	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16237	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T310	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T193	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T209	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T162	13		T155	3		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	9		T171	2		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T8	23		T9	24		T13	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T16	3		T30	1		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T26	6		T162	12		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	9		T139	11		T218	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T30	7		T221	3		T224	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T155	12		T172	9		T157	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T1	8		T244	10		T225	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	10		T151	10		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	4		T50	4		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	20		T10	7		T138	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	2		T12	2		T148	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	12		T141	9		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	13		T172	5		T235	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T143	2		T234	9		T21	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	16		T14	15		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T140	12		T33	5		T18	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40