Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25921

1

T1

37

T2

20

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22138

1

T2

20

T3

13

T5

71

auto[ADC_CTRL_FILTER_COND_OUT]

3783

1

T1

37

T6

75

T10

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20043

1

T1

22

T2

20

T3

13

auto[1]

5878

1

T1

15

T5

12

T6

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21746

1

T1

19

T2

20

T3

13

auto[1]

4175

1

T1

18

T5

10

T6

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	154	1			T233	5		T162	1		T38	13
values[0]	12	1			T174	8		T306	4		-	-
values[1]	770	1			T1	22		T55	2		T218	12
values[2]	691	1			T6	9		T233	9		T166	1
values[3]	744	1			T5	12		T36	1		T213	3
values[4]	638	1			T10	15		T15	1		T214	1
values[5]	2854	1			T6	43		T8	25		T9	27
values[6]	798	1			T50	5		T55	1		T148	13
values[7]	808	1			T14	16		T139	12		T16	3
values[8]	650	1			T138	14		T36	7		T214	1
values[9]	1188	1			T1	15		T6	23		T12	23
minimum	16614	1			T2	20		T3	13		T5	59

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	717	1			T1	22		T218	12		T233	9
values[1]	680	1			T5	12		T6	9		T36	1
values[2]	742	1			T213	3		T152	1		T19	5
values[3]	2695	1			T8	25		T9	27		T10	15
values[4]	793	1			T6	43		T50	5		T55	1
values[5]	813	1			T148	13		T171	7		T214	1
values[6]	863	1			T14	16		T139	12		T16	3
values[7]	632	1			T138	22		T36	7		T214	1
values[8]	933	1			T1	15		T6	23		T12	23
values[9]	177	1			T14	13		T18	20		T38	1
minimum	16876	1			T2	20		T3	13		T5	59

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

4211

1

T1

17

T5

2

T6

40

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T233	1		T167	1		T20	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	10		T218	12		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T36	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	5		T153	11		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T213	1		T221	4		T235	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T152	1		T19	1		T224	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T8	25		T9	27		T13	35
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	8		T28	2		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T50	5		T55	1		T148	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	21		T140	13		T165	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T148	10		T30	2		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T171	3		T214	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T14	16		T17	5		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T139	12		T16	2		T29	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T36	7		T141	11		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T138	9		T214	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	10		T26	7		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T1	9		T6	17		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T14	13		T38	1		T19	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T18	16		T215	1		T313	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16541	1			T2	20		T3	13		T5	58
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T55	1		T151	11		T235	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T233	8		T20	8		T157	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	12		T23	3		T184	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	9		T232	12		T21	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	4		T153	12		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T213	2		T235	2		T182	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T19	4		T47	1		T275	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T159	8		T230	21		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	7		T28	13		T150	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T148	11		T30	14		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	22		T280	6		T239	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T148	3		T30	2		T33	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T171	4		T150	10		T38	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T17	7		T162	10		T229	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	1		T29	19		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T231	13		T242	7		T182	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T138	13		T162	4		T274	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	10		T29	9		T234	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	6		T6	6		T223	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T19	3		T220	9		T154	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T18	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T10	1		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T151	13		T235	6		T234	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T154	10		T155	3		T234	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T233	1		T162	1		T38	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T174	4		T306	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T55	1		T220	1		T20	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	10		T55	1		T218	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T233	1		T167	1		T299	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T6	5		T166	1		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	3		T36	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T152	1		T153	11		T19	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	1		T214	1		T16	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	8		T28	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T8	25		T9	27		T13	35
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	21		T28	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T50	5		T55	1		T148	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T171	3		T140	13		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T14	16		T33	6		T17	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T139	12		T16	2		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T36	7		T141	11		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T138	7		T214	1		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T12	10		T14	13		T26	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T1	9		T6	17		T12	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T2	20		T3	13		T5	58
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T154	9		T234	2		T305	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T233	4		T38	5		T309	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T174	4		T306	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T220	7		T20	8		T173	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	12		T151	13		T235	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T233	8		T232	12		T21	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	4		T155	11		T260	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	9		T213	2		T48	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T153	12		T19	4		T47	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T16	2		T153	12		T19	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	7		T28	9		T150	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T159	8		T148	11		T230	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	22		T28	4		T280	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T148	3		T30	16		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T171	4		T150	10		T144	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T33	5		T17	7		T162	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T16	1		T29	8		T38	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T231	13		T174	11		T215	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T138	7		T29	11		T162	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T12	10		T29	9		T19	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	6		T6	6		T138	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T74	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T233	9		T167	1		T20	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T1	13		T218	1		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	10		T36	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	5		T153	13		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T213	3		T221	1		T235	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T152	1		T19	5		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T8	2		T9	3		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	8		T28	15		T150	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T50	1		T55	1		T148	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	23		T140	1		T165	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T148	4		T30	3		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T171	5		T214	1		T150	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	1		T17	11		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T139	1		T16	2		T29	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	1		T141	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T138	16		T214	1		T162	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	11		T26	1		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	7		T6	7		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T14	1		T38	1		T19	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T18	8		T215	1		T313	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T2	20		T3	13		T5	59
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T55	1		T151	14		T235	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T20	11		T157	2		T275	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	9		T218	11		T264	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	2		T232	13		T264	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	4		T153	10		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T221	3		T235	2		T224	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T224	8		T275	12		T85	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1085	1			T8	23		T9	24		T13	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	7		T162	13		T207	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T50	4		T148	11		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	20		T140	12		T239	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T148	9		T30	1		T33	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T171	2		T143	2		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T14	15		T17	1		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T139	11		T16	1		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T36	6		T141	10		T143	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T138	6		T247	11		T259	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	9		T26	6		T141	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	8		T6	16		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T14	12		T19	4		T154	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T18	12		T313	4		T92	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T174	3		T254	8		T89	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T151	10		T235	4		T234	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T154	10		T155	1		T234	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T233	5		T162	1		T38	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T174	5		T306	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	1		T220	8		T20	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	13		T55	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T233	9		T167	1		T299	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	5		T166	1		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T5	10		T36	1		T213	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T152	1		T153	13		T19	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	1		T214	1		T16	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	8		T28	10		T150	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T8	2		T9	3		T13	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	23		T28	5		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T50	1		T55	1		T148	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T171	5		T140	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	1		T33	6		T17	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T139	1		T16	2		T29	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T36	1		T141	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	8		T214	1		T29	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T12	11		T14	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T1	7		T6	7		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16614	1			T2	20		T3	13		T5	59
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T154	9		T155	2		T234	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T38	7		T248	3		T185	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T174	3		T306	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T20	11		T157	2		T275	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	9		T218	11		T151	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T232	13		T264	3		T21	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	4		T155	12		T246	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	2		T48	4		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T153	10		T224	8		T244	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T16	3		T153	11		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	7		T162	13		T207	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T8	23		T9	24		T13	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	20		T239	11		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T50	4		T148	9		T30	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T171	2		T140	12		T143	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	15		T33	5		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T139	11		T16	1		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T36	6		T141	10		T143	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T138	6		T247	11		T215	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	9		T14	12		T26	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T1	8		T6	16		T12	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21710

1

T1

20

T2

20

T3

13

auto[1]

auto[0]

4211

1

T1

17

T5

2

T6

40