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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.92


Total test records in report: 919
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T797 /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3875847707 Aug 03 05:32:57 PM PDT 24 Aug 03 05:34:18 PM PDT 24 27004282386 ps
T798 /workspace/coverage/default/10.adc_ctrl_stress_all.3688883811 Aug 03 05:29:05 PM PDT 24 Aug 03 05:33:04 PM PDT 24 376346213882 ps
T799 /workspace/coverage/default/46.adc_ctrl_alert_test.263415920 Aug 03 05:33:19 PM PDT 24 Aug 03 05:33:20 PM PDT 24 360434066 ps
T800 /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1348112213 Aug 03 05:33:32 PM PDT 24 Aug 03 05:49:02 PM PDT 24 386101975987 ps
T60 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4149780153 Aug 03 04:26:39 PM PDT 24 Aug 03 04:26:43 PM PDT 24 1914907944 ps
T131 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2568494913 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:43 PM PDT 24 2073991918 ps
T801 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2800823222 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:38 PM PDT 24 329400647 ps
T132 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3208878709 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:47 PM PDT 24 461056461 ps
T64 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2128262170 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:48 PM PDT 24 926990780 ps
T57 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.171687694 Aug 03 04:26:35 PM PDT 24 Aug 03 04:26:39 PM PDT 24 5380707765 ps
T802 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2762334949 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:48 PM PDT 24 414368594 ps
T133 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.939303996 Aug 03 04:26:49 PM PDT 24 Aug 03 04:26:50 PM PDT 24 360136867 ps
T116 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2816502260 Aug 03 04:26:40 PM PDT 24 Aug 03 04:26:41 PM PDT 24 521863909 ps
T58 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3886184974 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:48 PM PDT 24 4702637678 ps
T59 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1268977614 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:56 PM PDT 24 4191836625 ps
T65 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2497081158 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:40 PM PDT 24 538031390 ps
T803 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.574648936 Aug 03 04:26:43 PM PDT 24 Aug 03 04:26:44 PM PDT 24 391868593 ps
T61 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.979014577 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:51 PM PDT 24 4216236401 ps
T62 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.467799537 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:38 PM PDT 24 4133562127 ps
T63 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1108942896 Aug 03 04:26:40 PM PDT 24 Aug 03 04:26:44 PM PDT 24 4027906478 ps
T134 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1995340655 Aug 03 04:26:27 PM PDT 24 Aug 03 04:26:28 PM PDT 24 439047353 ps
T66 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2638686517 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:32 PM PDT 24 4137400214 ps
T804 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1953909344 Aug 03 04:26:50 PM PDT 24 Aug 03 04:26:51 PM PDT 24 361573456 ps
T805 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.39528184 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:39 PM PDT 24 400894043 ps
T135 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.865842057 Aug 03 04:26:22 PM PDT 24 Aug 03 04:26:25 PM PDT 24 4397717316 ps
T806 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2144253135 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:36 PM PDT 24 516603844 ps
T67 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.570449480 Aug 03 04:26:43 PM PDT 24 Aug 03 04:26:49 PM PDT 24 4007643864 ps
T807 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2220996490 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:31 PM PDT 24 1183545437 ps
T84 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1973949439 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:45 PM PDT 24 594903516 ps
T808 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4227995692 Aug 03 04:26:48 PM PDT 24 Aug 03 04:26:50 PM PDT 24 386279379 ps
T809 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2225675858 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:45 PM PDT 24 544128607 ps
T810 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3966652483 Aug 03 04:26:48 PM PDT 24 Aug 03 04:26:49 PM PDT 24 543861935 ps
T71 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3319556631 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:39 PM PDT 24 475613120 ps
T811 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.60243506 Aug 03 04:26:48 PM PDT 24 Aug 03 04:26:50 PM PDT 24 522580428 ps
T72 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3448200101 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:38 PM PDT 24 480427078 ps
T812 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.511282016 Aug 03 04:26:42 PM PDT 24 Aug 03 04:26:43 PM PDT 24 453955071 ps
T813 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3277109397 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:29 PM PDT 24 573332174 ps
T814 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1161908020 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:46 PM PDT 24 360499514 ps
T73 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3329424178 Aug 03 04:26:39 PM PDT 24 Aug 03 04:26:41 PM PDT 24 685120770 ps
T815 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3185343930 Aug 03 04:26:48 PM PDT 24 Aug 03 04:26:50 PM PDT 24 523527708 ps
T75 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.267542208 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:40 PM PDT 24 540564992 ps
T816 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.88903456 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:47 PM PDT 24 1970060740 ps
T68 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2884823007 Aug 03 04:26:41 PM PDT 24 Aug 03 04:26:47 PM PDT 24 8448710590 ps
T817 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2016353115 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:46 PM PDT 24 418645477 ps
T117 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1683471775 Aug 03 04:26:20 PM PDT 24 Aug 03 04:26:22 PM PDT 24 1301319488 ps
T818 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1512649559 Aug 03 04:26:29 PM PDT 24 Aug 03 04:26:30 PM PDT 24 1234859038 ps
T819 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2515672997 Aug 03 04:26:31 PM PDT 24 Aug 03 04:26:32 PM PDT 24 473502385 ps
T820 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2762688436 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:47 PM PDT 24 393650055 ps
T821 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3470833252 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:48 PM PDT 24 409304491 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1480984231 Aug 03 04:26:32 PM PDT 24 Aug 03 04:26:33 PM PDT 24 747034886 ps
T119 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3772284471 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:31 PM PDT 24 1283715540 ps
T822 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3100617102 Aug 03 04:26:30 PM PDT 24 Aug 03 04:26:34 PM PDT 24 887032137 ps
T823 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1756541000 Aug 03 04:26:40 PM PDT 24 Aug 03 04:26:56 PM PDT 24 4113232070 ps
T103 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.181782982 Aug 03 04:26:29 PM PDT 24 Aug 03 04:26:42 PM PDT 24 4500454022 ps
T104 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2684489836 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:29 PM PDT 24 531377730 ps
T120 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4287233176 Aug 03 04:26:32 PM PDT 24 Aug 03 04:27:18 PM PDT 24 42316491373 ps
T824 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1049069586 Aug 03 04:26:40 PM PDT 24 Aug 03 04:27:04 PM PDT 24 8767448590 ps
T825 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3594281827 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:29 PM PDT 24 1195212806 ps
T95 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3882815709 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:38 PM PDT 24 372995029 ps
T826 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1808262431 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:47 PM PDT 24 477862877 ps
T827 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.740085807 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:40 PM PDT 24 1647190737 ps
T828 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2313482989 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:40 PM PDT 24 387381269 ps
T340 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2511851316 Aug 03 04:26:43 PM PDT 24 Aug 03 04:27:05 PM PDT 24 8449012233 ps
T829 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2300514618 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:50 PM PDT 24 5531692959 ps
T830 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1816412765 Aug 03 04:26:43 PM PDT 24 Aug 03 04:26:44 PM PDT 24 372751016 ps
T341 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2433505685 Aug 03 04:26:40 PM PDT 24 Aug 03 04:26:45 PM PDT 24 4908530301 ps
T831 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2834340497 Aug 03 04:26:35 PM PDT 24 Aug 03 04:26:36 PM PDT 24 445971474 ps
T832 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3956229250 Aug 03 04:26:51 PM PDT 24 Aug 03 04:27:08 PM PDT 24 5075196182 ps
T833 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4167072328 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:46 PM PDT 24 571107668 ps
T338 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4128231967 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:47 PM PDT 24 4102481074 ps
T121 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.310380817 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:32 PM PDT 24 1032396359 ps
T834 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.128349679 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:45 PM PDT 24 471662325 ps
T835 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4183616791 Aug 03 04:26:42 PM PDT 24 Aug 03 04:26:43 PM PDT 24 393565055 ps
T339 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.401492636 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:47 PM PDT 24 4179902902 ps
T836 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.509678473 Aug 03 04:26:32 PM PDT 24 Aug 03 04:27:00 PM PDT 24 26261416093 ps
T837 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1059985170 Aug 03 04:26:39 PM PDT 24 Aug 03 04:26:40 PM PDT 24 448748982 ps
T79 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.564724932 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:50 PM PDT 24 4110177116 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1548917154 Aug 03 04:26:30 PM PDT 24 Aug 03 04:26:31 PM PDT 24 342850822 ps
T839 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1554273104 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:39 PM PDT 24 495442136 ps
T122 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3305667166 Aug 03 04:26:29 PM PDT 24 Aug 03 04:26:50 PM PDT 24 25874821827 ps
T840 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.696667292 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:40 PM PDT 24 633011443 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.699080024 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:39 PM PDT 24 502153004 ps
T842 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2977101269 Aug 03 04:26:33 PM PDT 24 Aug 03 04:26:37 PM PDT 24 4850264087 ps
T843 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.708404812 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:40 PM PDT 24 539261894 ps
T844 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2560530414 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:38 PM PDT 24 410778344 ps
T845 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2170894855 Aug 03 04:26:43 PM PDT 24 Aug 03 04:26:44 PM PDT 24 314489917 ps
T846 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3384717395 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:39 PM PDT 24 646969948 ps
T847 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3179034101 Aug 03 04:26:42 PM PDT 24 Aug 03 04:26:43 PM PDT 24 368204226 ps
T848 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3379233267 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:30 PM PDT 24 603263259 ps
T849 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3680303644 Aug 03 04:26:43 PM PDT 24 Aug 03 04:26:45 PM PDT 24 410473688 ps
T850 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2963668715 Aug 03 04:26:22 PM PDT 24 Aug 03 04:26:24 PM PDT 24 530749353 ps
T851 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.933419798 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:47 PM PDT 24 494469985 ps
T852 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3848010052 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:48 PM PDT 24 516664996 ps
T853 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3178157359 Aug 03 04:26:31 PM PDT 24 Aug 03 04:26:32 PM PDT 24 500631094 ps
T854 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3518562797 Aug 03 04:26:31 PM PDT 24 Aug 03 04:26:32 PM PDT 24 545863145 ps
T855 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2299917711 Aug 03 04:26:56 PM PDT 24 Aug 03 04:26:58 PM PDT 24 422567216 ps
T856 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.917254961 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:38 PM PDT 24 495857852 ps
T857 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2957922091 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:47 PM PDT 24 279218647 ps
T858 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.429241646 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:38 PM PDT 24 418341879 ps
T859 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2353214623 Aug 03 04:26:40 PM PDT 24 Aug 03 04:26:45 PM PDT 24 2434465247 ps
T860 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.373556565 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:39 PM PDT 24 528683098 ps
T861 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2559329968 Aug 03 04:26:30 PM PDT 24 Aug 03 04:26:32 PM PDT 24 378830012 ps
T862 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1784262576 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:46 PM PDT 24 497714451 ps
T863 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.241283725 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:37 PM PDT 24 317788582 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.870571613 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:47 PM PDT 24 344726959 ps
T865 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2256643805 Aug 03 04:26:40 PM PDT 24 Aug 03 04:26:43 PM PDT 24 2131604723 ps
T866 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.653302824 Aug 03 04:26:50 PM PDT 24 Aug 03 04:26:52 PM PDT 24 437996811 ps
T867 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1616961185 Aug 03 04:26:40 PM PDT 24 Aug 03 04:26:47 PM PDT 24 8585740070 ps
T868 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1131082599 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:46 PM PDT 24 529142237 ps
T123 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.328913803 Aug 03 04:26:20 PM PDT 24 Aug 03 04:26:22 PM PDT 24 415825538 ps
T124 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.513583762 Aug 03 04:26:42 PM PDT 24 Aug 03 04:26:43 PM PDT 24 978806420 ps
T869 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1432013345 Aug 03 04:26:55 PM PDT 24 Aug 03 04:26:56 PM PDT 24 526328810 ps
T870 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3687335168 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:39 PM PDT 24 1250043171 ps
T871 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1376193579 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:47 PM PDT 24 405133691 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3324370615 Aug 03 04:26:24 PM PDT 24 Aug 03 04:26:26 PM PDT 24 496835305 ps
T873 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3610220479 Aug 03 04:26:43 PM PDT 24 Aug 03 04:26:44 PM PDT 24 314698845 ps
T125 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1086528178 Aug 03 04:26:28 PM PDT 24 Aug 03 04:27:15 PM PDT 24 9130156200 ps
T874 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2115272438 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:56 PM PDT 24 8252185990 ps
T875 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.50371537 Aug 03 04:26:56 PM PDT 24 Aug 03 04:26:57 PM PDT 24 547478786 ps
T876 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3441897508 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:46 PM PDT 24 378970363 ps
T877 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3258571318 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:49 PM PDT 24 510388230 ps
T878 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3887941981 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:37 PM PDT 24 508693285 ps
T879 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4065529968 Aug 03 04:26:56 PM PDT 24 Aug 03 04:26:57 PM PDT 24 412688864 ps
T880 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3052832763 Aug 03 04:26:20 PM PDT 24 Aug 03 04:26:42 PM PDT 24 8747645541 ps
T881 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1226356080 Aug 03 04:26:40 PM PDT 24 Aug 03 04:26:41 PM PDT 24 720508056 ps
T882 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.854985896 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:51 PM PDT 24 5056114837 ps
T883 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3912982541 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:38 PM PDT 24 458069026 ps
T884 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.464940352 Aug 03 04:26:38 PM PDT 24 Aug 03 04:26:42 PM PDT 24 4826933143 ps
T80 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2591626223 Aug 03 04:26:30 PM PDT 24 Aug 03 04:26:52 PM PDT 24 8489840554 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2085605828 Aug 03 04:26:29 PM PDT 24 Aug 03 04:26:31 PM PDT 24 457975522 ps
T886 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1847598804 Aug 03 04:26:51 PM PDT 24 Aug 03 04:26:55 PM PDT 24 4311898996 ps
T887 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2659303820 Aug 03 04:26:42 PM PDT 24 Aug 03 04:26:44 PM PDT 24 4088939610 ps
T888 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4063630411 Aug 03 04:26:44 PM PDT 24 Aug 03 04:26:47 PM PDT 24 651257711 ps
T889 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3562191496 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:47 PM PDT 24 416725508 ps
T890 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2085400392 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:42 PM PDT 24 2209796095 ps
T891 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.339985460 Aug 03 04:26:30 PM PDT 24 Aug 03 04:26:32 PM PDT 24 433371225 ps
T126 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2449566272 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:48 PM PDT 24 468835470 ps
T892 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2550303981 Aug 03 04:26:30 PM PDT 24 Aug 03 04:26:35 PM PDT 24 2006179395 ps
T127 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4083633298 Aug 03 04:26:39 PM PDT 24 Aug 03 04:26:40 PM PDT 24 414324905 ps
T893 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4020933189 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:37 PM PDT 24 600182887 ps
T128 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.806399973 Aug 03 04:26:42 PM PDT 24 Aug 03 04:26:43 PM PDT 24 502815819 ps
T894 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.647136912 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:47 PM PDT 24 417895280 ps
T895 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.97145126 Aug 03 04:26:35 PM PDT 24 Aug 03 04:26:39 PM PDT 24 406906406 ps
T896 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3147874378 Aug 03 04:26:48 PM PDT 24 Aug 03 04:26:51 PM PDT 24 1284604089 ps
T897 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1115010523 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:51 PM PDT 24 4445121502 ps
T129 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.447413452 Aug 03 04:26:24 PM PDT 24 Aug 03 04:26:27 PM PDT 24 629891994 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1965565692 Aug 03 04:26:21 PM PDT 24 Aug 03 04:26:59 PM PDT 24 44462146317 ps
T899 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1876028322 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:39 PM PDT 24 432882674 ps
T900 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.504092428 Aug 03 04:26:55 PM PDT 24 Aug 03 04:26:56 PM PDT 24 562193935 ps
T901 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.348417084 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:49 PM PDT 24 503001955 ps
T902 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2750714583 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:39 PM PDT 24 447993565 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3302652880 Aug 03 04:26:31 PM PDT 24 Aug 03 04:26:33 PM PDT 24 1778683939 ps
T904 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2396078315 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:49 PM PDT 24 469707324 ps
T905 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2499222323 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:48 PM PDT 24 463015225 ps
T130 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3184158329 Aug 03 04:26:35 PM PDT 24 Aug 03 04:26:37 PM PDT 24 346347897 ps
T906 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.633655478 Aug 03 04:26:46 PM PDT 24 Aug 03 04:26:47 PM PDT 24 509895530 ps
T907 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2740974946 Aug 03 04:26:50 PM PDT 24 Aug 03 04:26:52 PM PDT 24 448458976 ps
T908 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3826261069 Aug 03 04:26:31 PM PDT 24 Aug 03 04:26:33 PM PDT 24 365540549 ps
T909 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4040370783 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:48 PM PDT 24 356480760 ps
T910 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1694086551 Aug 03 04:26:37 PM PDT 24 Aug 03 04:26:38 PM PDT 24 366749256 ps
T911 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2703196842 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:48 PM PDT 24 311862289 ps
T912 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1803754240 Aug 03 04:26:28 PM PDT 24 Aug 03 04:26:30 PM PDT 24 325606023 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1957639916 Aug 03 04:26:30 PM PDT 24 Aug 03 04:26:34 PM PDT 24 515918254 ps
T914 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3239745777 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:57 PM PDT 24 4254823449 ps
T915 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2501872217 Aug 03 04:26:45 PM PDT 24 Aug 03 04:26:47 PM PDT 24 351821896 ps
T916 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4242393179 Aug 03 04:26:36 PM PDT 24 Aug 03 04:26:38 PM PDT 24 522263790 ps
T917 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2044492341 Aug 03 04:26:29 PM PDT 24 Aug 03 04:26:30 PM PDT 24 352307979 ps
T918 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2202999870 Aug 03 04:26:21 PM PDT 24 Aug 03 04:26:23 PM PDT 24 369609301 ps
T919 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2836324647 Aug 03 04:26:47 PM PDT 24 Aug 03 04:26:48 PM PDT 24 405010662 ps

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2324404962
Short name T10
Test name
Test status
Simulation time 301734646377 ps
CPU time 661.78 seconds
Started Aug 03 05:30:01 PM PDT 24
Finished Aug 03 05:41:03 PM PDT 24
Peak memory 210032 kb
Host smart-b9921a30-ed94-45f5-9723-eb4293b5e63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324404962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2324404962
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.162329911
Short name T14
Test name
Test status
Simulation time 544442281400 ps
CPU time 213.02 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:32:37 PM PDT 24
Peak memory 201468 kb
Host smart-952ac559-edb4-4d87-b5c2-08e72493c7b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162329911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.162329911
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1491979494
Short name T19
Test name
Test status
Simulation time 245232847507 ps
CPU time 193.71 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:31:50 PM PDT 24
Peak memory 210092 kb
Host smart-01ea83a7-47ed-424c-8af0-f26ea6a2b872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491979494 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1491979494
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2918931593
Short name T55
Test name
Test status
Simulation time 669935105275 ps
CPU time 583.11 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:38:13 PM PDT 24
Peak memory 210020 kb
Host smart-1e99a3f7-95d7-4206-b973-4bca7c705da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918931593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2918931593
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3611860120
Short name T162
Test name
Test status
Simulation time 684227710586 ps
CPU time 448.9 seconds
Started Aug 03 05:29:52 PM PDT 24
Finished Aug 03 05:37:21 PM PDT 24
Peak memory 201452 kb
Host smart-7b277155-7dc2-4cdd-adca-470b0b517812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611860120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3611860120
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1176872775
Short name T6
Test name
Test status
Simulation time 589652303537 ps
CPU time 370.41 seconds
Started Aug 03 05:32:05 PM PDT 24
Finished Aug 03 05:38:15 PM PDT 24
Peak memory 201364 kb
Host smart-ed105d16-5fbc-4b80-a9c7-ec346607f05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176872775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1176872775
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3887270119
Short name T154
Test name
Test status
Simulation time 535507484714 ps
CPU time 1289.29 seconds
Started Aug 03 05:28:28 PM PDT 24
Finished Aug 03 05:49:58 PM PDT 24
Peak memory 201412 kb
Host smart-b76dd866-28c8-409b-ba55-149aab7cea2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887270119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3887270119
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2646232162
Short name T155
Test name
Test status
Simulation time 632957049064 ps
CPU time 263.83 seconds
Started Aug 03 05:31:21 PM PDT 24
Finished Aug 03 05:35:45 PM PDT 24
Peak memory 201424 kb
Host smart-a926638c-5803-46d3-800a-68b0cd506502
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646232162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2646232162
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2497081158
Short name T65
Test name
Test status
Simulation time 538031390 ps
CPU time 2.04 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:40 PM PDT 24
Peak memory 201460 kb
Host smart-adb1744a-34c6-411e-9728-9ca5acfece1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497081158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2497081158
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.52993596
Short name T16
Test name
Test status
Simulation time 189334140197 ps
CPU time 153.31 seconds
Started Aug 03 05:32:25 PM PDT 24
Finished Aug 03 05:34:59 PM PDT 24
Peak memory 210232 kb
Host smart-7aa56da2-f360-4daa-8334-c3e8a1d747a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52993596 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.52993596
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3668725151
Short name T235
Test name
Test status
Simulation time 589045199311 ps
CPU time 1070.06 seconds
Started Aug 03 05:30:52 PM PDT 24
Finished Aug 03 05:48:42 PM PDT 24
Peak memory 201500 kb
Host smart-3a46b3c1-a0e8-42b5-8611-4601667ad2a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668725151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3668725151
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2149263060
Short name T69
Test name
Test status
Simulation time 4355243792 ps
CPU time 6.04 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:28:42 PM PDT 24
Peak memory 217140 kb
Host smart-98ea60d4-aa4c-40c2-82f7-e6e3b0212d8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149263060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2149263060
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.358033374
Short name T148
Test name
Test status
Simulation time 367128891156 ps
CPU time 414.19 seconds
Started Aug 03 05:29:17 PM PDT 24
Finished Aug 03 05:36:11 PM PDT 24
Peak memory 201408 kb
Host smart-b5e0b868-0e19-4914-b3b2-81a8db976385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358033374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.358033374
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.830599303
Short name T157
Test name
Test status
Simulation time 494521204790 ps
CPU time 1092.19 seconds
Started Aug 03 05:29:58 PM PDT 24
Finished Aug 03 05:48:11 PM PDT 24
Peak memory 201440 kb
Host smart-5f64d9a7-be8a-4570-b75c-07a1f48c26ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830599303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.830599303
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2507895678
Short name T273
Test name
Test status
Simulation time 512589817250 ps
CPU time 303.02 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:33:43 PM PDT 24
Peak memory 201396 kb
Host smart-7b7c0b59-ef5e-40e7-ae29-4f721c797326
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507895678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2507895678
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.560099910
Short name T36
Test name
Test status
Simulation time 417040880444 ps
CPU time 206.59 seconds
Started Aug 03 05:29:23 PM PDT 24
Finished Aug 03 05:32:50 PM PDT 24
Peak memory 201432 kb
Host smart-80f046b1-67db-4109-925b-d0adac9fdaaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560099910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
560099910
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4287233176
Short name T120
Test name
Test status
Simulation time 42316491373 ps
CPU time 45.67 seconds
Started Aug 03 04:26:32 PM PDT 24
Finished Aug 03 04:27:18 PM PDT 24
Peak memory 201400 kb
Host smart-63122772-20aa-499b-8691-3ada33a91e59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287233176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4287233176
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3043237965
Short name T30
Test name
Test status
Simulation time 361020876739 ps
CPU time 594.8 seconds
Started Aug 03 05:31:08 PM PDT 24
Finished Aug 03 05:41:03 PM PDT 24
Peak memory 201424 kb
Host smart-15853989-f8ec-4e5a-8384-2e7408656cba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043237965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3043237965
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2606880001
Short name T38
Test name
Test status
Simulation time 657160766664 ps
CPU time 958.21 seconds
Started Aug 03 05:32:37 PM PDT 24
Finished Aug 03 05:48:35 PM PDT 24
Peak memory 201424 kb
Host smart-32798430-9130-4d1a-a8fd-af621c3eb310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606880001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2606880001
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4108585861
Short name T5
Test name
Test status
Simulation time 216628427326 ps
CPU time 40.59 seconds
Started Aug 03 05:29:01 PM PDT 24
Finished Aug 03 05:29:41 PM PDT 24
Peak memory 201400 kb
Host smart-f2646080-19fa-471a-9371-d8b542298ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108585861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4108585861
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.198135070
Short name T226
Test name
Test status
Simulation time 495063294578 ps
CPU time 313.1 seconds
Started Aug 03 05:30:08 PM PDT 24
Finished Aug 03 05:35:21 PM PDT 24
Peak memory 201424 kb
Host smart-1300b05b-261f-4cd6-a78c-1b5fb0f09685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198135070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.198135070
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2547565951
Short name T234
Test name
Test status
Simulation time 491675366423 ps
CPU time 1137.26 seconds
Started Aug 03 05:29:36 PM PDT 24
Finished Aug 03 05:48:34 PM PDT 24
Peak memory 201432 kb
Host smart-83eeedb6-d066-4bc2-9260-5056774feec5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547565951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2547565951
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3716688563
Short name T89
Test name
Test status
Simulation time 538360549746 ps
CPU time 298.79 seconds
Started Aug 03 05:30:07 PM PDT 24
Finished Aug 03 05:35:06 PM PDT 24
Peak memory 201520 kb
Host smart-ebd739d4-7cd4-4a43-b0f8-43ed117bf3ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716688563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3716688563
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2343424711
Short name T271
Test name
Test status
Simulation time 480633146713 ps
CPU time 911.39 seconds
Started Aug 03 05:32:32 PM PDT 24
Finished Aug 03 05:47:44 PM PDT 24
Peak memory 201440 kb
Host smart-c54291ad-6a54-4067-bc3d-3ff8b87f23ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343424711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2343424711
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.657277127
Short name T224
Test name
Test status
Simulation time 537485082147 ps
CPU time 1241.54 seconds
Started Aug 03 05:29:11 PM PDT 24
Finished Aug 03 05:49:53 PM PDT 24
Peak memory 201460 kb
Host smart-8ff07c2a-f759-43cc-983d-6b62942855d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657277127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.657277127
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3035341292
Short name T99
Test name
Test status
Simulation time 330107232108 ps
CPU time 691.96 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:40:38 PM PDT 24
Peak memory 201448 kb
Host smart-3b2bf20b-df8a-471f-b1fe-76aab5297678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035341292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3035341292
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4044735170
Short name T8
Test name
Test status
Simulation time 390879319555 ps
CPU time 228.42 seconds
Started Aug 03 05:30:18 PM PDT 24
Finished Aug 03 05:34:06 PM PDT 24
Peak memory 201436 kb
Host smart-472c4ffc-ce78-4c5a-a824-ac28f2251b99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044735170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4044735170
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.283804385
Short name T331
Test name
Test status
Simulation time 496881957629 ps
CPU time 334.94 seconds
Started Aug 03 05:32:41 PM PDT 24
Finished Aug 03 05:38:16 PM PDT 24
Peak memory 201476 kb
Host smart-1b9146b1-9344-44be-9b19-b868e19749e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283804385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.283804385
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3157694466
Short name T49
Test name
Test status
Simulation time 45456817411 ps
CPU time 104.78 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:30:25 PM PDT 24
Peak memory 209868 kb
Host smart-20080d85-e689-4390-8c80-09c542cc4316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157694466 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3157694466
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1377460489
Short name T287
Test name
Test status
Simulation time 549476860628 ps
CPU time 139.17 seconds
Started Aug 03 05:28:53 PM PDT 24
Finished Aug 03 05:31:13 PM PDT 24
Peak memory 201420 kb
Host smart-a046f1e1-76ca-4589-a0da-c3ff0d880ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377460489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1377460489
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.93321929
Short name T78
Test name
Test status
Simulation time 320088681 ps
CPU time 1.27 seconds
Started Aug 03 05:29:16 PM PDT 24
Finished Aug 03 05:29:17 PM PDT 24
Peak memory 201196 kb
Host smart-505e20ac-2f9c-4711-b856-8f6bfb7e5a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93321929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.93321929
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2884823007
Short name T68
Test name
Test status
Simulation time 8448710590 ps
CPU time 6.01 seconds
Started Aug 03 04:26:41 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201416 kb
Host smart-913400ba-0ab7-4d2e-b51f-411258bb1bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884823007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2884823007
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3519152759
Short name T1
Test name
Test status
Simulation time 333572522417 ps
CPU time 694.04 seconds
Started Aug 03 05:33:31 PM PDT 24
Finished Aug 03 05:45:05 PM PDT 24
Peak memory 201436 kb
Host smart-b1bdf07c-e238-4ca7-8760-817e61edef16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519152759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3519152759
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1936840162
Short name T233
Test name
Test status
Simulation time 488813386974 ps
CPU time 251.68 seconds
Started Aug 03 05:29:15 PM PDT 24
Finished Aug 03 05:33:27 PM PDT 24
Peak memory 201532 kb
Host smart-157654be-96dc-4adb-bd74-461bdf8edb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936840162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1936840162
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.865842057
Short name T135
Test name
Test status
Simulation time 4397717316 ps
CPU time 3.39 seconds
Started Aug 03 04:26:22 PM PDT 24
Finished Aug 03 04:26:25 PM PDT 24
Peak memory 201364 kb
Host smart-009ac9dc-4d9a-474b-a399-a7503f701b14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865842057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.865842057
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3579763268
Short name T277
Test name
Test status
Simulation time 104808120627 ps
CPU time 110.98 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:30:55 PM PDT 24
Peak memory 210108 kb
Host smart-11d52069-4617-48d0-864b-7b65e68c3f81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579763268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3579763268
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.783633926
Short name T305
Test name
Test status
Simulation time 489441207515 ps
CPU time 575.42 seconds
Started Aug 03 05:29:49 PM PDT 24
Finished Aug 03 05:39:24 PM PDT 24
Peak memory 201384 kb
Host smart-f2c25c88-7d65-4095-ad9c-d04ee8d5176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783633926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.783633926
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3315965025
Short name T247
Test name
Test status
Simulation time 167861583895 ps
CPU time 98.92 seconds
Started Aug 03 05:30:19 PM PDT 24
Finished Aug 03 05:31:58 PM PDT 24
Peak memory 201420 kb
Host smart-92175246-a640-4523-b0e9-4c2ce2202498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315965025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3315965025
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1415692404
Short name T192
Test name
Test status
Simulation time 326126406580 ps
CPU time 175.81 seconds
Started Aug 03 05:30:28 PM PDT 24
Finished Aug 03 05:33:24 PM PDT 24
Peak memory 201492 kb
Host smart-78c17e16-020f-4482-b4d8-89c90026bde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415692404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1415692404
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2502550131
Short name T211
Test name
Test status
Simulation time 663129700903 ps
CPU time 1453.27 seconds
Started Aug 03 05:29:37 PM PDT 24
Finished Aug 03 05:53:50 PM PDT 24
Peak memory 201560 kb
Host smart-69a476df-c8d6-44db-99ec-b825744b9554
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502550131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2502550131
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1762870182
Short name T256
Test name
Test status
Simulation time 348040891422 ps
CPU time 154.62 seconds
Started Aug 03 05:29:02 PM PDT 24
Finished Aug 03 05:31:37 PM PDT 24
Peak memory 218136 kb
Host smart-364be62f-9630-4813-b2a6-2c4d83b596ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762870182 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1762870182
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.262887972
Short name T173
Test name
Test status
Simulation time 317523791460 ps
CPU time 362.53 seconds
Started Aug 03 05:29:53 PM PDT 24
Finished Aug 03 05:35:55 PM PDT 24
Peak memory 201472 kb
Host smart-37ed0385-f667-438d-8df0-50650737975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262887972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.262887972
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.979357521
Short name T307
Test name
Test status
Simulation time 332704557263 ps
CPU time 194.02 seconds
Started Aug 03 05:29:36 PM PDT 24
Finished Aug 03 05:32:50 PM PDT 24
Peak memory 201464 kb
Host smart-d5768753-503d-4a04-a506-2d4c04173288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979357521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.979357521
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1929674172
Short name T18
Test name
Test status
Simulation time 191131296190 ps
CPU time 286.12 seconds
Started Aug 03 05:29:57 PM PDT 24
Finished Aug 03 05:34:43 PM PDT 24
Peak memory 211172 kb
Host smart-aee5e9fb-253a-4fa7-bccf-5cff652508f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929674172 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1929674172
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3993376771
Short name T174
Test name
Test status
Simulation time 497893772428 ps
CPU time 287.44 seconds
Started Aug 03 05:32:01 PM PDT 24
Finished Aug 03 05:36:49 PM PDT 24
Peak memory 201512 kb
Host smart-6d960842-e545-451e-8bdc-7a2ba0ffb402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993376771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3993376771
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3841444256
Short name T12
Test name
Test status
Simulation time 339684978637 ps
CPU time 672.24 seconds
Started Aug 03 05:30:23 PM PDT 24
Finished Aug 03 05:41:35 PM PDT 24
Peak memory 201508 kb
Host smart-32b69554-b6fb-4f3a-afda-c5ffbeb11602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841444256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3841444256
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1449227613
Short name T204
Test name
Test status
Simulation time 350441435814 ps
CPU time 1008.89 seconds
Started Aug 03 05:32:04 PM PDT 24
Finished Aug 03 05:48:53 PM PDT 24
Peak memory 209996 kb
Host smart-8a916ee5-ac4b-491a-bb4d-e5d9b7d17a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449227613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1449227613
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1118692102
Short name T214
Test name
Test status
Simulation time 494861124299 ps
CPU time 1075.14 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:52:53 PM PDT 24
Peak memory 201420 kb
Host smart-cc6d8884-3f6a-47a7-8e04-82270000824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118692102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1118692102
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1610384277
Short name T207
Test name
Test status
Simulation time 318090462184 ps
CPU time 448.56 seconds
Started Aug 03 05:29:27 PM PDT 24
Finished Aug 03 05:36:56 PM PDT 24
Peak memory 210016 kb
Host smart-045f9845-123e-404d-85fb-f9a4ba2346d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610384277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1610384277
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3421286428
Short name T251
Test name
Test status
Simulation time 333909503528 ps
CPU time 225.36 seconds
Started Aug 03 05:28:28 PM PDT 24
Finished Aug 03 05:32:13 PM PDT 24
Peak memory 201436 kb
Host smart-04e6d2a5-ace6-45fc-89ec-641a9e9e30ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421286428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3421286428
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2226831488
Short name T28
Test name
Test status
Simulation time 490488267033 ps
CPU time 1066.53 seconds
Started Aug 03 05:31:39 PM PDT 24
Finished Aug 03 05:49:25 PM PDT 24
Peak memory 201412 kb
Host smart-328a5b6b-bccf-4e83-bd0d-2b75b537ba9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226831488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2226831488
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1672278420
Short name T184
Test name
Test status
Simulation time 330504283822 ps
CPU time 183.48 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:31:43 PM PDT 24
Peak memory 201604 kb
Host smart-c043c8d1-9c8e-4ca5-a3e3-aaed04a58ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672278420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1672278420
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1717941179
Short name T301
Test name
Test status
Simulation time 425435768750 ps
CPU time 925.28 seconds
Started Aug 03 05:28:28 PM PDT 24
Finished Aug 03 05:43:54 PM PDT 24
Peak memory 201436 kb
Host smart-69df195d-b40b-4646-a236-618385a03e4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717941179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1717941179
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1888051682
Short name T292
Test name
Test status
Simulation time 174353350475 ps
CPU time 408.49 seconds
Started Aug 03 05:29:05 PM PDT 24
Finished Aug 03 05:35:54 PM PDT 24
Peak memory 200800 kb
Host smart-5da290a6-597e-47ac-aa35-6578ff79d8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888051682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1888051682
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3507425976
Short name T53
Test name
Test status
Simulation time 123230287058 ps
CPU time 454.76 seconds
Started Aug 03 05:29:48 PM PDT 24
Finished Aug 03 05:37:23 PM PDT 24
Peak memory 201840 kb
Host smart-5efda4ae-1e30-4e46-9d73-57fcb8b6527f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507425976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3507425976
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.970814853
Short name T21
Test name
Test status
Simulation time 132605031275 ps
CPU time 292.49 seconds
Started Aug 03 05:31:10 PM PDT 24
Finished Aug 03 05:36:02 PM PDT 24
Peak memory 210216 kb
Host smart-82e83da6-ba19-46f6-a236-ac6db5d64ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970814853 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.970814853
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3880714685
Short name T284
Test name
Test status
Simulation time 372981555650 ps
CPU time 901.35 seconds
Started Aug 03 05:31:02 PM PDT 24
Finished Aug 03 05:46:04 PM PDT 24
Peak memory 210012 kb
Host smart-c8961669-5389-4bbf-9eb0-219dd293c0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880714685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3880714685
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3754721781
Short name T265
Test name
Test status
Simulation time 607267402853 ps
CPU time 362.72 seconds
Started Aug 03 05:31:07 PM PDT 24
Finished Aug 03 05:37:10 PM PDT 24
Peak memory 201432 kb
Host smart-278a78fd-ff38-4506-8052-bbe090029168
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754721781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3754721781
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1855714047
Short name T182
Test name
Test status
Simulation time 356474221550 ps
CPU time 104.69 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:36:43 PM PDT 24
Peak memory 201360 kb
Host smart-d891c791-326f-4570-9de9-73a15d4f5d04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855714047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1855714047
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3486685134
Short name T297
Test name
Test status
Simulation time 329528042111 ps
CPU time 447.12 seconds
Started Aug 03 05:32:26 PM PDT 24
Finished Aug 03 05:39:53 PM PDT 24
Peak memory 201464 kb
Host smart-deccd245-0832-4178-9f86-0c1c0b9c69f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486685134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3486685134
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1565739636
Short name T269
Test name
Test status
Simulation time 476022892683 ps
CPU time 280.25 seconds
Started Aug 03 05:29:09 PM PDT 24
Finished Aug 03 05:33:49 PM PDT 24
Peak memory 201428 kb
Host smart-b00a09c1-7f66-4eaf-aa99-2b41e29cb957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565739636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1565739636
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3746196673
Short name T186
Test name
Test status
Simulation time 494984087256 ps
CPU time 292.73 seconds
Started Aug 03 05:29:21 PM PDT 24
Finished Aug 03 05:34:14 PM PDT 24
Peak memory 201472 kb
Host smart-456c7975-0ccb-470a-b376-c49acac83428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746196673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3746196673
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2916700723
Short name T196
Test name
Test status
Simulation time 755149986324 ps
CPU time 1263.72 seconds
Started Aug 03 05:28:44 PM PDT 24
Finished Aug 03 05:49:48 PM PDT 24
Peak memory 212600 kb
Host smart-3311a740-93e0-4251-8620-2c8ca26a19cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916700723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2916700723
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3587906281
Short name T141
Test name
Test status
Simulation time 529537273624 ps
CPU time 72.02 seconds
Started Aug 03 05:28:53 PM PDT 24
Finished Aug 03 05:30:05 PM PDT 24
Peak memory 201416 kb
Host smart-648bc433-1244-4ac1-b8cb-795c6c9a479e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587906281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3587906281
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.826758842
Short name T310
Test name
Test status
Simulation time 183586074287 ps
CPU time 224.14 seconds
Started Aug 03 05:29:02 PM PDT 24
Finished Aug 03 05:32:46 PM PDT 24
Peak memory 201448 kb
Host smart-89c1bf7d-fbaa-4d8c-8911-f1c6548b88ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826758842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.826758842
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.134033080
Short name T294
Test name
Test status
Simulation time 348633781448 ps
CPU time 693.87 seconds
Started Aug 03 05:29:20 PM PDT 24
Finished Aug 03 05:40:54 PM PDT 24
Peak memory 201372 kb
Host smart-c49c0bdc-f27d-4ae1-9f5b-02497a7859ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134033080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.134033080
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2285791032
Short name T749
Test name
Test status
Simulation time 201629172095 ps
CPU time 240.86 seconds
Started Aug 03 05:30:20 PM PDT 24
Finished Aug 03 05:34:21 PM PDT 24
Peak memory 218292 kb
Host smart-a4d0c1bd-9e75-49b5-a12d-ccc9809582e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285791032 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2285791032
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4068139133
Short name T296
Test name
Test status
Simulation time 330200376520 ps
CPU time 347.02 seconds
Started Aug 03 05:31:29 PM PDT 24
Finished Aug 03 05:37:16 PM PDT 24
Peak memory 201448 kb
Host smart-691bb902-f93f-4c2d-bce7-6dab5c97f665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068139133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4068139133
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.267542208
Short name T75
Test name
Test status
Simulation time 540564992 ps
CPU time 1.89 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:40 PM PDT 24
Peak memory 201456 kb
Host smart-4f69d392-be16-4272-ac4f-faa4c5cba41b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267542208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.267542208
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3052832763
Short name T880
Test name
Test status
Simulation time 8747645541 ps
CPU time 22.27 seconds
Started Aug 03 04:26:20 PM PDT 24
Finished Aug 03 04:26:42 PM PDT 24
Peak memory 201452 kb
Host smart-d74efcc6-09ad-4862-a679-fd6189f4e826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052832763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3052832763
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4109206636
Short name T46
Test name
Test status
Simulation time 71876672249 ps
CPU time 115.57 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:31:02 PM PDT 24
Peak memory 218320 kb
Host smart-23cbf993-d04a-4420-8d2a-ebb756483a0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109206636 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.4109206636
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.217286336
Short name T342
Test name
Test status
Simulation time 119117316541 ps
CPU time 434.7 seconds
Started Aug 03 05:29:17 PM PDT 24
Finished Aug 03 05:36:32 PM PDT 24
Peak memory 201800 kb
Host smart-8bf9c42e-d8bb-4988-8636-06fc33ac6bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217286336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.217286336
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1579669094
Short name T250
Test name
Test status
Simulation time 165537611189 ps
CPU time 356.65 seconds
Started Aug 03 05:29:16 PM PDT 24
Finished Aug 03 05:35:13 PM PDT 24
Peak memory 201424 kb
Host smart-7033ce20-ef45-4e5c-b081-d6fde79e5949
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579669094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1579669094
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1298919772
Short name T279
Test name
Test status
Simulation time 485906565782 ps
CPU time 530.31 seconds
Started Aug 03 05:29:32 PM PDT 24
Finished Aug 03 05:38:23 PM PDT 24
Peak memory 201396 kb
Host smart-19e55557-b885-4666-a249-0f8a4a6bda0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298919772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1298919772
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.4095016976
Short name T209
Test name
Test status
Simulation time 632023948127 ps
CPU time 351.65 seconds
Started Aug 03 05:29:48 PM PDT 24
Finished Aug 03 05:35:40 PM PDT 24
Peak memory 212292 kb
Host smart-87990802-d73e-497c-9279-6704f3116bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095016976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.4095016976
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2824345817
Short name T193
Test name
Test status
Simulation time 571843265777 ps
CPU time 241.91 seconds
Started Aug 03 05:29:53 PM PDT 24
Finished Aug 03 05:33:56 PM PDT 24
Peak memory 201400 kb
Host smart-46ac55c1-6188-4551-8554-1c9523d71b05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824345817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2824345817
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2469685558
Short name T325
Test name
Test status
Simulation time 529800813025 ps
CPU time 589.72 seconds
Started Aug 03 05:30:10 PM PDT 24
Finished Aug 03 05:40:00 PM PDT 24
Peak memory 201516 kb
Host smart-4284d90c-b2db-4f4e-9ad7-9e41b62548ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469685558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2469685558
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.667681574
Short name T236
Test name
Test status
Simulation time 358152801290 ps
CPU time 267.81 seconds
Started Aug 03 05:31:33 PM PDT 24
Finished Aug 03 05:36:01 PM PDT 24
Peak memory 201444 kb
Host smart-d62a4232-ace5-4a1e-a030-64e430c595ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667681574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
667681574
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4109940439
Short name T87
Test name
Test status
Simulation time 710452173447 ps
CPU time 1505.06 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:53:55 PM PDT 24
Peak memory 201468 kb
Host smart-0f11dfb1-3ff1-49fc-96a6-f9fa3b21f736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109940439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4109940439
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2604468834
Short name T201
Test name
Test status
Simulation time 144809054606 ps
CPU time 728.98 seconds
Started Aug 03 05:32:16 PM PDT 24
Finished Aug 03 05:44:25 PM PDT 24
Peak memory 201856 kb
Host smart-ae432710-1d53-4666-80cf-bbc21e4d8c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604468834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2604468834
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.447413452
Short name T129
Test name
Test status
Simulation time 629891994 ps
CPU time 2.45 seconds
Started Aug 03 04:26:24 PM PDT 24
Finished Aug 03 04:26:27 PM PDT 24
Peak memory 201308 kb
Host smart-b28c7649-98de-41b4-9bb4-471118c9a708
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447413452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.447413452
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1965565692
Short name T898
Test name
Test status
Simulation time 44462146317 ps
CPU time 38.02 seconds
Started Aug 03 04:26:21 PM PDT 24
Finished Aug 03 04:26:59 PM PDT 24
Peak memory 201340 kb
Host smart-312eb19d-20f6-4ac4-9af1-02e456fe4f51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965565692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1965565692
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1683471775
Short name T117
Test name
Test status
Simulation time 1301319488 ps
CPU time 1.43 seconds
Started Aug 03 04:26:20 PM PDT 24
Finished Aug 03 04:26:22 PM PDT 24
Peak memory 201148 kb
Host smart-5f951157-03c1-445c-b660-aafd1b189c34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683471775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1683471775
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3324370615
Short name T872
Test name
Test status
Simulation time 496835305 ps
CPU time 1.55 seconds
Started Aug 03 04:26:24 PM PDT 24
Finished Aug 03 04:26:26 PM PDT 24
Peak memory 201216 kb
Host smart-5a78c6e1-00f8-404f-8b9d-bc6f89530ed7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324370615 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3324370615
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.328913803
Short name T123
Test name
Test status
Simulation time 415825538 ps
CPU time 1.74 seconds
Started Aug 03 04:26:20 PM PDT 24
Finished Aug 03 04:26:22 PM PDT 24
Peak memory 201192 kb
Host smart-97c0928d-b648-413e-b7d0-03bdd55a81e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328913803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.328913803
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2963668715
Short name T850
Test name
Test status
Simulation time 530749353 ps
CPU time 1.97 seconds
Started Aug 03 04:26:22 PM PDT 24
Finished Aug 03 04:26:24 PM PDT 24
Peak memory 201072 kb
Host smart-4fd53fcf-bea3-4b11-9ac4-e3bd1cc1eeb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963668715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2963668715
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2202999870
Short name T918
Test name
Test status
Simulation time 369609301 ps
CPU time 2.04 seconds
Started Aug 03 04:26:21 PM PDT 24
Finished Aug 03 04:26:23 PM PDT 24
Peak memory 201464 kb
Host smart-cc91d372-ec4c-438f-9c78-752b696ec5da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202999870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2202999870
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2220996490
Short name T807
Test name
Test status
Simulation time 1183545437 ps
CPU time 2.6 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:31 PM PDT 24
Peak memory 201264 kb
Host smart-93c3297f-7737-4eff-8a8b-fe2a99f83a49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220996490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2220996490
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1512649559
Short name T818
Test name
Test status
Simulation time 1234859038 ps
CPU time 1.49 seconds
Started Aug 03 04:26:29 PM PDT 24
Finished Aug 03 04:26:30 PM PDT 24
Peak memory 201128 kb
Host smart-a1b1d148-1b54-4708-9d07-97608a27bf29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512649559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1512649559
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.339985460
Short name T891
Test name
Test status
Simulation time 433371225 ps
CPU time 1.98 seconds
Started Aug 03 04:26:30 PM PDT 24
Finished Aug 03 04:26:32 PM PDT 24
Peak memory 201252 kb
Host smart-e24a0eef-0cd7-4a86-b113-044d9574fc4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339985460 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.339985460
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1803754240
Short name T912
Test name
Test status
Simulation time 325606023 ps
CPU time 1.52 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:30 PM PDT 24
Peak memory 201152 kb
Host smart-7d0305f1-a1e6-4413-a85f-5e83c8d6eaa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803754240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1803754240
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3518562797
Short name T854
Test name
Test status
Simulation time 545863145 ps
CPU time 0.68 seconds
Started Aug 03 04:26:31 PM PDT 24
Finished Aug 03 04:26:32 PM PDT 24
Peak memory 201172 kb
Host smart-6dde442b-cc7f-4513-8b14-6dc67e2ab857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518562797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3518562797
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2550303981
Short name T892
Test name
Test status
Simulation time 2006179395 ps
CPU time 4.86 seconds
Started Aug 03 04:26:30 PM PDT 24
Finished Aug 03 04:26:35 PM PDT 24
Peak memory 201300 kb
Host smart-e4834fca-839e-4ab0-8bfa-5852f75d4a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550303981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2550303981
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1957639916
Short name T913
Test name
Test status
Simulation time 515918254 ps
CPU time 3.57 seconds
Started Aug 03 04:26:30 PM PDT 24
Finished Aug 03 04:26:34 PM PDT 24
Peak memory 209644 kb
Host smart-6078624b-b853-4b2a-ba0e-ab53cb1439bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957639916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1957639916
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.467799537
Short name T62
Test name
Test status
Simulation time 4133562127 ps
CPU time 10.3 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 201480 kb
Host smart-5978577d-d1b8-426b-9dcf-82c8b6e92392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467799537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.467799537
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4020933189
Short name T893
Test name
Test status
Simulation time 600182887 ps
CPU time 1.2 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:37 PM PDT 24
Peak memory 201288 kb
Host smart-bc4283d0-13f6-48e7-82e9-2ea315dcb283
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020933189 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.4020933189
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2816502260
Short name T116
Test name
Test status
Simulation time 521863909 ps
CPU time 1.07 seconds
Started Aug 03 04:26:40 PM PDT 24
Finished Aug 03 04:26:41 PM PDT 24
Peak memory 201196 kb
Host smart-ef453937-f2b3-4cce-add0-5587e0dda0fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816502260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2816502260
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3887941981
Short name T878
Test name
Test status
Simulation time 508693285 ps
CPU time 0.92 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:37 PM PDT 24
Peak memory 201128 kb
Host smart-2e8140ba-e113-4d65-a1c0-465f95c37181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887941981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3887941981
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2300514618
Short name T829
Test name
Test status
Simulation time 5531692959 ps
CPU time 12.61 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:50 PM PDT 24
Peak memory 201392 kb
Host smart-fd3cd2f5-aedd-4979-94ac-66334c45c223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300514618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2300514618
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1108942896
Short name T63
Test name
Test status
Simulation time 4027906478 ps
CPU time 3.66 seconds
Started Aug 03 04:26:40 PM PDT 24
Finished Aug 03 04:26:44 PM PDT 24
Peak memory 201396 kb
Host smart-c7bf5584-f914-421d-93ca-d93ee43340f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108942896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1108942896
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3384717395
Short name T846
Test name
Test status
Simulation time 646969948 ps
CPU time 1.14 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201444 kb
Host smart-80fd070a-c92b-465d-b505-6f62d87c0c0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384717395 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3384717395
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.806399973
Short name T128
Test name
Test status
Simulation time 502815819 ps
CPU time 0.9 seconds
Started Aug 03 04:26:42 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 201140 kb
Host smart-843d24e8-8461-47a7-a52a-b654ba4ee345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806399973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.806399973
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2144253135
Short name T806
Test name
Test status
Simulation time 516603844 ps
CPU time 0.66 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:36 PM PDT 24
Peak memory 201164 kb
Host smart-117a7b93-fb9d-4b3b-b296-9e381bb17e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144253135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2144253135
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.740085807
Short name T827
Test name
Test status
Simulation time 1647190737 ps
CPU time 4.02 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:40 PM PDT 24
Peak memory 201264 kb
Host smart-eb410a47-6020-4a0f-9b7a-a276a3e4b961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740085807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.740085807
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2433505685
Short name T341
Test name
Test status
Simulation time 4908530301 ps
CPU time 4.98 seconds
Started Aug 03 04:26:40 PM PDT 24
Finished Aug 03 04:26:45 PM PDT 24
Peak memory 201420 kb
Host smart-7043da20-c1f1-44f5-8c7b-f4b65030e45b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433505685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2433505685
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1554273104
Short name T839
Test name
Test status
Simulation time 495442136 ps
CPU time 1.2 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201628 kb
Host smart-59c4aae7-7ff9-47d2-a12e-011fc331d865
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554273104 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1554273104
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4242393179
Short name T916
Test name
Test status
Simulation time 522263790 ps
CPU time 1.43 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 201148 kb
Host smart-ae04e775-04a0-4d7e-a10e-181ace716985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242393179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4242393179
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4183616791
Short name T835
Test name
Test status
Simulation time 393565055 ps
CPU time 0.98 seconds
Started Aug 03 04:26:42 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 201128 kb
Host smart-4ae39238-75d2-4ac2-86eb-0d48cd3a8a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183616791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.4183616791
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3886184974
Short name T58
Test name
Test status
Simulation time 4702637678 ps
CPU time 10.78 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201404 kb
Host smart-1892e105-59c2-40b9-9671-e66fc6a8afeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886184974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3886184974
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.708404812
Short name T843
Test name
Test status
Simulation time 539261894 ps
CPU time 1.99 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:40 PM PDT 24
Peak memory 201444 kb
Host smart-237eaf26-3d0d-4cf2-b60f-9534034b7bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708404812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.708404812
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.464940352
Short name T884
Test name
Test status
Simulation time 4826933143 ps
CPU time 3.87 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:42 PM PDT 24
Peak memory 201448 kb
Host smart-19d71f23-d37f-40a1-a769-73cf86998d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464940352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.464940352
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3882815709
Short name T95
Test name
Test status
Simulation time 372995029 ps
CPU time 1.06 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 201276 kb
Host smart-7cee332b-82fb-4596-9207-3d53810a5ba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882815709 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3882815709
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.699080024
Short name T841
Test name
Test status
Simulation time 502153004 ps
CPU time 1.03 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201148 kb
Host smart-f110fa4d-c849-4fbb-994c-a474fc9bdeaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699080024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.699080024
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2834340497
Short name T831
Test name
Test status
Simulation time 445971474 ps
CPU time 0.83 seconds
Started Aug 03 04:26:35 PM PDT 24
Finished Aug 03 04:26:36 PM PDT 24
Peak memory 201100 kb
Host smart-5c82f32e-ab7e-40e5-9649-13d8fda41929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834340497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2834340497
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2353214623
Short name T859
Test name
Test status
Simulation time 2434465247 ps
CPU time 4.39 seconds
Started Aug 03 04:26:40 PM PDT 24
Finished Aug 03 04:26:45 PM PDT 24
Peak memory 201160 kb
Host smart-5269672d-10f4-4f19-9e82-c01a18cf1dc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353214623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2353214623
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2750714583
Short name T902
Test name
Test status
Simulation time 447993565 ps
CPU time 2.41 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201472 kb
Host smart-53b1ad9d-1742-44c4-88f2-f705f859eef1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750714583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2750714583
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1616961185
Short name T867
Test name
Test status
Simulation time 8585740070 ps
CPU time 6.76 seconds
Started Aug 03 04:26:40 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201376 kb
Host smart-181c0992-f17f-4f14-95e7-4cea728c8096
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616961185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1616961185
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2299917711
Short name T855
Test name
Test status
Simulation time 422567216 ps
CPU time 2.09 seconds
Started Aug 03 04:26:56 PM PDT 24
Finished Aug 03 04:26:58 PM PDT 24
Peak memory 201228 kb
Host smart-fd133cfa-cbde-4506-a713-c212271e6441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299917711 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2299917711
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2449566272
Short name T126
Test name
Test status
Simulation time 468835470 ps
CPU time 1.22 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201148 kb
Host smart-2644dc96-e3f0-4b3a-8252-b4c7d921311a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449566272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2449566272
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3966652483
Short name T810
Test name
Test status
Simulation time 543861935 ps
CPU time 0.93 seconds
Started Aug 03 04:26:48 PM PDT 24
Finished Aug 03 04:26:49 PM PDT 24
Peak memory 201136 kb
Host smart-d20d7e21-998e-43cb-9b57-c32a1e7778f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966652483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3966652483
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2659303820
Short name T887
Test name
Test status
Simulation time 4088939610 ps
CPU time 2.38 seconds
Started Aug 03 04:26:42 PM PDT 24
Finished Aug 03 04:26:44 PM PDT 24
Peak memory 201400 kb
Host smart-3512bfd3-e906-4d55-aa70-89e216ac9b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659303820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2659303820
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3448200101
Short name T72
Test name
Test status
Simulation time 480427078 ps
CPU time 1.84 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 209588 kb
Host smart-c98884ca-ccc1-4c13-8ff4-06c705b32e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448200101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3448200101
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3239745777
Short name T914
Test name
Test status
Simulation time 4254823449 ps
CPU time 11.34 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:57 PM PDT 24
Peak memory 201456 kb
Host smart-ee8a0b58-d0f1-4150-adc7-e71c2f5e7884
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239745777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3239745777
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1973949439
Short name T84
Test name
Test status
Simulation time 594903516 ps
CPU time 1.34 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:45 PM PDT 24
Peak memory 201248 kb
Host smart-e503b724-63fa-498e-92ee-9a437be01f62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973949439 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1973949439
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.647136912
Short name T894
Test name
Test status
Simulation time 417895280 ps
CPU time 1.67 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201496 kb
Host smart-b94bbf39-a5b5-4fb6-920c-25af8f8f3c0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647136912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.647136912
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.574648936
Short name T803
Test name
Test status
Simulation time 391868593 ps
CPU time 1.52 seconds
Started Aug 03 04:26:43 PM PDT 24
Finished Aug 03 04:26:44 PM PDT 24
Peak memory 201140 kb
Host smart-bbde6487-9f3c-4869-ad4d-6421e380047f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574648936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.574648936
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1268977614
Short name T59
Test name
Test status
Simulation time 4191836625 ps
CPU time 9.48 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:56 PM PDT 24
Peak memory 201752 kb
Host smart-a8154c3b-6f24-4788-95ce-cc24274ad5ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268977614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1268977614
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4167072328
Short name T833
Test name
Test status
Simulation time 571107668 ps
CPU time 2.77 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:46 PM PDT 24
Peak memory 210768 kb
Host smart-339008dd-bd1d-4c80-aeb2-a6a2c7dc2a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167072328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4167072328
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.979014577
Short name T61
Test name
Test status
Simulation time 4216236401 ps
CPU time 6.29 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:51 PM PDT 24
Peak memory 201420 kb
Host smart-cfee3c0f-b5ae-4a8d-86d5-15de2d431541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979014577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.979014577
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1784262576
Short name T862
Test name
Test status
Simulation time 497714451 ps
CPU time 1.37 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:46 PM PDT 24
Peak memory 217952 kb
Host smart-4910ce07-faac-4bfe-8f96-63e841970dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784262576 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1784262576
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.939303996
Short name T133
Test name
Test status
Simulation time 360136867 ps
CPU time 0.94 seconds
Started Aug 03 04:26:49 PM PDT 24
Finished Aug 03 04:26:50 PM PDT 24
Peak memory 201176 kb
Host smart-175fccd4-4847-4ed3-ace9-d73a2ad3982e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939303996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.939303996
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3848010052
Short name T852
Test name
Test status
Simulation time 516664996 ps
CPU time 1.87 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201188 kb
Host smart-8c5be461-a27f-4850-b0cf-2ce24912dfc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848010052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3848010052
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1115010523
Short name T897
Test name
Test status
Simulation time 4445121502 ps
CPU time 3.51 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:51 PM PDT 24
Peak memory 201420 kb
Host smart-1cae8c1c-b03f-4669-86e8-723b311c63a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115010523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1115010523
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4063630411
Short name T888
Test name
Test status
Simulation time 651257711 ps
CPU time 2.55 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201436 kb
Host smart-8f9634e4-04b1-4302-8fe4-468eaa024b48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063630411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.4063630411
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2511851316
Short name T340
Test name
Test status
Simulation time 8449012233 ps
CPU time 22.26 seconds
Started Aug 03 04:26:43 PM PDT 24
Finished Aug 03 04:27:05 PM PDT 24
Peak memory 201472 kb
Host smart-4bb3f5d5-ddda-4b78-aba2-df22b2533cda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511851316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2511851316
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3562191496
Short name T889
Test name
Test status
Simulation time 416725508 ps
CPU time 1.03 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201332 kb
Host smart-4feb5939-6f6b-4cc5-b809-d1ccebea6534
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562191496 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3562191496
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2501872217
Short name T915
Test name
Test status
Simulation time 351821896 ps
CPU time 1.66 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201196 kb
Host smart-d779d8a1-46a5-4dc9-b814-69a72c5ef170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501872217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2501872217
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3680303644
Short name T849
Test name
Test status
Simulation time 410473688 ps
CPU time 1.08 seconds
Started Aug 03 04:26:43 PM PDT 24
Finished Aug 03 04:26:45 PM PDT 24
Peak memory 201120 kb
Host smart-8e874908-acf5-4837-9233-60c3aaa49f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680303644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3680303644
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3956229250
Short name T832
Test name
Test status
Simulation time 5075196182 ps
CPU time 16.53 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:27:08 PM PDT 24
Peak memory 201368 kb
Host smart-1e0a9453-5bbb-4d03-8516-0149a7dad740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956229250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3956229250
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3147874378
Short name T896
Test name
Test status
Simulation time 1284604089 ps
CPU time 3.23 seconds
Started Aug 03 04:26:48 PM PDT 24
Finished Aug 03 04:26:51 PM PDT 24
Peak memory 210620 kb
Host smart-0ca11d0a-66b4-4577-b3ff-4159bca85965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147874378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3147874378
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2115272438
Short name T874
Test name
Test status
Simulation time 8252185990 ps
CPU time 11.75 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:56 PM PDT 24
Peak memory 201448 kb
Host smart-dc03ffdb-97ac-4875-94ca-1bc82fc504f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115272438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2115272438
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3179034101
Short name T847
Test name
Test status
Simulation time 368204226 ps
CPU time 1.02 seconds
Started Aug 03 04:26:42 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 201400 kb
Host smart-f1d54b50-f824-466c-b745-0ecf392475dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179034101 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3179034101
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3208878709
Short name T132
Test name
Test status
Simulation time 461056461 ps
CPU time 1.77 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201144 kb
Host smart-d5edc578-5026-405b-8525-17d09ff6b129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208878709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3208878709
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1161908020
Short name T814
Test name
Test status
Simulation time 360499514 ps
CPU time 1.42 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:46 PM PDT 24
Peak memory 201144 kb
Host smart-e47899f7-b708-4018-b34a-c2e92936d550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161908020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1161908020
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.854985896
Short name T882
Test name
Test status
Simulation time 5056114837 ps
CPU time 6.27 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:51 PM PDT 24
Peak memory 201384 kb
Host smart-4e45ff90-2412-4130-93c7-89bbf030a164
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854985896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.854985896
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1376193579
Short name T871
Test name
Test status
Simulation time 405133691 ps
CPU time 2.81 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201392 kb
Host smart-a57ee131-1a58-4956-8a54-7a2de31cb5c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376193579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1376193579
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1847598804
Short name T886
Test name
Test status
Simulation time 4311898996 ps
CPU time 3.94 seconds
Started Aug 03 04:26:51 PM PDT 24
Finished Aug 03 04:26:55 PM PDT 24
Peak memory 201428 kb
Host smart-57799d80-b6b9-4e0d-9131-4cbb82d5d18e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847598804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1847598804
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.50371537
Short name T875
Test name
Test status
Simulation time 547478786 ps
CPU time 1.14 seconds
Started Aug 03 04:26:56 PM PDT 24
Finished Aug 03 04:26:57 PM PDT 24
Peak memory 201224 kb
Host smart-1ce29513-a9fc-4c29-ad5f-28d72286d153
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50371537 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.50371537
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4065529968
Short name T879
Test name
Test status
Simulation time 412688864 ps
CPU time 1.63 seconds
Started Aug 03 04:26:56 PM PDT 24
Finished Aug 03 04:26:57 PM PDT 24
Peak memory 201092 kb
Host smart-173f37ee-b826-49e1-b05a-7f2f43a998a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065529968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.4065529968
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.870571613
Short name T864
Test name
Test status
Simulation time 344726959 ps
CPU time 1.38 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201184 kb
Host smart-17f73d09-66d2-4796-a79b-c67b5768262f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870571613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.870571613
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.88903456
Short name T816
Test name
Test status
Simulation time 1970060740 ps
CPU time 1.78 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201160 kb
Host smart-4b95fd14-487a-4ace-9cf5-96302e251684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88903456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ct
rl_same_csr_outstanding.88903456
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2128262170
Short name T64
Test name
Test status
Simulation time 926990780 ps
CPU time 1.62 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201464 kb
Host smart-431c35c2-9c55-44a8-9406-49e722f52311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128262170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2128262170
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.570449480
Short name T67
Test name
Test status
Simulation time 4007643864 ps
CPU time 6.25 seconds
Started Aug 03 04:26:43 PM PDT 24
Finished Aug 03 04:26:49 PM PDT 24
Peak memory 201360 kb
Host smart-6a83da63-dde8-4232-bdbd-e47415dddb1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570449480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.570449480
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3100617102
Short name T822
Test name
Test status
Simulation time 887032137 ps
CPU time 3.6 seconds
Started Aug 03 04:26:30 PM PDT 24
Finished Aug 03 04:26:34 PM PDT 24
Peak memory 201328 kb
Host smart-b1624ec6-af37-4e15-bebc-9196cfe1a741
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100617102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3100617102
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1086528178
Short name T125
Test name
Test status
Simulation time 9130156200 ps
CPU time 47.04 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 201288 kb
Host smart-66af7163-4384-4373-a225-e8514ca662d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086528178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1086528178
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3594281827
Short name T825
Test name
Test status
Simulation time 1195212806 ps
CPU time 1.23 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:29 PM PDT 24
Peak memory 201192 kb
Host smart-2742ab21-fec8-4198-b006-c7c7602b10aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594281827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3594281827
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2044492341
Short name T917
Test name
Test status
Simulation time 352307979 ps
CPU time 1.64 seconds
Started Aug 03 04:26:29 PM PDT 24
Finished Aug 03 04:26:30 PM PDT 24
Peak memory 201284 kb
Host smart-91626ce3-2152-40dc-8591-2bd9f456f822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044492341 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2044492341
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3277109397
Short name T813
Test name
Test status
Simulation time 573332174 ps
CPU time 1.09 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:29 PM PDT 24
Peak memory 201136 kb
Host smart-8ce25711-cd3c-4abd-acbc-aae06fc280f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277109397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3277109397
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1548917154
Short name T838
Test name
Test status
Simulation time 342850822 ps
CPU time 0.87 seconds
Started Aug 03 04:26:30 PM PDT 24
Finished Aug 03 04:26:31 PM PDT 24
Peak memory 201096 kb
Host smart-6e55efdd-ebdc-4ef7-a441-3d2fef29db85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548917154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1548917154
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3302652880
Short name T903
Test name
Test status
Simulation time 1778683939 ps
CPU time 1.86 seconds
Started Aug 03 04:26:31 PM PDT 24
Finished Aug 03 04:26:33 PM PDT 24
Peak memory 201116 kb
Host smart-33a32233-817f-4ddb-ba7a-732c027b7afd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302652880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3302652880
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3826261069
Short name T908
Test name
Test status
Simulation time 365540549 ps
CPU time 2.43 seconds
Started Aug 03 04:26:31 PM PDT 24
Finished Aug 03 04:26:33 PM PDT 24
Peak memory 201484 kb
Host smart-3be348cd-f1b7-4bf2-a412-47fa59dedd2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826261069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3826261069
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2638686517
Short name T66
Test name
Test status
Simulation time 4137400214 ps
CPU time 3.83 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:32 PM PDT 24
Peak memory 201456 kb
Host smart-d50ace1d-0443-4ac8-a7f9-d87122fb9170
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638686517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2638686517
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2957922091
Short name T857
Test name
Test status
Simulation time 279218647 ps
CPU time 1.29 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201488 kb
Host smart-15e4b9b6-cd75-4358-89d0-d84b6bcd33eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957922091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2957922091
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.504092428
Short name T900
Test name
Test status
Simulation time 562193935 ps
CPU time 1.01 seconds
Started Aug 03 04:26:55 PM PDT 24
Finished Aug 03 04:26:56 PM PDT 24
Peak memory 201092 kb
Host smart-3fe9d294-0648-46a3-b712-bafb9f4dbc8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504092428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.504092428
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2740974946
Short name T907
Test name
Test status
Simulation time 448458976 ps
CPU time 1.65 seconds
Started Aug 03 04:26:50 PM PDT 24
Finished Aug 03 04:26:52 PM PDT 24
Peak memory 201068 kb
Host smart-89e9bda8-a134-4ca1-9e34-11aa819c37dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740974946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2740974946
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.128349679
Short name T834
Test name
Test status
Simulation time 471662325 ps
CPU time 0.84 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:45 PM PDT 24
Peak memory 201132 kb
Host smart-cfd1906b-424b-41ec-8af0-13ac0e455fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128349679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.128349679
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.933419798
Short name T851
Test name
Test status
Simulation time 494469985 ps
CPU time 0.91 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201092 kb
Host smart-59e59b4d-b4fe-4f08-a6fe-a247dabae2f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933419798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.933419798
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3441897508
Short name T876
Test name
Test status
Simulation time 378970363 ps
CPU time 0.71 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:46 PM PDT 24
Peak memory 201276 kb
Host smart-62a6464d-6655-4f50-8f8d-707c7104bf4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441897508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3441897508
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2225675858
Short name T809
Test name
Test status
Simulation time 544128607 ps
CPU time 0.85 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:45 PM PDT 24
Peak memory 201104 kb
Host smart-399f0fdf-fa3f-4002-96e7-edfeb460382b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225675858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2225675858
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3610220479
Short name T873
Test name
Test status
Simulation time 314698845 ps
CPU time 0.96 seconds
Started Aug 03 04:26:43 PM PDT 24
Finished Aug 03 04:26:44 PM PDT 24
Peak memory 201104 kb
Host smart-a94f0b55-8bf1-47b8-85c4-05a2177926d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610220479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3610220479
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4227995692
Short name T808
Test name
Test status
Simulation time 386279379 ps
CPU time 1.14 seconds
Started Aug 03 04:26:48 PM PDT 24
Finished Aug 03 04:26:50 PM PDT 24
Peak memory 201180 kb
Host smart-74b57a40-db6f-4ef9-9790-bb6289940894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227995692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.4227995692
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2762334949
Short name T802
Test name
Test status
Simulation time 414368594 ps
CPU time 1.54 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201176 kb
Host smart-bc0bd7cb-b3d4-4ee2-aac0-dcac5859d056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762334949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2762334949
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.310380817
Short name T121
Test name
Test status
Simulation time 1032396359 ps
CPU time 4.15 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:32 PM PDT 24
Peak memory 201336 kb
Host smart-334bd9a6-f2bd-4510-b297-d9ac1aa5a563
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310380817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.310380817
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.509678473
Short name T836
Test name
Test status
Simulation time 26261416093 ps
CPU time 27.61 seconds
Started Aug 03 04:26:32 PM PDT 24
Finished Aug 03 04:27:00 PM PDT 24
Peak memory 201368 kb
Host smart-ddfeb8bd-1a3a-4189-8edf-82e70bc7908e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509678473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.509678473
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3772284471
Short name T119
Test name
Test status
Simulation time 1283715540 ps
CPU time 3.4 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:31 PM PDT 24
Peak memory 201192 kb
Host smart-4d6e9f65-5f91-41b3-bc83-58bb5860ea0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772284471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3772284471
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2684489836
Short name T104
Test name
Test status
Simulation time 531377730 ps
CPU time 1.08 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:29 PM PDT 24
Peak memory 201396 kb
Host smart-c9c30d85-8d91-4a15-b9cb-8f1c473515fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684489836 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2684489836
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1995340655
Short name T134
Test name
Test status
Simulation time 439047353 ps
CPU time 1 seconds
Started Aug 03 04:26:27 PM PDT 24
Finished Aug 03 04:26:28 PM PDT 24
Peak memory 201148 kb
Host smart-5d1309c4-535e-4902-bc4e-f9c362e5e148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995340655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1995340655
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3178157359
Short name T853
Test name
Test status
Simulation time 500631094 ps
CPU time 0.85 seconds
Started Aug 03 04:26:31 PM PDT 24
Finished Aug 03 04:26:32 PM PDT 24
Peak memory 201164 kb
Host smart-576ce5f9-0cdc-42bc-9e34-9a01a7e2769d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178157359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3178157359
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2977101269
Short name T842
Test name
Test status
Simulation time 4850264087 ps
CPU time 3.6 seconds
Started Aug 03 04:26:33 PM PDT 24
Finished Aug 03 04:26:37 PM PDT 24
Peak memory 201384 kb
Host smart-73c6a4d8-1b5a-45fa-9f7a-c3d60eaa8002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977101269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2977101269
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3379233267
Short name T848
Test name
Test status
Simulation time 603263259 ps
CPU time 1.73 seconds
Started Aug 03 04:26:28 PM PDT 24
Finished Aug 03 04:26:30 PM PDT 24
Peak memory 201400 kb
Host smart-6e51f13b-5b14-4bba-9342-59be19281fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379233267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3379233267
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.181782982
Short name T103
Test name
Test status
Simulation time 4500454022 ps
CPU time 12.15 seconds
Started Aug 03 04:26:29 PM PDT 24
Finished Aug 03 04:26:42 PM PDT 24
Peak memory 201484 kb
Host smart-6a759499-fea4-4f6b-8aa1-bc391929c7cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181782982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.181782982
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2396078315
Short name T904
Test name
Test status
Simulation time 469707324 ps
CPU time 1.23 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:49 PM PDT 24
Peak memory 201168 kb
Host smart-47a40de1-e5da-4207-b9dc-f667f79dab2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396078315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2396078315
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.348417084
Short name T901
Test name
Test status
Simulation time 503001955 ps
CPU time 1.24 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:49 PM PDT 24
Peak memory 201120 kb
Host smart-2b240130-0f5c-4eb4-aee8-51820c5dcbec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348417084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.348417084
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1953909344
Short name T804
Test name
Test status
Simulation time 361573456 ps
CPU time 0.88 seconds
Started Aug 03 04:26:50 PM PDT 24
Finished Aug 03 04:26:51 PM PDT 24
Peak memory 201164 kb
Host smart-1edfcc32-2c11-40ba-b291-89da8cd9f89b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953909344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1953909344
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2762688436
Short name T820
Test name
Test status
Simulation time 393650055 ps
CPU time 1.08 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201168 kb
Host smart-0d35e762-7756-4b58-bdd5-98b1acf0d201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762688436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2762688436
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2703196842
Short name T911
Test name
Test status
Simulation time 311862289 ps
CPU time 1 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201156 kb
Host smart-fd0dcd70-3ece-42cc-a6b1-27112239ee22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703196842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2703196842
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1131082599
Short name T868
Test name
Test status
Simulation time 529142237 ps
CPU time 1.71 seconds
Started Aug 03 04:26:44 PM PDT 24
Finished Aug 03 04:26:46 PM PDT 24
Peak memory 201120 kb
Host smart-1030b0dd-4a58-4dac-9a75-4e8cf8e2d225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131082599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1131082599
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.653302824
Short name T866
Test name
Test status
Simulation time 437996811 ps
CPU time 1.59 seconds
Started Aug 03 04:26:50 PM PDT 24
Finished Aug 03 04:26:52 PM PDT 24
Peak memory 201136 kb
Host smart-4355b66c-e168-4027-b8c4-f9a45065f976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653302824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.653302824
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4040370783
Short name T909
Test name
Test status
Simulation time 356480760 ps
CPU time 0.83 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201180 kb
Host smart-041bd2be-627e-43ff-98b0-472541f7aa4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040370783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4040370783
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1808262431
Short name T826
Test name
Test status
Simulation time 477862877 ps
CPU time 0.92 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201188 kb
Host smart-63b6c704-c233-4b3e-851a-44f791dc51e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808262431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1808262431
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2016353115
Short name T817
Test name
Test status
Simulation time 418645477 ps
CPU time 1.51 seconds
Started Aug 03 04:26:45 PM PDT 24
Finished Aug 03 04:26:46 PM PDT 24
Peak memory 201108 kb
Host smart-fc9cd1ce-e4c2-4a96-820a-76fb5f9c2ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016353115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2016353115
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3687335168
Short name T870
Test name
Test status
Simulation time 1250043171 ps
CPU time 2.55 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201244 kb
Host smart-da63cdae-d4d5-4195-b0f3-d6279c2f527a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687335168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3687335168
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3305667166
Short name T122
Test name
Test status
Simulation time 25874821827 ps
CPU time 20.89 seconds
Started Aug 03 04:26:29 PM PDT 24
Finished Aug 03 04:26:50 PM PDT 24
Peak memory 201344 kb
Host smart-77841fba-e338-44a5-a9e9-8492a5c4148d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305667166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3305667166
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1480984231
Short name T118
Test name
Test status
Simulation time 747034886 ps
CPU time 1.59 seconds
Started Aug 03 04:26:32 PM PDT 24
Finished Aug 03 04:26:33 PM PDT 24
Peak memory 201148 kb
Host smart-ce7e8465-46ff-4f16-a63c-bc84791209c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480984231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1480984231
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2560530414
Short name T844
Test name
Test status
Simulation time 410778344 ps
CPU time 0.97 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 201260 kb
Host smart-e039d08b-4f65-4d22-956a-0b08a82350e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560530414 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2560530414
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2515672997
Short name T819
Test name
Test status
Simulation time 473502385 ps
CPU time 1.33 seconds
Started Aug 03 04:26:31 PM PDT 24
Finished Aug 03 04:26:32 PM PDT 24
Peak memory 201192 kb
Host smart-1891c928-7dce-45a5-b17a-f4ba306fd403
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515672997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2515672997
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2085605828
Short name T885
Test name
Test status
Simulation time 457975522 ps
CPU time 1.7 seconds
Started Aug 03 04:26:29 PM PDT 24
Finished Aug 03 04:26:31 PM PDT 24
Peak memory 201072 kb
Host smart-970f6065-4d5c-453e-8a1f-cea2ad5a5d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085605828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2085605828
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1756541000
Short name T823
Test name
Test status
Simulation time 4113232070 ps
CPU time 16.48 seconds
Started Aug 03 04:26:40 PM PDT 24
Finished Aug 03 04:26:56 PM PDT 24
Peak memory 201332 kb
Host smart-613a604a-9137-4274-ad2f-a3fa31ed34b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756541000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1756541000
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2559329968
Short name T861
Test name
Test status
Simulation time 378830012 ps
CPU time 2.44 seconds
Started Aug 03 04:26:30 PM PDT 24
Finished Aug 03 04:26:32 PM PDT 24
Peak memory 209688 kb
Host smart-35ee3a62-fcdc-4f81-ab40-7c4adcb9b8f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559329968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2559329968
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2591626223
Short name T80
Test name
Test status
Simulation time 8489840554 ps
CPU time 21.88 seconds
Started Aug 03 04:26:30 PM PDT 24
Finished Aug 03 04:26:52 PM PDT 24
Peak memory 201452 kb
Host smart-1f9f6abf-9f7f-48a6-9d13-bec0826cafbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591626223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2591626223
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1432013345
Short name T869
Test name
Test status
Simulation time 526328810 ps
CPU time 0.73 seconds
Started Aug 03 04:26:55 PM PDT 24
Finished Aug 03 04:26:56 PM PDT 24
Peak memory 201088 kb
Host smart-aee0f010-bd7f-4e7b-b574-3599f9be275f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432013345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1432013345
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2836324647
Short name T919
Test name
Test status
Simulation time 405010662 ps
CPU time 1.5 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201188 kb
Host smart-e03f44c7-b732-4eb9-960d-3dbe34850e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836324647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2836324647
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3258571318
Short name T877
Test name
Test status
Simulation time 510388230 ps
CPU time 1.68 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:49 PM PDT 24
Peak memory 201172 kb
Host smart-7f4c29de-3601-49aa-a37e-41b1390e2633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258571318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3258571318
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1816412765
Short name T830
Test name
Test status
Simulation time 372751016 ps
CPU time 0.99 seconds
Started Aug 03 04:26:43 PM PDT 24
Finished Aug 03 04:26:44 PM PDT 24
Peak memory 201140 kb
Host smart-dd0f264b-d852-42e2-922f-84267ca427e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816412765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1816412765
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3470833252
Short name T821
Test name
Test status
Simulation time 409304491 ps
CPU time 0.91 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201200 kb
Host smart-453640ff-f0b4-4653-aba2-985a68bd7961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470833252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3470833252
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.633655478
Short name T906
Test name
Test status
Simulation time 509895530 ps
CPU time 1.72 seconds
Started Aug 03 04:26:46 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201100 kb
Host smart-64d699f1-bf56-4ac4-886e-35c689e625e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633655478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.633655478
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.60243506
Short name T811
Test name
Test status
Simulation time 522580428 ps
CPU time 1.8 seconds
Started Aug 03 04:26:48 PM PDT 24
Finished Aug 03 04:26:50 PM PDT 24
Peak memory 201200 kb
Host smart-e79ec4ad-515c-4853-9b1f-579d3112381e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60243506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.60243506
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2499222323
Short name T905
Test name
Test status
Simulation time 463015225 ps
CPU time 1.65 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 201136 kb
Host smart-640b0042-e0d5-4c52-9e41-c29ed3224dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499222323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2499222323
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2170894855
Short name T845
Test name
Test status
Simulation time 314489917 ps
CPU time 0.92 seconds
Started Aug 03 04:26:43 PM PDT 24
Finished Aug 03 04:26:44 PM PDT 24
Peak memory 201120 kb
Host smart-39f78edc-c451-4d96-a0e0-5e4f6f0dc6e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170894855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2170894855
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3185343930
Short name T815
Test name
Test status
Simulation time 523527708 ps
CPU time 1.77 seconds
Started Aug 03 04:26:48 PM PDT 24
Finished Aug 03 04:26:50 PM PDT 24
Peak memory 201192 kb
Host smart-3b7a2bb1-8c1d-4782-80b4-dc1c74a76a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185343930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3185343930
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3319556631
Short name T71
Test name
Test status
Simulation time 475613120 ps
CPU time 1.53 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201276 kb
Host smart-7da13a52-058e-4bfc-a59d-5ba15a11f1c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319556631 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3319556631
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4083633298
Short name T127
Test name
Test status
Simulation time 414324905 ps
CPU time 1.07 seconds
Started Aug 03 04:26:39 PM PDT 24
Finished Aug 03 04:26:40 PM PDT 24
Peak memory 201132 kb
Host smart-8524ebfb-4183-439d-831b-b0d45c8cb71b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083633298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4083633298
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2800823222
Short name T801
Test name
Test status
Simulation time 329400647 ps
CPU time 0.78 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 201144 kb
Host smart-33968497-ac48-4a05-b69d-095b094bc424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800823222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2800823222
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.171687694
Short name T57
Test name
Test status
Simulation time 5380707765 ps
CPU time 3.88 seconds
Started Aug 03 04:26:35 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201388 kb
Host smart-82c68c47-9545-4a56-be77-7cefdbc801b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171687694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.171687694
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3329424178
Short name T73
Test name
Test status
Simulation time 685120770 ps
CPU time 1.75 seconds
Started Aug 03 04:26:39 PM PDT 24
Finished Aug 03 04:26:41 PM PDT 24
Peak memory 201440 kb
Host smart-b253a7d7-5d54-4e2d-9757-115d16811513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329424178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3329424178
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1049069586
Short name T824
Test name
Test status
Simulation time 8767448590 ps
CPU time 23.44 seconds
Started Aug 03 04:26:40 PM PDT 24
Finished Aug 03 04:27:04 PM PDT 24
Peak memory 201404 kb
Host smart-ccc7db08-4515-4683-8b7a-2912ba103c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049069586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1049069586
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.373556565
Short name T860
Test name
Test status
Simulation time 528683098 ps
CPU time 2.08 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201328 kb
Host smart-357eadd5-a4d4-4c0b-9b1f-11e1ad237f6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373556565 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.373556565
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.917254961
Short name T856
Test name
Test status
Simulation time 495857852 ps
CPU time 1.21 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 201140 kb
Host smart-19ab580f-ccb2-416d-8301-74277288aace
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917254961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.917254961
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.241283725
Short name T863
Test name
Test status
Simulation time 317788582 ps
CPU time 0.79 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:37 PM PDT 24
Peak memory 201120 kb
Host smart-91ff3e7b-b007-43bd-9da2-b20d2ad5badc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241283725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.241283725
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2568494913
Short name T131
Test name
Test status
Simulation time 2073991918 ps
CPU time 7.04 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 201200 kb
Host smart-237f2cd5-54ab-4017-bc4c-018101b7a81c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568494913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2568494913
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.97145126
Short name T895
Test name
Test status
Simulation time 406906406 ps
CPU time 3.05 seconds
Started Aug 03 04:26:35 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 217784 kb
Host smart-fad1c9eb-6290-4a6b-ba4c-88ada8d56c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97145126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.97145126
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1226356080
Short name T881
Test name
Test status
Simulation time 720508056 ps
CPU time 0.93 seconds
Started Aug 03 04:26:40 PM PDT 24
Finished Aug 03 04:26:41 PM PDT 24
Peak memory 201232 kb
Host smart-69408b4b-8c19-426f-bfed-bc838d8110ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226356080 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1226356080
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.513583762
Short name T124
Test name
Test status
Simulation time 978806420 ps
CPU time 0.89 seconds
Started Aug 03 04:26:42 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 201140 kb
Host smart-7c83ce48-51b8-44a7-89db-2bfba5af472f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513583762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.513583762
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.511282016
Short name T812
Test name
Test status
Simulation time 453955071 ps
CPU time 1.59 seconds
Started Aug 03 04:26:42 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 201196 kb
Host smart-7d5a20b2-d240-47aa-9bae-d249cf8b8232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511282016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.511282016
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2085400392
Short name T890
Test name
Test status
Simulation time 2209796095 ps
CPU time 5.62 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:42 PM PDT 24
Peak memory 201180 kb
Host smart-eb334a37-fe79-4e69-8caf-d0637d4b88a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085400392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2085400392
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.696667292
Short name T840
Test name
Test status
Simulation time 633011443 ps
CPU time 1.66 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:40 PM PDT 24
Peak memory 201432 kb
Host smart-aab03275-31b7-451a-b96a-0832356c825f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696667292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.696667292
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.564724932
Short name T79
Test name
Test status
Simulation time 4110177116 ps
CPU time 11.66 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:50 PM PDT 24
Peak memory 201420 kb
Host smart-2c6504aa-052c-4937-9ece-fdfaab436b8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564724932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.564724932
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1059985170
Short name T837
Test name
Test status
Simulation time 448748982 ps
CPU time 1.25 seconds
Started Aug 03 04:26:39 PM PDT 24
Finished Aug 03 04:26:40 PM PDT 24
Peak memory 201236 kb
Host smart-b488fb75-0e19-48f2-95fc-46de589b036c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059985170 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1059985170
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3184158329
Short name T130
Test name
Test status
Simulation time 346347897 ps
CPU time 1.57 seconds
Started Aug 03 04:26:35 PM PDT 24
Finished Aug 03 04:26:37 PM PDT 24
Peak memory 201264 kb
Host smart-3f7cba29-1a35-49e6-89a9-f758b95d2dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184158329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3184158329
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.429241646
Short name T858
Test name
Test status
Simulation time 418341879 ps
CPU time 0.73 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 201072 kb
Host smart-22187c8a-66ab-4f47-96ab-e5ba8ea172d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429241646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.429241646
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2256643805
Short name T865
Test name
Test status
Simulation time 2131604723 ps
CPU time 2.69 seconds
Started Aug 03 04:26:40 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 201108 kb
Host smart-6a40e136-2fad-4768-af5f-e90af1082d90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256643805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2256643805
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1876028322
Short name T899
Test name
Test status
Simulation time 432882674 ps
CPU time 2.55 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201436 kb
Host smart-9fd9ee61-3ab8-4e69-899b-c59345f2ab06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876028322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1876028322
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.401492636
Short name T339
Test name
Test status
Simulation time 4179902902 ps
CPU time 9.59 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201432 kb
Host smart-9ae97f6a-82b0-4647-a9ef-51a6a9e00e84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401492636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.401492636
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3912982541
Short name T883
Test name
Test status
Simulation time 458069026 ps
CPU time 1.33 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 201256 kb
Host smart-e6554bd5-c46c-46a5-8d85-0b6cf12f4a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912982541 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3912982541
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1694086551
Short name T910
Test name
Test status
Simulation time 366749256 ps
CPU time 1.49 seconds
Started Aug 03 04:26:37 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 201176 kb
Host smart-803eaea2-2c2a-47dc-a625-36ff86a82899
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694086551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1694086551
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.39528184
Short name T805
Test name
Test status
Simulation time 400894043 ps
CPU time 0.83 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 201160 kb
Host smart-08c9946a-8e51-4227-b98f-004157057021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39528184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.39528184
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4149780153
Short name T60
Test name
Test status
Simulation time 1914907944 ps
CPU time 4.36 seconds
Started Aug 03 04:26:39 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 201124 kb
Host smart-ab70a569-39d9-473d-a77e-75c0af31c018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149780153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4149780153
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2313482989
Short name T828
Test name
Test status
Simulation time 387381269 ps
CPU time 1.76 seconds
Started Aug 03 04:26:38 PM PDT 24
Finished Aug 03 04:26:40 PM PDT 24
Peak memory 201452 kb
Host smart-5918bcea-3cde-4592-8d7e-22449911b280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313482989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2313482989
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4128231967
Short name T338
Test name
Test status
Simulation time 4102481074 ps
CPU time 10.84 seconds
Started Aug 03 04:26:36 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 201484 kb
Host smart-c9672d9c-3b08-4b28-8621-5a4b2be7d11d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128231967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4128231967
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1448947441
Short name T463
Test name
Test status
Simulation time 355440214 ps
CPU time 1.45 seconds
Started Aug 03 05:28:27 PM PDT 24
Finished Aug 03 05:28:29 PM PDT 24
Peak memory 201256 kb
Host smart-b88a5b39-b9f9-4820-ba2d-e362f21b17fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448947441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1448947441
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2798767571
Short name T476
Test name
Test status
Simulation time 330100927303 ps
CPU time 457.06 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:36:06 PM PDT 24
Peak memory 201428 kb
Host smart-97fd4754-a548-40ab-958e-95fc37d761fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798767571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2798767571
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2303649209
Short name T682
Test name
Test status
Simulation time 176748632418 ps
CPU time 194.77 seconds
Started Aug 03 05:28:27 PM PDT 24
Finished Aug 03 05:31:42 PM PDT 24
Peak memory 201504 kb
Host smart-7e8f1722-5038-4f52-a2bc-f018c80161b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303649209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2303649209
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2173994397
Short name T680
Test name
Test status
Simulation time 163217684870 ps
CPU time 96.15 seconds
Started Aug 03 05:28:28 PM PDT 24
Finished Aug 03 05:30:04 PM PDT 24
Peak memory 201432 kb
Host smart-f55dad02-a4a7-47ed-93c7-beb1225cbdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173994397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2173994397
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2377802440
Short name T378
Test name
Test status
Simulation time 158948571215 ps
CPU time 47.27 seconds
Started Aug 03 05:28:27 PM PDT 24
Finished Aug 03 05:29:15 PM PDT 24
Peak memory 201508 kb
Host smart-a6ba8c55-6314-497f-a980-334928fcb677
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377802440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2377802440
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1502802303
Short name T298
Test name
Test status
Simulation time 168144619534 ps
CPU time 56.19 seconds
Started Aug 03 05:28:24 PM PDT 24
Finished Aug 03 05:29:20 PM PDT 24
Peak memory 201420 kb
Host smart-f0ab37dd-3b00-4ab8-bf8a-a070a007fab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502802303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1502802303
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1616122711
Short name T487
Test name
Test status
Simulation time 490562797758 ps
CPU time 298.09 seconds
Started Aug 03 05:28:28 PM PDT 24
Finished Aug 03 05:33:26 PM PDT 24
Peak memory 201400 kb
Host smart-8d310554-974d-451d-8002-20a787743935
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616122711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1616122711
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1956620779
Short name T657
Test name
Test status
Simulation time 207672451658 ps
CPU time 127.56 seconds
Started Aug 03 05:28:26 PM PDT 24
Finished Aug 03 05:30:34 PM PDT 24
Peak memory 201472 kb
Host smart-4785af76-aa38-455e-9434-f078afc90cfe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956620779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1956620779
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3881367264
Short name T506
Test name
Test status
Simulation time 204917950236 ps
CPU time 419.39 seconds
Started Aug 03 05:28:30 PM PDT 24
Finished Aug 03 05:35:30 PM PDT 24
Peak memory 201396 kb
Host smart-e1e6c97e-5250-4494-b3c3-374de200b0aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881367264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3881367264
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.4211417172
Short name T347
Test name
Test status
Simulation time 104307619901 ps
CPU time 577.01 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:38:06 PM PDT 24
Peak memory 201820 kb
Host smart-1c53e735-b5ca-4b1b-b8c1-4722a9979436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211417172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.4211417172
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3971069841
Short name T3
Test name
Test status
Simulation time 30212053511 ps
CPU time 67.16 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:29:37 PM PDT 24
Peak memory 201256 kb
Host smart-c07d224a-d02c-444b-b80e-1b51a803c840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971069841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3971069841
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.631498116
Short name T708
Test name
Test status
Simulation time 4360583480 ps
CPU time 11.07 seconds
Started Aug 03 05:28:26 PM PDT 24
Finished Aug 03 05:28:37 PM PDT 24
Peak memory 201328 kb
Host smart-04251391-d7b2-423f-aeae-be772b44ad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631498116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.631498116
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1968098827
Short name T82
Test name
Test status
Simulation time 8251983987 ps
CPU time 4.6 seconds
Started Aug 03 05:28:27 PM PDT 24
Finished Aug 03 05:28:32 PM PDT 24
Peak memory 217180 kb
Host smart-32a7f4c8-0c8b-40c2-a960-3caf6d134f18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968098827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1968098827
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3603424503
Short name T41
Test name
Test status
Simulation time 5597066540 ps
CPU time 1.94 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:28:31 PM PDT 24
Peak memory 201336 kb
Host smart-0ed93341-77df-4ebf-b853-a085a5a183be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603424503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3603424503
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3958736669
Short name T45
Test name
Test status
Simulation time 341073555465 ps
CPU time 297.35 seconds
Started Aug 03 05:28:30 PM PDT 24
Finished Aug 03 05:33:28 PM PDT 24
Peak memory 218248 kb
Host smart-906536f0-2615-49d9-a582-0eaf1c732160
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958736669 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3958736669
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2186642056
Short name T624
Test name
Test status
Simulation time 407597348 ps
CPU time 0.84 seconds
Started Aug 03 05:28:30 PM PDT 24
Finished Aug 03 05:28:31 PM PDT 24
Peak memory 201196 kb
Host smart-85d11b8f-578c-4cd6-bb5d-87bf7d77901e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186642056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2186642056
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.495993675
Short name T110
Test name
Test status
Simulation time 363896973409 ps
CPU time 379.61 seconds
Started Aug 03 05:28:27 PM PDT 24
Finished Aug 03 05:34:47 PM PDT 24
Peak memory 201500 kb
Host smart-5c866634-d522-4ea5-8003-44e2a129f4a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495993675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.495993675
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1183545158
Short name T609
Test name
Test status
Simulation time 327814691959 ps
CPU time 186.38 seconds
Started Aug 03 05:28:30 PM PDT 24
Finished Aug 03 05:31:37 PM PDT 24
Peak memory 201508 kb
Host smart-5c28b082-4854-4d62-9411-11dfaca6eee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183545158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1183545158
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.772783193
Short name T750
Test name
Test status
Simulation time 159744296191 ps
CPU time 387.13 seconds
Started Aug 03 05:28:30 PM PDT 24
Finished Aug 03 05:34:58 PM PDT 24
Peak memory 201468 kb
Host smart-8e3fdf70-4822-4bf7-a4b0-ad27c6bc124d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=772783193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.772783193
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1845834934
Short name T181
Test name
Test status
Simulation time 333551299984 ps
CPU time 195.67 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:31:45 PM PDT 24
Peak memory 201396 kb
Host smart-8ef54a45-457c-4e0e-8caf-2a6aa00c2869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845834934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1845834934
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1218970343
Short name T112
Test name
Test status
Simulation time 502753645226 ps
CPU time 1232.14 seconds
Started Aug 03 05:28:30 PM PDT 24
Finished Aug 03 05:49:02 PM PDT 24
Peak memory 201476 kb
Host smart-5a89b10a-5f65-4d98-96cc-a0c0c9e61da2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218970343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1218970343
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3182927581
Short name T491
Test name
Test status
Simulation time 385551691180 ps
CPU time 227.64 seconds
Started Aug 03 05:28:30 PM PDT 24
Finished Aug 03 05:32:18 PM PDT 24
Peak memory 201384 kb
Host smart-57ac1834-ed6b-4480-ae08-20ba4e3d55f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182927581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3182927581
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1329399106
Short name T730
Test name
Test status
Simulation time 405219880996 ps
CPU time 895.86 seconds
Started Aug 03 05:28:26 PM PDT 24
Finished Aug 03 05:43:22 PM PDT 24
Peak memory 201368 kb
Host smart-fca7adb5-b603-4ffc-a750-c927edf48b40
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329399106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1329399106
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.374108880
Short name T198
Test name
Test status
Simulation time 74479770405 ps
CPU time 364.49 seconds
Started Aug 03 05:28:28 PM PDT 24
Finished Aug 03 05:34:33 PM PDT 24
Peak memory 201804 kb
Host smart-b698df33-ef42-4884-8f8b-6eb51ee45558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374108880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.374108880
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.37164096
Short name T11
Test name
Test status
Simulation time 43804611643 ps
CPU time 102.58 seconds
Started Aug 03 05:28:30 PM PDT 24
Finished Aug 03 05:30:13 PM PDT 24
Peak memory 201356 kb
Host smart-b5ceeb56-cd49-4f7d-967c-0e9b642f41e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37164096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.37164096
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1914202847
Short name T396
Test name
Test status
Simulation time 3517156098 ps
CPU time 4.51 seconds
Started Aug 03 05:28:27 PM PDT 24
Finished Aug 03 05:28:31 PM PDT 24
Peak memory 201332 kb
Host smart-259148f4-9390-46fe-bd29-496e7d3e381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914202847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1914202847
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2014609027
Short name T81
Test name
Test status
Simulation time 4582863556 ps
CPU time 3.28 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:28:33 PM PDT 24
Peak memory 217096 kb
Host smart-67bc0948-a8c2-4bbf-8d10-23711778ad5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014609027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2014609027
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.663192379
Short name T599
Test name
Test status
Simulation time 5975781484 ps
CPU time 14.36 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:28:44 PM PDT 24
Peak memory 201340 kb
Host smart-4ea06493-65eb-4590-b6c6-e09106007a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663192379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.663192379
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3843711480
Short name T627
Test name
Test status
Simulation time 90846915951 ps
CPU time 104.24 seconds
Started Aug 03 05:28:28 PM PDT 24
Finished Aug 03 05:30:13 PM PDT 24
Peak memory 218252 kb
Host smart-33deedc5-76e3-4a44-9ee1-05856520600b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843711480 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3843711480
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3950455306
Short name T615
Test name
Test status
Simulation time 499254314 ps
CPU time 1.76 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:29:06 PM PDT 24
Peak memory 201248 kb
Host smart-d4b8f1da-87af-4d93-9c92-8b5e51834957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950455306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3950455306
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3574684869
Short name T645
Test name
Test status
Simulation time 528112631688 ps
CPU time 392.95 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:35:37 PM PDT 24
Peak memory 201476 kb
Host smart-2ce8f134-0472-4d74-bf97-988f2079c83a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574684869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3574684869
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1768144227
Short name T719
Test name
Test status
Simulation time 182244271664 ps
CPU time 402.86 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:35:47 PM PDT 24
Peak memory 201480 kb
Host smart-97132675-aeb3-4d92-82d8-9322a8576e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768144227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1768144227
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.549458172
Short name T220
Test name
Test status
Simulation time 486259678061 ps
CPU time 343.09 seconds
Started Aug 03 05:29:02 PM PDT 24
Finished Aug 03 05:34:46 PM PDT 24
Peak memory 201436 kb
Host smart-d810e0df-f4b9-4450-b90c-2caf197ede17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549458172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.549458172
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2866814981
Short name T757
Test name
Test status
Simulation time 159091326098 ps
CPU time 361.08 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:35:05 PM PDT 24
Peak memory 201452 kb
Host smart-d8143071-f4db-4f16-8344-4cae2411ee1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866814981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2866814981
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1359574733
Short name T502
Test name
Test status
Simulation time 331843809869 ps
CPU time 431.38 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:36:16 PM PDT 24
Peak memory 201416 kb
Host smart-dab9b738-8f7e-40a8-af30-4501e9a3b7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359574733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1359574733
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1150145041
Short name T428
Test name
Test status
Simulation time 326818589799 ps
CPU time 320.58 seconds
Started Aug 03 05:29:02 PM PDT 24
Finished Aug 03 05:34:23 PM PDT 24
Peak memory 201400 kb
Host smart-6688fd68-5c4e-455b-bc9c-777fc895dba3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150145041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1150145041
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1812677462
Short name T176
Test name
Test status
Simulation time 527876655948 ps
CPU time 343 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:34:47 PM PDT 24
Peak memory 201488 kb
Host smart-5b2ea8bb-e73c-4a7d-a0a5-5c69ccbac369
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812677462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1812677462
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3723406859
Short name T711
Test name
Test status
Simulation time 195177075635 ps
CPU time 414.77 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:35:59 PM PDT 24
Peak memory 201384 kb
Host smart-1afa2f5d-9b79-4784-8f9e-0cae9b2dceb6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723406859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3723406859
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2439079950
Short name T195
Test name
Test status
Simulation time 79907624581 ps
CPU time 431.28 seconds
Started Aug 03 05:29:05 PM PDT 24
Finished Aug 03 05:36:16 PM PDT 24
Peak memory 201840 kb
Host smart-ed0180bd-2974-4346-af68-b4bb050103d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439079950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2439079950
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1777158291
Short name T607
Test name
Test status
Simulation time 25923708070 ps
CPU time 55.34 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:30:01 PM PDT 24
Peak memory 201372 kb
Host smart-2d83fa1b-d4db-461e-9142-72c58aa29f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777158291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1777158291
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.504170229
Short name T772
Test name
Test status
Simulation time 3392334784 ps
CPU time 2.4 seconds
Started Aug 03 05:29:01 PM PDT 24
Finished Aug 03 05:29:03 PM PDT 24
Peak memory 201332 kb
Host smart-f88e9202-3ab5-428d-8370-9dd1f98a7b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504170229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.504170229
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.4291434859
Short name T88
Test name
Test status
Simulation time 5740974553 ps
CPU time 4.29 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:29:08 PM PDT 24
Peak memory 201392 kb
Host smart-3ccd7f9e-804e-4d74-bfec-79d47976a27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291434859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.4291434859
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3688883811
Short name T798
Test name
Test status
Simulation time 376346213882 ps
CPU time 239.33 seconds
Started Aug 03 05:29:05 PM PDT 24
Finished Aug 03 05:33:04 PM PDT 24
Peak memory 201408 kb
Host smart-f6355d9d-661e-4f49-bc55-7d2f08677fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688883811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3688883811
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2252728268
Short name T194
Test name
Test status
Simulation time 151807262213 ps
CPU time 91.37 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:30:35 PM PDT 24
Peak memory 209784 kb
Host smart-e08ea0b7-e172-4821-a72a-ccdb7e5d8a74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252728268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2252728268
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1015636682
Short name T439
Test name
Test status
Simulation time 473390030 ps
CPU time 0.68 seconds
Started Aug 03 05:29:03 PM PDT 24
Finished Aug 03 05:29:04 PM PDT 24
Peak memory 201220 kb
Host smart-3b48edc4-25a0-496d-aa43-c83dfd2319ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015636682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1015636682
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.410040057
Short name T144
Test name
Test status
Simulation time 169318250941 ps
CPU time 103.13 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:30:49 PM PDT 24
Peak memory 201444 kb
Host smart-eae0313f-4340-4b4b-a010-258870fa0978
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410040057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.410040057
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.582154761
Short name T232
Test name
Test status
Simulation time 163693264490 ps
CPU time 93.39 seconds
Started Aug 03 05:29:03 PM PDT 24
Finished Aug 03 05:30:37 PM PDT 24
Peak memory 201444 kb
Host smart-13cece18-3b6f-4159-8cab-fa3639665ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582154761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.582154761
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2278414366
Short name T746
Test name
Test status
Simulation time 170844431146 ps
CPU time 101.68 seconds
Started Aug 03 05:29:05 PM PDT 24
Finished Aug 03 05:30:47 PM PDT 24
Peak memory 201448 kb
Host smart-c6fff976-97f2-483b-ad00-c13c19c2ddfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278414366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2278414366
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4065398784
Short name T552
Test name
Test status
Simulation time 483360664940 ps
CPU time 1135.19 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:48:00 PM PDT 24
Peak memory 201640 kb
Host smart-c5ca243c-6ba1-4120-92e7-c90e3d911bfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065398784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.4065398784
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1713102728
Short name T393
Test name
Test status
Simulation time 330633842654 ps
CPU time 712.7 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:40:57 PM PDT 24
Peak memory 201432 kb
Host smart-ffa1feea-04d3-4a6f-add7-3091aa39e6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713102728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1713102728
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3210597017
Short name T626
Test name
Test status
Simulation time 159942778936 ps
CPU time 391.53 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:35:36 PM PDT 24
Peak memory 201348 kb
Host smart-cfad1846-a114-4873-94c5-be20a173453b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210597017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3210597017
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2933105550
Short name T245
Test name
Test status
Simulation time 189836148135 ps
CPU time 421.6 seconds
Started Aug 03 05:29:07 PM PDT 24
Finished Aug 03 05:36:09 PM PDT 24
Peak memory 201516 kb
Host smart-7913aafe-7d99-442a-add0-e2794a9ed8ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933105550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2933105550
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3249943001
Short name T149
Test name
Test status
Simulation time 198064595355 ps
CPU time 233.5 seconds
Started Aug 03 05:29:03 PM PDT 24
Finished Aug 03 05:32:56 PM PDT 24
Peak memory 201428 kb
Host smart-4a8d78b9-a78c-45b9-a802-81370e16a25a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249943001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3249943001
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.464835454
Short name T775
Test name
Test status
Simulation time 111445623440 ps
CPU time 357.37 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:35:02 PM PDT 24
Peak memory 201920 kb
Host smart-4f1c0f57-06dd-419a-8920-b8886d249e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464835454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.464835454
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2633205412
Short name T608
Test name
Test status
Simulation time 24733370551 ps
CPU time 27.1 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:29:32 PM PDT 24
Peak memory 201368 kb
Host smart-f656fcfb-11fb-48e0-9c72-172a74ab9b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633205412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2633205412
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2304015724
Short name T471
Test name
Test status
Simulation time 4357894551 ps
CPU time 3.5 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:29:08 PM PDT 24
Peak memory 201388 kb
Host smart-24bbc3a7-a545-4f6c-b288-de3d54013da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304015724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2304015724
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.49569612
Short name T678
Test name
Test status
Simulation time 6027473051 ps
CPU time 4.11 seconds
Started Aug 03 05:29:01 PM PDT 24
Finished Aug 03 05:29:05 PM PDT 24
Peak memory 201340 kb
Host smart-1ea58b03-ce6c-4400-bba0-b85f49a0a1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49569612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.49569612
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.4136365185
Short name T453
Test name
Test status
Simulation time 457422087 ps
CPU time 1.7 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:29:05 PM PDT 24
Peak memory 201208 kb
Host smart-2d5db89e-8ca0-4ba2-8605-9788fdfd9519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136365185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.4136365185
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1348622467
Short name T777
Test name
Test status
Simulation time 330541824320 ps
CPU time 739.72 seconds
Started Aug 03 05:29:01 PM PDT 24
Finished Aug 03 05:41:21 PM PDT 24
Peak memory 201480 kb
Host smart-6e881025-1f19-443c-b592-c9393ff1a759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348622467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1348622467
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.877291046
Short name T769
Test name
Test status
Simulation time 340529078543 ps
CPU time 782.63 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:42:07 PM PDT 24
Peak memory 201424 kb
Host smart-b9ccceb3-7222-4eb0-9307-15bbb7c3dd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877291046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.877291046
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.46231368
Short name T733
Test name
Test status
Simulation time 493729552268 ps
CPU time 1113.38 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:47:37 PM PDT 24
Peak memory 201408 kb
Host smart-3d668113-a8c7-4a7d-9689-9c7c5f4d1d28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=46231368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt
_fixed.46231368
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.573461641
Short name T167
Test name
Test status
Simulation time 332146779984 ps
CPU time 137.12 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:31:21 PM PDT 24
Peak memory 201436 kb
Host smart-90dad339-7f73-45de-a6f8-b1d294dc0348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573461641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.573461641
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2305627790
Short name T115
Test name
Test status
Simulation time 163079001637 ps
CPU time 105.32 seconds
Started Aug 03 05:29:03 PM PDT 24
Finished Aug 03 05:30:48 PM PDT 24
Peak memory 201456 kb
Host smart-51004d22-04c2-456f-bce4-3d78a92059f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305627790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2305627790
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3379544623
Short name T510
Test name
Test status
Simulation time 214166178741 ps
CPU time 508.67 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:37:32 PM PDT 24
Peak memory 201444 kb
Host smart-16fed52c-82a8-4043-9750-9d4f52f3ba27
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379544623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3379544623
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3753443618
Short name T202
Test name
Test status
Simulation time 131530059601 ps
CPU time 706.89 seconds
Started Aug 03 05:29:03 PM PDT 24
Finished Aug 03 05:40:50 PM PDT 24
Peak memory 201816 kb
Host smart-07a40c5a-7dfd-4bf7-b201-255319714590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753443618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3753443618
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3012333307
Short name T610
Test name
Test status
Simulation time 32280949171 ps
CPU time 71.59 seconds
Started Aug 03 05:29:03 PM PDT 24
Finished Aug 03 05:30:15 PM PDT 24
Peak memory 201508 kb
Host smart-d44d3581-ff0c-4a0b-a093-c9bfbbd20375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012333307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3012333307
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3984237451
Short name T648
Test name
Test status
Simulation time 4083437343 ps
CPU time 2.74 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:29:09 PM PDT 24
Peak memory 201348 kb
Host smart-11b23a0c-06f1-4c68-ba12-1cf6772b3aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984237451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3984237451
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2990063046
Short name T495
Test name
Test status
Simulation time 5678846080 ps
CPU time 12.67 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:29:18 PM PDT 24
Peak memory 201376 kb
Host smart-bf4ec69d-ce82-4d1a-8850-570f0d0f03f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990063046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2990063046
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1663232748
Short name T258
Test name
Test status
Simulation time 196878984893 ps
CPU time 114.4 seconds
Started Aug 03 05:29:02 PM PDT 24
Finished Aug 03 05:30:56 PM PDT 24
Peak memory 201440 kb
Host smart-e637b843-ca17-4a54-822f-5a9053d1f378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663232748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1663232748
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.401845250
Short name T524
Test name
Test status
Simulation time 494920518 ps
CPU time 1.17 seconds
Started Aug 03 05:29:08 PM PDT 24
Finished Aug 03 05:29:09 PM PDT 24
Peak memory 201196 kb
Host smart-d15b5180-f126-48a4-8987-6dfedcef0ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401845250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.401845250
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3495517159
Short name T713
Test name
Test status
Simulation time 484801734393 ps
CPU time 328.62 seconds
Started Aug 03 05:29:12 PM PDT 24
Finished Aug 03 05:34:41 PM PDT 24
Peak memory 201388 kb
Host smart-058c1039-ad40-4a5b-9704-b71a3885e166
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495517159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3495517159
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2624941549
Short name T604
Test name
Test status
Simulation time 164936645155 ps
CPU time 186.6 seconds
Started Aug 03 05:29:08 PM PDT 24
Finished Aug 03 05:32:14 PM PDT 24
Peak memory 201448 kb
Host smart-9fae9bad-099f-4d1d-848e-4fff060c990c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624941549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2624941549
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.330072259
Short name T791
Test name
Test status
Simulation time 161591540491 ps
CPU time 40.53 seconds
Started Aug 03 05:29:08 PM PDT 24
Finished Aug 03 05:29:49 PM PDT 24
Peak memory 201392 kb
Host smart-b0537fd3-a6a6-4ed1-8c78-d918b83f0cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330072259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.330072259
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1460082673
Short name T86
Test name
Test status
Simulation time 162352651580 ps
CPU time 346.05 seconds
Started Aug 03 05:29:10 PM PDT 24
Finished Aug 03 05:34:57 PM PDT 24
Peak memory 201396 kb
Host smart-67eb421f-4f4b-453f-a773-7b2f559ff890
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460082673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1460082673
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2900640456
Short name T295
Test name
Test status
Simulation time 176075594780 ps
CPU time 381.73 seconds
Started Aug 03 05:29:10 PM PDT 24
Finished Aug 03 05:35:32 PM PDT 24
Peak memory 201456 kb
Host smart-41fd3e7d-bf96-4679-9023-a7f555919d68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900640456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2900640456
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.918797622
Short name T794
Test name
Test status
Simulation time 605925891445 ps
CPU time 728.76 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:41:13 PM PDT 24
Peak memory 201380 kb
Host smart-a32003d1-cd2a-4347-873d-fa30cc109749
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918797622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.918797622
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1326429946
Short name T355
Test name
Test status
Simulation time 94603082727 ps
CPU time 480.8 seconds
Started Aug 03 05:29:05 PM PDT 24
Finished Aug 03 05:37:06 PM PDT 24
Peak memory 201808 kb
Host smart-495aee6b-9dff-4278-a85d-f57c3a3e89e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326429946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1326429946
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3017726098
Short name T31
Test name
Test status
Simulation time 40443720118 ps
CPU time 90.6 seconds
Started Aug 03 05:29:05 PM PDT 24
Finished Aug 03 05:30:36 PM PDT 24
Peak memory 201324 kb
Host smart-6cbe0b53-65db-4825-a4c9-0aadc8d91490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017726098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3017726098
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.574873252
Short name T356
Test name
Test status
Simulation time 4155304352 ps
CPU time 5.28 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:29:11 PM PDT 24
Peak memory 201336 kb
Host smart-87af78f1-8469-456e-a170-c4dcd1590b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574873252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.574873252
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.13803843
Short name T474
Test name
Test status
Simulation time 5612373778 ps
CPU time 4.13 seconds
Started Aug 03 05:29:05 PM PDT 24
Finished Aug 03 05:29:10 PM PDT 24
Peak memory 201332 kb
Host smart-ce152fc9-714b-4c0a-aa7b-73590ae02d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13803843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.13803843
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1808741626
Short name T493
Test name
Test status
Simulation time 175859749696 ps
CPU time 397.91 seconds
Started Aug 03 05:29:08 PM PDT 24
Finished Aug 03 05:35:46 PM PDT 24
Peak memory 201504 kb
Host smart-d3e275a8-3444-4f57-89b8-ee2c7d6e4f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808741626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1808741626
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2844919206
Short name T744
Test name
Test status
Simulation time 413272615 ps
CPU time 1.6 seconds
Started Aug 03 05:29:12 PM PDT 24
Finished Aug 03 05:29:13 PM PDT 24
Peak memory 201168 kb
Host smart-a1fde534-578a-48fc-85bd-c56c2f27211b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844919206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2844919206
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2763831112
Short name T321
Test name
Test status
Simulation time 553812146634 ps
CPU time 76.46 seconds
Started Aug 03 05:29:08 PM PDT 24
Finished Aug 03 05:30:24 PM PDT 24
Peak memory 201436 kb
Host smart-7ca17a71-61e3-4668-8e52-5a67ba9d49b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763831112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2763831112
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1020043669
Short name T291
Test name
Test status
Simulation time 355231689008 ps
CPU time 825.89 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:42:53 PM PDT 24
Peak memory 201476 kb
Host smart-baddb5e8-eb31-407a-83ea-0faabb48c597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020043669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1020043669
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3635055667
Short name T255
Test name
Test status
Simulation time 492321844392 ps
CPU time 556.5 seconds
Started Aug 03 05:29:11 PM PDT 24
Finished Aug 03 05:38:27 PM PDT 24
Peak memory 201480 kb
Host smart-436493a3-ce45-472f-b574-627f947576d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635055667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3635055667
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3825558206
Short name T519
Test name
Test status
Simulation time 168216679239 ps
CPU time 54.11 seconds
Started Aug 03 05:29:08 PM PDT 24
Finished Aug 03 05:30:02 PM PDT 24
Peak memory 201520 kb
Host smart-a8db26be-ac75-460a-aea9-9f8415cbd8d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825558206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3825558206
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2733162863
Short name T165
Test name
Test status
Simulation time 487780894648 ps
CPU time 528.95 seconds
Started Aug 03 05:29:10 PM PDT 24
Finished Aug 03 05:38:00 PM PDT 24
Peak memory 201404 kb
Host smart-5237b1ff-9acc-4d9b-86a4-9cfcb04aabda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733162863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2733162863
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.814669708
Short name T389
Test name
Test status
Simulation time 330447330736 ps
CPU time 640.42 seconds
Started Aug 03 05:29:08 PM PDT 24
Finished Aug 03 05:39:49 PM PDT 24
Peak memory 201400 kb
Host smart-6e8eb43b-25fe-4674-bc6a-1dd7c485824f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=814669708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.814669708
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3406605216
Short name T634
Test name
Test status
Simulation time 259252717719 ps
CPU time 234.95 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:33:01 PM PDT 24
Peak memory 201352 kb
Host smart-2edb1b93-5c0f-4781-a203-076cacb2088a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406605216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3406605216
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3090432546
Short name T759
Test name
Test status
Simulation time 397204904420 ps
CPU time 62.52 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:30:09 PM PDT 24
Peak memory 201452 kb
Host smart-05f4e57e-b67f-49b0-9b91-ebb3d051b8c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090432546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3090432546
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3151584143
Short name T534
Test name
Test status
Simulation time 133572143588 ps
CPU time 532.29 seconds
Started Aug 03 05:29:06 PM PDT 24
Finished Aug 03 05:37:59 PM PDT 24
Peak memory 201888 kb
Host smart-c714bb15-b63a-4589-92a5-aee69f0f5fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151584143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3151584143
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2862010806
Short name T668
Test name
Test status
Simulation time 42600001500 ps
CPU time 104.81 seconds
Started Aug 03 05:29:07 PM PDT 24
Finished Aug 03 05:30:52 PM PDT 24
Peak memory 201308 kb
Host smart-d57055b0-41ad-48ed-9e30-f9256d47fcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862010806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2862010806
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2199300769
Short name T413
Test name
Test status
Simulation time 3742488052 ps
CPU time 2.91 seconds
Started Aug 03 05:29:12 PM PDT 24
Finished Aug 03 05:29:15 PM PDT 24
Peak memory 201264 kb
Host smart-e5108415-3c1d-4990-add0-59d60291c4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199300769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2199300769
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.135848636
Short name T412
Test name
Test status
Simulation time 5776844063 ps
CPU time 2.62 seconds
Started Aug 03 05:29:10 PM PDT 24
Finished Aug 03 05:29:13 PM PDT 24
Peak memory 201344 kb
Host smart-4969778f-1a23-4622-a0b4-78ca2776a040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135848636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.135848636
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3286290039
Short name T324
Test name
Test status
Simulation time 20354138380 ps
CPU time 44.03 seconds
Started Aug 03 05:29:09 PM PDT 24
Finished Aug 03 05:29:53 PM PDT 24
Peak memory 209792 kb
Host smart-99f2be69-2a98-4296-a5bb-bbbb42bc2c76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286290039 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3286290039
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2058356262
Short name T675
Test name
Test status
Simulation time 365335350692 ps
CPU time 210.57 seconds
Started Aug 03 05:29:11 PM PDT 24
Finished Aug 03 05:32:42 PM PDT 24
Peak memory 201448 kb
Host smart-a471ffa1-1c8b-41bc-8e55-7f5b5f251411
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058356262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2058356262
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1166540581
Short name T654
Test name
Test status
Simulation time 164719489665 ps
CPU time 311.32 seconds
Started Aug 03 05:29:13 PM PDT 24
Finished Aug 03 05:34:25 PM PDT 24
Peak memory 201404 kb
Host smart-667d7031-b7f7-42be-9118-6bc6a0a479ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166540581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1166540581
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.35905393
Short name T29
Test name
Test status
Simulation time 488974376692 ps
CPU time 1166.28 seconds
Started Aug 03 05:29:10 PM PDT 24
Finished Aug 03 05:48:36 PM PDT 24
Peak memory 201480 kb
Host smart-ac557479-9351-4046-a5d5-830a5c44e867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35905393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.35905393
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1057059603
Short name T649
Test name
Test status
Simulation time 162495317119 ps
CPU time 199.56 seconds
Started Aug 03 05:29:14 PM PDT 24
Finished Aug 03 05:32:34 PM PDT 24
Peak memory 201444 kb
Host smart-4ee891fe-132e-42d8-9034-abaa9779de22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057059603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1057059603
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2392061698
Short name T614
Test name
Test status
Simulation time 328174519524 ps
CPU time 169.32 seconds
Started Aug 03 05:29:10 PM PDT 24
Finished Aug 03 05:32:00 PM PDT 24
Peak memory 201464 kb
Host smart-b4aa076a-abdf-45c2-af48-a589be70c590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392061698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2392061698
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1145855465
Short name T585
Test name
Test status
Simulation time 338445110991 ps
CPU time 393.61 seconds
Started Aug 03 05:29:12 PM PDT 24
Finished Aug 03 05:35:46 PM PDT 24
Peak memory 201484 kb
Host smart-24c83f71-2b39-4992-a4ae-45fc9ba3a533
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145855465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1145855465
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2412436157
Short name T361
Test name
Test status
Simulation time 399550394390 ps
CPU time 430.83 seconds
Started Aug 03 05:29:13 PM PDT 24
Finished Aug 03 05:36:24 PM PDT 24
Peak memory 201580 kb
Host smart-394f41c3-ba13-4a13-a41f-4f3ce55ac6c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412436157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2412436157
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3952810252
Short name T343
Test name
Test status
Simulation time 119260654519 ps
CPU time 573.35 seconds
Started Aug 03 05:29:10 PM PDT 24
Finished Aug 03 05:38:43 PM PDT 24
Peak memory 201788 kb
Host smart-59de185a-3e91-41ee-9fac-4ee0a06a7ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952810252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3952810252
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2670988074
Short name T532
Test name
Test status
Simulation time 36572529848 ps
CPU time 63.91 seconds
Started Aug 03 05:29:12 PM PDT 24
Finished Aug 03 05:30:16 PM PDT 24
Peak memory 201336 kb
Host smart-40be5167-0807-443e-ae41-abea966b8d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670988074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2670988074
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3276761868
Short name T482
Test name
Test status
Simulation time 4497632260 ps
CPU time 6.76 seconds
Started Aug 03 05:29:11 PM PDT 24
Finished Aug 03 05:29:18 PM PDT 24
Peak memory 201364 kb
Host smart-22249574-4ede-4371-8100-681d78f9f9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276761868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3276761868
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.816905706
Short name T681
Test name
Test status
Simulation time 5822899511 ps
CPU time 13.24 seconds
Started Aug 03 05:29:12 PM PDT 24
Finished Aug 03 05:29:25 PM PDT 24
Peak memory 201388 kb
Host smart-1bc6181f-4446-4bc3-a1dc-c3d0b9d444e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816905706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.816905706
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2829553564
Short name T465
Test name
Test status
Simulation time 172357583361 ps
CPU time 109.34 seconds
Started Aug 03 05:29:10 PM PDT 24
Finished Aug 03 05:31:00 PM PDT 24
Peak memory 201428 kb
Host smart-d40ae857-79c9-4d45-b22e-0889ec98c6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829553564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2829553564
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1275515943
Short name T345
Test name
Test status
Simulation time 1133869845080 ps
CPU time 501.46 seconds
Started Aug 03 05:29:12 PM PDT 24
Finished Aug 03 05:37:33 PM PDT 24
Peak memory 202296 kb
Host smart-b5798bb7-19c3-417d-b484-6e94826ae61e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275515943 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1275515943
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2304733284
Short name T595
Test name
Test status
Simulation time 441746374 ps
CPU time 0.91 seconds
Started Aug 03 05:29:20 PM PDT 24
Finished Aug 03 05:29:21 PM PDT 24
Peak memory 201196 kb
Host smart-653250a9-6343-41d6-92dd-6fd65ec2e628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304733284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2304733284
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1547072266
Short name T513
Test name
Test status
Simulation time 164959652067 ps
CPU time 89.26 seconds
Started Aug 03 05:29:16 PM PDT 24
Finished Aug 03 05:30:45 PM PDT 24
Peak memory 201456 kb
Host smart-ca50c225-ec42-41ef-885e-97140429a035
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547072266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1547072266
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1500300505
Short name T150
Test name
Test status
Simulation time 318671762869 ps
CPU time 726.61 seconds
Started Aug 03 05:29:12 PM PDT 24
Finished Aug 03 05:41:19 PM PDT 24
Peak memory 201424 kb
Host smart-f0e1a0c2-e8b2-4b88-acaf-b9d857b590cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500300505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1500300505
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3537123310
Short name T461
Test name
Test status
Simulation time 161448815152 ps
CPU time 378.64 seconds
Started Aug 03 05:29:11 PM PDT 24
Finished Aug 03 05:35:30 PM PDT 24
Peak memory 201492 kb
Host smart-a514c668-08a9-4001-bf85-0d5d44e49248
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537123310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3537123310
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3158855075
Short name T497
Test name
Test status
Simulation time 165096385566 ps
CPU time 369.35 seconds
Started Aug 03 05:29:11 PM PDT 24
Finished Aug 03 05:35:21 PM PDT 24
Peak memory 201484 kb
Host smart-fafcf0a6-9781-4b30-9a69-9f49d9c6fa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158855075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3158855075
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.4059667826
Short name T592
Test name
Test status
Simulation time 489775600685 ps
CPU time 599.19 seconds
Started Aug 03 05:29:11 PM PDT 24
Finished Aug 03 05:39:10 PM PDT 24
Peak memory 201412 kb
Host smart-1c8d8dc0-32e5-44bb-9dc1-f673e3a02bcf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059667826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.4059667826
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.164053879
Short name T143
Test name
Test status
Simulation time 574616167254 ps
CPU time 973.63 seconds
Started Aug 03 05:29:11 PM PDT 24
Finished Aug 03 05:45:24 PM PDT 24
Peak memory 201480 kb
Host smart-99fafbc6-984f-4d00-a71e-b5cb84a015b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164053879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.164053879
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2175932109
Short name T535
Test name
Test status
Simulation time 398808641648 ps
CPU time 454.46 seconds
Started Aug 03 05:29:18 PM PDT 24
Finished Aug 03 05:36:53 PM PDT 24
Peak memory 201392 kb
Host smart-7aa2b0ae-fda1-4486-a144-1e46151341f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175932109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2175932109
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2412513454
Short name T416
Test name
Test status
Simulation time 28934717910 ps
CPU time 60 seconds
Started Aug 03 05:29:15 PM PDT 24
Finished Aug 03 05:30:15 PM PDT 24
Peak memory 201340 kb
Host smart-8be6602f-5959-4343-9425-77000b69d6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412513454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2412513454
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1909238400
Short name T761
Test name
Test status
Simulation time 3059494539 ps
CPU time 4.72 seconds
Started Aug 03 05:29:16 PM PDT 24
Finished Aug 03 05:29:21 PM PDT 24
Peak memory 201356 kb
Host smart-066eac23-867a-4b29-b8ab-973e0268d0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909238400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1909238400
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1660599435
Short name T688
Test name
Test status
Simulation time 5864402127 ps
CPU time 4.27 seconds
Started Aug 03 05:29:11 PM PDT 24
Finished Aug 03 05:29:15 PM PDT 24
Peak memory 201352 kb
Host smart-ca35269f-00ed-4fa8-8155-d2248e6ce185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660599435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1660599435
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.453198430
Short name T398
Test name
Test status
Simulation time 49136127714 ps
CPU time 26.24 seconds
Started Aug 03 05:29:16 PM PDT 24
Finished Aug 03 05:29:42 PM PDT 24
Peak memory 201348 kb
Host smart-1c25da1e-d873-414d-940d-cbd4c04c1dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453198430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
453198430
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3457279859
Short name T44
Test name
Test status
Simulation time 81266237466 ps
CPU time 353.16 seconds
Started Aug 03 05:29:18 PM PDT 24
Finished Aug 03 05:35:11 PM PDT 24
Peak memory 210504 kb
Host smart-0311392e-1ff8-4494-add2-9e24a9c4a42d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457279859 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3457279859
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.535931623
Short name T617
Test name
Test status
Simulation time 405508250 ps
CPU time 1.48 seconds
Started Aug 03 05:29:23 PM PDT 24
Finished Aug 03 05:29:24 PM PDT 24
Peak memory 201380 kb
Host smart-2016c7c8-985a-45f8-b618-3898bdbf187b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535931623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.535931623
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3216266465
Short name T222
Test name
Test status
Simulation time 169492199055 ps
CPU time 323.53 seconds
Started Aug 03 05:29:21 PM PDT 24
Finished Aug 03 05:34:45 PM PDT 24
Peak memory 201512 kb
Host smart-91b9603e-512e-4172-b3f2-4ead02b6ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216266465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3216266465
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2308189336
Short name T98
Test name
Test status
Simulation time 495836328370 ps
CPU time 240.23 seconds
Started Aug 03 05:29:19 PM PDT 24
Finished Aug 03 05:33:20 PM PDT 24
Peak memory 201368 kb
Host smart-da232578-824b-4610-9b7e-9bd1f4a64518
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308189336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2308189336
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1568668862
Short name T554
Test name
Test status
Simulation time 325138913853 ps
CPU time 95.75 seconds
Started Aug 03 05:29:20 PM PDT 24
Finished Aug 03 05:30:56 PM PDT 24
Peak memory 201392 kb
Host smart-551e42b2-ef24-4ded-a3b7-ca7445fbb373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568668862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1568668862
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2801380662
Short name T751
Test name
Test status
Simulation time 167254228174 ps
CPU time 89.95 seconds
Started Aug 03 05:29:19 PM PDT 24
Finished Aug 03 05:30:49 PM PDT 24
Peak memory 201380 kb
Host smart-a92644e2-0649-462b-a56f-b6beda943e8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801380662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2801380662
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3604737724
Short name T27
Test name
Test status
Simulation time 586954857244 ps
CPU time 1365.46 seconds
Started Aug 03 05:29:22 PM PDT 24
Finished Aug 03 05:52:07 PM PDT 24
Peak memory 201344 kb
Host smart-74ed5c79-dfd3-49d3-ac50-222380e53b43
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604737724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3604737724
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.858727829
Short name T485
Test name
Test status
Simulation time 94315839401 ps
CPU time 261.54 seconds
Started Aug 03 05:29:21 PM PDT 24
Finished Aug 03 05:33:43 PM PDT 24
Peak memory 201892 kb
Host smart-0411ddd7-007e-4964-be8e-f76f333bbdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858727829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.858727829
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3242793103
Short name T158
Test name
Test status
Simulation time 24498865705 ps
CPU time 29.64 seconds
Started Aug 03 05:29:21 PM PDT 24
Finished Aug 03 05:29:50 PM PDT 24
Peak memory 201352 kb
Host smart-db548dd4-dd6c-48c7-bb81-3f747fbe0cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242793103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3242793103
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.552645323
Short name T644
Test name
Test status
Simulation time 3238273751 ps
CPU time 2.47 seconds
Started Aug 03 05:29:21 PM PDT 24
Finished Aug 03 05:29:23 PM PDT 24
Peak memory 201344 kb
Host smart-7bdfdd8a-48c2-441a-86ad-b1cb2fad0c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552645323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.552645323
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1547273112
Short name T419
Test name
Test status
Simulation time 6017827215 ps
CPU time 4.42 seconds
Started Aug 03 05:29:18 PM PDT 24
Finished Aug 03 05:29:23 PM PDT 24
Peak memory 201376 kb
Host smart-6dd080d8-d11e-4eec-a87c-3dd57cea063b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547273112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1547273112
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2964997841
Short name T47
Test name
Test status
Simulation time 11837602400 ps
CPU time 28.24 seconds
Started Aug 03 05:29:22 PM PDT 24
Finished Aug 03 05:29:51 PM PDT 24
Peak memory 210028 kb
Host smart-6b7f149f-fa9f-4b05-a26b-b1ece975aa4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964997841 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2964997841
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3483658178
Short name T659
Test name
Test status
Simulation time 310250150 ps
CPU time 0.81 seconds
Started Aug 03 05:29:27 PM PDT 24
Finished Aug 03 05:29:28 PM PDT 24
Peak memory 201244 kb
Host smart-b4c9438f-943c-4d07-996a-50484be15599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483658178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3483658178
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.494450809
Short name T171
Test name
Test status
Simulation time 166868689995 ps
CPU time 36.5 seconds
Started Aug 03 05:29:26 PM PDT 24
Finished Aug 03 05:30:03 PM PDT 24
Peak memory 201416 kb
Host smart-61b59472-85be-48f2-aab0-2118119979e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494450809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.494450809
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.549404277
Short name T796
Test name
Test status
Simulation time 222183579868 ps
CPU time 267.65 seconds
Started Aug 03 05:29:27 PM PDT 24
Finished Aug 03 05:33:55 PM PDT 24
Peak memory 201456 kb
Host smart-9937a130-6dbe-427e-94f3-383e9231c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549404277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.549404277
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.514226062
Short name T450
Test name
Test status
Simulation time 324164178874 ps
CPU time 666.84 seconds
Started Aug 03 05:29:20 PM PDT 24
Finished Aug 03 05:40:27 PM PDT 24
Peak memory 201360 kb
Host smart-34656a4c-833a-45f0-b4ce-2c210fbc8c5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=514226062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.514226062
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3566507824
Short name T464
Test name
Test status
Simulation time 330820961516 ps
CPU time 798.49 seconds
Started Aug 03 05:29:25 PM PDT 24
Finished Aug 03 05:42:44 PM PDT 24
Peak memory 201516 kb
Host smart-da2c72e3-37fa-42b3-8dbf-a07c1998916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566507824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3566507824
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1233590200
Short name T111
Test name
Test status
Simulation time 325745860993 ps
CPU time 356.23 seconds
Started Aug 03 05:29:25 PM PDT 24
Finished Aug 03 05:35:21 PM PDT 24
Peak memory 201436 kb
Host smart-dd8c85c1-50b0-436d-ab81-18e26b3d45bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233590200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1233590200
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1987573564
Short name T623
Test name
Test status
Simulation time 174061629389 ps
CPU time 399.27 seconds
Started Aug 03 05:29:26 PM PDT 24
Finished Aug 03 05:36:06 PM PDT 24
Peak memory 201448 kb
Host smart-9dbd0ae0-d6ab-4a64-94a9-b7d7a9f9c71e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987573564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1987573564
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2541252024
Short name T533
Test name
Test status
Simulation time 399043185393 ps
CPU time 249.04 seconds
Started Aug 03 05:29:27 PM PDT 24
Finished Aug 03 05:33:36 PM PDT 24
Peak memory 201460 kb
Host smart-622e575d-5d08-41be-be4b-0571d33c9125
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541252024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2541252024
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2224796561
Short name T597
Test name
Test status
Simulation time 118842096523 ps
CPU time 486.69 seconds
Started Aug 03 05:29:26 PM PDT 24
Finished Aug 03 05:37:33 PM PDT 24
Peak memory 201852 kb
Host smart-bb17286b-cf90-40bc-9efe-fcdd470cffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224796561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2224796561
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2031515788
Short name T469
Test name
Test status
Simulation time 38347251538 ps
CPU time 78.96 seconds
Started Aug 03 05:29:25 PM PDT 24
Finished Aug 03 05:30:44 PM PDT 24
Peak memory 201316 kb
Host smart-a35e6282-6ac8-411c-bb77-a0782aa9d1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031515788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2031515788
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3711377417
Short name T571
Test name
Test status
Simulation time 4672471923 ps
CPU time 12.09 seconds
Started Aug 03 05:29:28 PM PDT 24
Finished Aug 03 05:29:40 PM PDT 24
Peak memory 201324 kb
Host smart-202a6a74-d767-4bd9-91bf-a0845024f188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711377417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3711377417
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3784041407
Short name T489
Test name
Test status
Simulation time 5976522789 ps
CPU time 2.25 seconds
Started Aug 03 05:29:22 PM PDT 24
Finished Aug 03 05:29:24 PM PDT 24
Peak memory 201372 kb
Host smart-926db3d8-61b6-455d-9321-e1c11e793290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784041407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3784041407
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.767713080
Short name T718
Test name
Test status
Simulation time 448759592 ps
CPU time 0.95 seconds
Started Aug 03 05:29:30 PM PDT 24
Finished Aug 03 05:29:31 PM PDT 24
Peak memory 201256 kb
Host smart-5c9f2206-08b6-4b09-ac40-1d52b9f4fc6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767713080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.767713080
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2329533275
Short name T243
Test name
Test status
Simulation time 165460617466 ps
CPU time 98.58 seconds
Started Aug 03 05:29:30 PM PDT 24
Finished Aug 03 05:31:09 PM PDT 24
Peak memory 201496 kb
Host smart-dc01bad2-69f2-4735-a9be-7b3850caf399
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329533275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2329533275
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.653664850
Short name T779
Test name
Test status
Simulation time 158468997960 ps
CPU time 351.18 seconds
Started Aug 03 05:29:25 PM PDT 24
Finished Aug 03 05:35:17 PM PDT 24
Peak memory 201424 kb
Host smart-06b514ce-b8ce-4391-8eeb-314229e46931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653664850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.653664850
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3551158159
Short name T431
Test name
Test status
Simulation time 332972901162 ps
CPU time 61.7 seconds
Started Aug 03 05:29:26 PM PDT 24
Finished Aug 03 05:30:27 PM PDT 24
Peak memory 201428 kb
Host smart-71a7570a-6fb2-489b-b930-a53855366bd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551158159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3551158159
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.493358614
Short name T319
Test name
Test status
Simulation time 324597830556 ps
CPU time 780.37 seconds
Started Aug 03 05:29:29 PM PDT 24
Finished Aug 03 05:42:29 PM PDT 24
Peak memory 201528 kb
Host smart-b2df60a2-0217-42c4-a7ae-f21fc226d43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493358614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.493358614
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.993250043
Short name T96
Test name
Test status
Simulation time 489990278499 ps
CPU time 1211.96 seconds
Started Aug 03 05:29:25 PM PDT 24
Finished Aug 03 05:49:37 PM PDT 24
Peak memory 201452 kb
Host smart-b13f46d7-626b-4b89-b182-90f43b7c846c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=993250043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.993250043
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.522880889
Short name T768
Test name
Test status
Simulation time 598510384080 ps
CPU time 1283.34 seconds
Started Aug 03 05:29:26 PM PDT 24
Finished Aug 03 05:50:49 PM PDT 24
Peak memory 201456 kb
Host smart-5d62f6ed-25d5-49f2-860c-167210311d3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522880889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.522880889
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2318588804
Short name T377
Test name
Test status
Simulation time 585842239641 ps
CPU time 300.91 seconds
Started Aug 03 05:29:31 PM PDT 24
Finished Aug 03 05:34:32 PM PDT 24
Peak memory 201428 kb
Host smart-6d349b3d-a210-448d-b1ef-5d61028e3863
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318588804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2318588804
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.103271069
Short name T690
Test name
Test status
Simulation time 114879699252 ps
CPU time 437.8 seconds
Started Aug 03 05:29:31 PM PDT 24
Finished Aug 03 05:36:48 PM PDT 24
Peak memory 201828 kb
Host smart-4a33c96a-bb6f-4cb5-9eff-abc24e430080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103271069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.103271069
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.394562421
Short name T655
Test name
Test status
Simulation time 42375790249 ps
CPU time 102.92 seconds
Started Aug 03 05:29:31 PM PDT 24
Finished Aug 03 05:31:14 PM PDT 24
Peak memory 201296 kb
Host smart-fe3088b8-9960-4f82-8f79-99672f3ae4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394562421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.394562421
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.583000624
Short name T700
Test name
Test status
Simulation time 4229031773 ps
CPU time 9.84 seconds
Started Aug 03 05:29:31 PM PDT 24
Finished Aug 03 05:29:41 PM PDT 24
Peak memory 201348 kb
Host smart-060781ab-7729-4f44-8b21-b6a5012b461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583000624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.583000624
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2901501664
Short name T114
Test name
Test status
Simulation time 5868875920 ps
CPU time 4.53 seconds
Started Aug 03 05:29:29 PM PDT 24
Finished Aug 03 05:29:34 PM PDT 24
Peak memory 201316 kb
Host smart-637ef02f-1fd1-437c-a226-b49c3758e5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901501664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2901501664
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2949717141
Short name T736
Test name
Test status
Simulation time 486751294381 ps
CPU time 1156.47 seconds
Started Aug 03 05:29:32 PM PDT 24
Finished Aug 03 05:48:48 PM PDT 24
Peak memory 201432 kb
Host smart-cd316393-f140-464d-9273-4abb089d611b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949717141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2949717141
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3275571969
Short name T603
Test name
Test status
Simulation time 68923684465 ps
CPU time 96.89 seconds
Started Aug 03 05:29:31 PM PDT 24
Finished Aug 03 05:31:08 PM PDT 24
Peak memory 218340 kb
Host smart-6a7d08e6-65ce-4219-ac20-8676631e5202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275571969 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3275571969
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.463546292
Short name T507
Test name
Test status
Simulation time 299708091 ps
CPU time 1.23 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:28:37 PM PDT 24
Peak memory 201264 kb
Host smart-e7ae9414-29c4-47df-871b-715185e3a285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463546292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.463546292
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.595558433
Short name T113
Test name
Test status
Simulation time 291638117708 ps
CPU time 663.79 seconds
Started Aug 03 05:28:37 PM PDT 24
Finished Aug 03 05:39:41 PM PDT 24
Peak memory 201516 kb
Host smart-3c6d220d-f668-472f-b222-1bff4b7f012a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595558433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.595558433
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.877017490
Short name T225
Test name
Test status
Simulation time 362969383901 ps
CPU time 412.05 seconds
Started Aug 03 05:28:37 PM PDT 24
Finished Aug 03 05:35:29 PM PDT 24
Peak memory 201408 kb
Host smart-95a3099f-4e0f-4aee-826b-ecdb40427820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877017490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.877017490
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1898650679
Short name T441
Test name
Test status
Simulation time 328286581038 ps
CPU time 401.71 seconds
Started Aug 03 05:28:37 PM PDT 24
Finished Aug 03 05:35:18 PM PDT 24
Peak memory 201456 kb
Host smart-a60a8421-5453-48c1-8e6b-482c59c619e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898650679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1898650679
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1879036217
Short name T152
Test name
Test status
Simulation time 496602145071 ps
CPU time 1212.28 seconds
Started Aug 03 05:28:27 PM PDT 24
Finished Aug 03 05:48:40 PM PDT 24
Peak memory 201456 kb
Host smart-d737fd6f-1644-493a-998c-4488c716786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879036217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1879036217
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.4000224333
Short name T542
Test name
Test status
Simulation time 326002543524 ps
CPU time 376.12 seconds
Started Aug 03 05:28:29 PM PDT 24
Finished Aug 03 05:34:46 PM PDT 24
Peak memory 201404 kb
Host smart-35bc4b97-5f00-44e3-ae22-fe12c8081560
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000224333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.4000224333
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1820727677
Short name T185
Test name
Test status
Simulation time 341320639781 ps
CPU time 124.49 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:30:40 PM PDT 24
Peak memory 201460 kb
Host smart-6dda01d5-65b4-4b4e-a4c4-a7c610a9c639
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820727677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1820727677
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2439896776
Short name T163
Test name
Test status
Simulation time 214812979635 ps
CPU time 44.25 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:29:20 PM PDT 24
Peak memory 201472 kb
Host smart-e91c42a5-3749-4fef-83de-6787273a321e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439896776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2439896776
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1716634820
Short name T619
Test name
Test status
Simulation time 88390389389 ps
CPU time 423.22 seconds
Started Aug 03 05:28:38 PM PDT 24
Finished Aug 03 05:35:41 PM PDT 24
Peak memory 201828 kb
Host smart-a1e60e3e-f26f-425d-b274-9d09ceee71ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716634820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1716634820
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1107243616
Short name T714
Test name
Test status
Simulation time 32920526822 ps
CPU time 80.51 seconds
Started Aug 03 05:28:33 PM PDT 24
Finished Aug 03 05:29:54 PM PDT 24
Peak memory 201356 kb
Host smart-cca880b5-b1eb-4a58-8b7d-b5b9421a234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107243616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1107243616
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2436646445
Short name T388
Test name
Test status
Simulation time 4578586046 ps
CPU time 2.37 seconds
Started Aug 03 05:28:37 PM PDT 24
Finished Aug 03 05:28:40 PM PDT 24
Peak memory 201304 kb
Host smart-a19911f0-62c2-4a17-b3c0-ad8ecf5be7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436646445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2436646445
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3637846801
Short name T529
Test name
Test status
Simulation time 5783820066 ps
CPU time 4.02 seconds
Started Aug 03 05:28:30 PM PDT 24
Finished Aug 03 05:28:34 PM PDT 24
Peak memory 201352 kb
Host smart-0e7a4764-9617-496e-882b-b6cde3498bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637846801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3637846801
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4235572511
Short name T747
Test name
Test status
Simulation time 165654076940 ps
CPU time 183.47 seconds
Started Aug 03 05:28:34 PM PDT 24
Finished Aug 03 05:31:38 PM PDT 24
Peak memory 201436 kb
Host smart-f34c7cf7-739b-4637-98fa-91c355559337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235572511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4235572511
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2190844612
Short name T25
Test name
Test status
Simulation time 198135257433 ps
CPU time 190.69 seconds
Started Aug 03 05:28:37 PM PDT 24
Finished Aug 03 05:31:48 PM PDT 24
Peak memory 210128 kb
Host smart-9e888edf-f138-4fdb-a943-9e6ba1a3b368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190844612 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2190844612
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1609257561
Short name T598
Test name
Test status
Simulation time 486963859 ps
CPU time 0.89 seconds
Started Aug 03 05:29:42 PM PDT 24
Finished Aug 03 05:29:43 PM PDT 24
Peak memory 201248 kb
Host smart-8d4d55d3-4a45-4353-98f4-e7110c749dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609257561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1609257561
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1528710195
Short name T311
Test name
Test status
Simulation time 557013080634 ps
CPU time 667.39 seconds
Started Aug 03 05:29:42 PM PDT 24
Finished Aug 03 05:40:49 PM PDT 24
Peak memory 201448 kb
Host smart-24a37ad5-1ec4-454c-99e6-e7c10b1758b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528710195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1528710195
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.921193780
Short name T438
Test name
Test status
Simulation time 336136725343 ps
CPU time 179.72 seconds
Started Aug 03 05:29:36 PM PDT 24
Finished Aug 03 05:32:36 PM PDT 24
Peak memory 201496 kb
Host smart-33833339-6c1b-4fd3-bd39-0fe72c0ddef6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=921193780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.921193780
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3799225644
Short name T762
Test name
Test status
Simulation time 329111381364 ps
CPU time 390.35 seconds
Started Aug 03 05:29:37 PM PDT 24
Finished Aug 03 05:36:07 PM PDT 24
Peak memory 201404 kb
Host smart-9e3a488d-e49d-4a4e-ba08-5919e7ae162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799225644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3799225644
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1446241307
Short name T727
Test name
Test status
Simulation time 481898805916 ps
CPU time 272.99 seconds
Started Aug 03 05:29:35 PM PDT 24
Finished Aug 03 05:34:08 PM PDT 24
Peak memory 201444 kb
Host smart-c2a51b1f-e1b8-4d96-83dd-d35b813985ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446241307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1446241307
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3100624269
Short name T91
Test name
Test status
Simulation time 601207270641 ps
CPU time 1408.72 seconds
Started Aug 03 05:29:37 PM PDT 24
Finished Aug 03 05:53:06 PM PDT 24
Peak memory 201460 kb
Host smart-7db82574-2ba8-439f-88e5-c4dcf1910691
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100624269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3100624269
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3575391897
Short name T348
Test name
Test status
Simulation time 140650243707 ps
CPU time 425.59 seconds
Started Aug 03 05:29:43 PM PDT 24
Finished Aug 03 05:36:49 PM PDT 24
Peak memory 201804 kb
Host smart-8ca004d4-b147-4499-9522-9a9afa3d0049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575391897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3575391897
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1509450247
Short name T633
Test name
Test status
Simulation time 35821096282 ps
CPU time 41.99 seconds
Started Aug 03 05:29:45 PM PDT 24
Finished Aug 03 05:30:27 PM PDT 24
Peak memory 201372 kb
Host smart-1bc95001-5812-40e0-9f34-c2ef28fa0e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509450247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1509450247
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2935972921
Short name T594
Test name
Test status
Simulation time 3601820727 ps
CPU time 5.44 seconds
Started Aug 03 05:29:41 PM PDT 24
Finished Aug 03 05:29:47 PM PDT 24
Peak memory 201236 kb
Host smart-51ae4c0d-965b-4846-abe6-7175b4f609c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935972921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2935972921
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3660648489
Short name T567
Test name
Test status
Simulation time 5774233542 ps
CPU time 14.23 seconds
Started Aug 03 05:29:36 PM PDT 24
Finished Aug 03 05:29:50 PM PDT 24
Peak memory 201360 kb
Host smart-60b42361-d178-4333-b5ac-983992dc8d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660648489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3660648489
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3934821670
Short name T74
Test name
Test status
Simulation time 30513596588 ps
CPU time 32.71 seconds
Started Aug 03 05:29:44 PM PDT 24
Finished Aug 03 05:30:17 PM PDT 24
Peak memory 201344 kb
Host smart-4a0b42a4-c24c-41a0-8f66-e529113ad75c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934821670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3934821670
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3023712796
Short name T322
Test name
Test status
Simulation time 63778395234 ps
CPU time 149.24 seconds
Started Aug 03 05:29:42 PM PDT 24
Finished Aug 03 05:32:11 PM PDT 24
Peak memory 217800 kb
Host smart-c88d0199-9ada-42d4-aab9-6726d5cc122d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023712796 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3023712796
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1198515019
Short name T658
Test name
Test status
Simulation time 499277182 ps
CPU time 0.91 seconds
Started Aug 03 05:29:48 PM PDT 24
Finished Aug 03 05:29:49 PM PDT 24
Peak memory 201220 kb
Host smart-8b14b9f8-2065-4057-9ee3-e829b0734eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198515019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1198515019
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1593561595
Short name T337
Test name
Test status
Simulation time 489883251722 ps
CPU time 1003.1 seconds
Started Aug 03 05:29:45 PM PDT 24
Finished Aug 03 05:46:28 PM PDT 24
Peak memory 201456 kb
Host smart-0e73babd-2ebf-4f9a-a54b-7a1d52299306
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593561595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1593561595
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1195991524
Short name T729
Test name
Test status
Simulation time 391017451564 ps
CPU time 234.9 seconds
Started Aug 03 05:29:40 PM PDT 24
Finished Aug 03 05:33:35 PM PDT 24
Peak memory 201464 kb
Host smart-bf0f1cce-f838-44e5-a634-5875dedb5c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195991524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1195991524
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2109564491
Short name T145
Test name
Test status
Simulation time 168092615852 ps
CPU time 104.26 seconds
Started Aug 03 05:29:45 PM PDT 24
Finished Aug 03 05:31:30 PM PDT 24
Peak memory 201468 kb
Host smart-d4fe73c0-6331-42ca-bf6a-b0776c6aaac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109564491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2109564491
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1621377756
Short name T549
Test name
Test status
Simulation time 321963262330 ps
CPU time 210.09 seconds
Started Aug 03 05:29:43 PM PDT 24
Finished Aug 03 05:33:13 PM PDT 24
Peak memory 201368 kb
Host smart-48f75dc3-77c2-4804-a743-6b8f5275c54a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621377756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1621377756
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.910425561
Short name T578
Test name
Test status
Simulation time 481816041561 ps
CPU time 274.08 seconds
Started Aug 03 05:29:42 PM PDT 24
Finished Aug 03 05:34:16 PM PDT 24
Peak memory 201424 kb
Host smart-ee2fa08f-dc64-41b6-9acb-e22cbe8b16f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910425561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.910425561
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2608235203
Short name T760
Test name
Test status
Simulation time 170648929166 ps
CPU time 398.71 seconds
Started Aug 03 05:29:44 PM PDT 24
Finished Aug 03 05:36:23 PM PDT 24
Peak memory 201440 kb
Host smart-aef85bc0-77da-4149-885c-ca4c1251f427
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608235203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2608235203
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2408384756
Short name T177
Test name
Test status
Simulation time 540525851235 ps
CPU time 1277.65 seconds
Started Aug 03 05:29:42 PM PDT 24
Finished Aug 03 05:51:00 PM PDT 24
Peak memory 201392 kb
Host smart-6112552b-0900-47bb-9433-5fe098118956
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408384756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2408384756
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2592634379
Short name T160
Test name
Test status
Simulation time 417403456170 ps
CPU time 110.22 seconds
Started Aug 03 05:29:42 PM PDT 24
Finished Aug 03 05:31:32 PM PDT 24
Peak memory 201436 kb
Host smart-0312a9d5-ddb4-4d5e-8a68-cf69c7aa2240
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592634379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2592634379
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2489285596
Short name T553
Test name
Test status
Simulation time 25399310020 ps
CPU time 32.04 seconds
Started Aug 03 05:29:45 PM PDT 24
Finished Aug 03 05:30:17 PM PDT 24
Peak memory 201348 kb
Host smart-92e74bf5-7348-4c89-859f-fb46229b9a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489285596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2489285596
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.4229010030
Short name T421
Test name
Test status
Simulation time 4195369626 ps
CPU time 10.52 seconds
Started Aug 03 05:29:41 PM PDT 24
Finished Aug 03 05:29:51 PM PDT 24
Peak memory 201352 kb
Host smart-1a27de55-9220-453a-bf48-07807e8cbe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229010030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4229010030
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.4100695693
Short name T635
Test name
Test status
Simulation time 6043611954 ps
CPU time 9.59 seconds
Started Aug 03 05:29:42 PM PDT 24
Finished Aug 03 05:29:51 PM PDT 24
Peak memory 201384 kb
Host smart-c7059aa1-d6d3-43aa-98c6-94bebb7c64ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100695693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.4100695693
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2620224676
Short name T720
Test name
Test status
Simulation time 16195079468 ps
CPU time 41.15 seconds
Started Aug 03 05:29:48 PM PDT 24
Finished Aug 03 05:30:29 PM PDT 24
Peak memory 201652 kb
Host smart-3c3e2611-955d-450b-b25a-4e031873f6af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620224676 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2620224676
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1738962749
Short name T77
Test name
Test status
Simulation time 456324752 ps
CPU time 1.19 seconds
Started Aug 03 05:29:52 PM PDT 24
Finished Aug 03 05:29:53 PM PDT 24
Peak memory 201180 kb
Host smart-f633ad5e-a38e-425f-9310-f66a11e39331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738962749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1738962749
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3701939757
Short name T228
Test name
Test status
Simulation time 351288429120 ps
CPU time 743.68 seconds
Started Aug 03 05:29:47 PM PDT 24
Finished Aug 03 05:42:10 PM PDT 24
Peak memory 201488 kb
Host smart-dcb611ba-ec0c-4e36-8204-a97525ded6e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701939757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3701939757
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2267850643
Short name T318
Test name
Test status
Simulation time 162899273501 ps
CPU time 49.7 seconds
Started Aug 03 05:29:49 PM PDT 24
Finished Aug 03 05:30:38 PM PDT 24
Peak memory 201404 kb
Host smart-e8cbe116-82a3-41fb-a720-97b98095bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267850643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2267850643
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.96549337
Short name T706
Test name
Test status
Simulation time 318814833378 ps
CPU time 192.37 seconds
Started Aug 03 05:29:48 PM PDT 24
Finished Aug 03 05:33:00 PM PDT 24
Peak memory 201380 kb
Host smart-f38c534d-1d8f-4724-a9b7-fc1158bff02f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=96549337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt
_fixed.96549337
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2392343159
Short name T650
Test name
Test status
Simulation time 488838705897 ps
CPU time 291.03 seconds
Started Aug 03 05:29:50 PM PDT 24
Finished Aug 03 05:34:41 PM PDT 24
Peak memory 201468 kb
Host smart-1a295519-c883-45bb-a5e2-e2006f6f13fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392343159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2392343159
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2672125333
Short name T443
Test name
Test status
Simulation time 325605119066 ps
CPU time 710.58 seconds
Started Aug 03 05:29:47 PM PDT 24
Finished Aug 03 05:41:38 PM PDT 24
Peak memory 201464 kb
Host smart-2036a7d4-965c-42ff-8a76-700ef3c6ea79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672125333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2672125333
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.622216951
Short name T276
Test name
Test status
Simulation time 370510995684 ps
CPU time 330.46 seconds
Started Aug 03 05:29:48 PM PDT 24
Finished Aug 03 05:35:18 PM PDT 24
Peak memory 201532 kb
Host smart-bddb130f-826a-40b7-8f87-2c655cfb3626
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622216951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.622216951
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3187269955
Short name T526
Test name
Test status
Simulation time 206827575773 ps
CPU time 130.2 seconds
Started Aug 03 05:29:48 PM PDT 24
Finished Aug 03 05:31:59 PM PDT 24
Peak memory 201504 kb
Host smart-b3df0def-7ebf-4bcf-944e-4f2db44518f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187269955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3187269955
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2864805660
Short name T787
Test name
Test status
Simulation time 63830164417 ps
CPU time 217.17 seconds
Started Aug 03 05:29:53 PM PDT 24
Finished Aug 03 05:33:30 PM PDT 24
Peak memory 201844 kb
Host smart-5fa5eb5a-6d36-45b0-99f9-cdffe5f95939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864805660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2864805660
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1048988082
Short name T364
Test name
Test status
Simulation time 32012345931 ps
CPU time 72.51 seconds
Started Aug 03 05:29:54 PM PDT 24
Finished Aug 03 05:31:06 PM PDT 24
Peak memory 201352 kb
Host smart-dc2add74-4527-412c-b5f3-ea272d1114f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048988082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1048988082
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1575446328
Short name T528
Test name
Test status
Simulation time 4818161906 ps
CPU time 6.54 seconds
Started Aug 03 05:29:47 PM PDT 24
Finished Aug 03 05:29:54 PM PDT 24
Peak memory 201344 kb
Host smart-9d4a1970-6fe1-49b7-9a5e-0768cfc552cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575446328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1575446328
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1706825945
Short name T568
Test name
Test status
Simulation time 5536290967 ps
CPU time 9.78 seconds
Started Aug 03 05:29:47 PM PDT 24
Finished Aug 03 05:29:57 PM PDT 24
Peak memory 201292 kb
Host smart-16085ffa-e448-4c93-822a-46423feb17ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706825945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1706825945
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.136895609
Short name T306
Test name
Test status
Simulation time 63948430459 ps
CPU time 92.07 seconds
Started Aug 03 05:29:54 PM PDT 24
Finished Aug 03 05:31:27 PM PDT 24
Peak memory 210188 kb
Host smart-a70374eb-5d47-4e8e-bd9d-4ae6b64f2ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136895609 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.136895609
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1507687481
Short name T368
Test name
Test status
Simulation time 287428987 ps
CPU time 1.27 seconds
Started Aug 03 05:30:01 PM PDT 24
Finished Aug 03 05:30:03 PM PDT 24
Peak memory 201216 kb
Host smart-79029816-b1ec-45cf-a239-8b875de538e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507687481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1507687481
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3946195200
Short name T590
Test name
Test status
Simulation time 497295538659 ps
CPU time 572.97 seconds
Started Aug 03 05:29:52 PM PDT 24
Finished Aug 03 05:39:25 PM PDT 24
Peak memory 201464 kb
Host smart-ac69dc62-99cb-46f8-a523-836c5ee955f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946195200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3946195200
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3776588645
Short name T550
Test name
Test status
Simulation time 160307628989 ps
CPU time 104.1 seconds
Started Aug 03 05:29:53 PM PDT 24
Finished Aug 03 05:31:37 PM PDT 24
Peak memory 201424 kb
Host smart-4857e64f-cd19-44ff-805a-078f7394a98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776588645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3776588645
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.581705245
Short name T582
Test name
Test status
Simulation time 165918610921 ps
CPU time 377.92 seconds
Started Aug 03 05:29:54 PM PDT 24
Finished Aug 03 05:36:12 PM PDT 24
Peak memory 201408 kb
Host smart-259eef68-bd5f-4685-acd1-634d44cca977
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=581705245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.581705245
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3620836526
Short name T562
Test name
Test status
Simulation time 556975219402 ps
CPU time 561.29 seconds
Started Aug 03 05:29:52 PM PDT 24
Finished Aug 03 05:39:13 PM PDT 24
Peak memory 201404 kb
Host smart-9ee8467e-725d-49a1-9c2e-cdfc5dbe4089
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620836526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3620836526
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3041206615
Short name T601
Test name
Test status
Simulation time 602885264823 ps
CPU time 751.62 seconds
Started Aug 03 05:29:56 PM PDT 24
Finished Aug 03 05:42:28 PM PDT 24
Peak memory 201464 kb
Host smart-0442df74-4d0d-46b6-b35b-b835f048eb1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041206615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3041206615
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4027080575
Short name T621
Test name
Test status
Simulation time 113575384636 ps
CPU time 575.58 seconds
Started Aug 03 05:29:57 PM PDT 24
Finished Aug 03 05:39:33 PM PDT 24
Peak memory 201800 kb
Host smart-9afb937d-3434-4edd-8790-369f71dce4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027080575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4027080575
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.556959952
Short name T686
Test name
Test status
Simulation time 39334473199 ps
CPU time 15.86 seconds
Started Aug 03 05:29:58 PM PDT 24
Finished Aug 03 05:30:14 PM PDT 24
Peak memory 201388 kb
Host smart-1d342056-5d85-47a0-8556-aab77338469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556959952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.556959952
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.4284824978
Short name T442
Test name
Test status
Simulation time 4366191940 ps
CPU time 11.71 seconds
Started Aug 03 05:30:01 PM PDT 24
Finished Aug 03 05:30:13 PM PDT 24
Peak memory 201348 kb
Host smart-2e124795-e10a-4c02-8eb4-eb46de776939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284824978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4284824978
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3492252707
Short name T352
Test name
Test status
Simulation time 5991150468 ps
CPU time 13.62 seconds
Started Aug 03 05:29:53 PM PDT 24
Finished Aug 03 05:30:07 PM PDT 24
Peak memory 201364 kb
Host smart-ba1143cb-0918-4f45-98bc-b30827a2be3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492252707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3492252707
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.5295687
Short name T467
Test name
Test status
Simulation time 444621218 ps
CPU time 0.84 seconds
Started Aug 03 05:30:04 PM PDT 24
Finished Aug 03 05:30:05 PM PDT 24
Peak memory 201148 kb
Host smart-ba45eed3-4c57-498b-8a31-8f924e30c347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5295687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.5295687
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.152778254
Short name T630
Test name
Test status
Simulation time 170087201916 ps
CPU time 389.26 seconds
Started Aug 03 05:30:03 PM PDT 24
Finished Aug 03 05:36:33 PM PDT 24
Peak memory 201456 kb
Host smart-e7492704-cd2f-44cb-bcb4-03eba2319e8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152778254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.152778254
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2797076066
Short name T168
Test name
Test status
Simulation time 527128977065 ps
CPU time 295.34 seconds
Started Aug 03 05:30:03 PM PDT 24
Finished Aug 03 05:34:58 PM PDT 24
Peak memory 201604 kb
Host smart-63334eea-ff75-4803-95fe-f75ffe1dbdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797076066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2797076066
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.335395275
Short name T333
Test name
Test status
Simulation time 329346378871 ps
CPU time 768.17 seconds
Started Aug 03 05:30:00 PM PDT 24
Finished Aug 03 05:42:48 PM PDT 24
Peak memory 201444 kb
Host smart-744357a5-40fa-4fc6-804d-cd0c27f2c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335395275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.335395275
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2135835427
Short name T458
Test name
Test status
Simulation time 494969923815 ps
CPU time 556.96 seconds
Started Aug 03 05:30:00 PM PDT 24
Finished Aug 03 05:39:17 PM PDT 24
Peak memory 201428 kb
Host smart-85735e85-afbf-412d-a0f8-2a3e2b312ef1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135835427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2135835427
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.513086098
Short name T618
Test name
Test status
Simulation time 478171937482 ps
CPU time 168.17 seconds
Started Aug 03 05:30:01 PM PDT 24
Finished Aug 03 05:32:50 PM PDT 24
Peak memory 201452 kb
Host smart-bbfa5ab8-83ad-47f6-9010-84e024baf9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513086098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.513086098
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2961547861
Short name T758
Test name
Test status
Simulation time 330665047951 ps
CPU time 548.64 seconds
Started Aug 03 05:29:57 PM PDT 24
Finished Aug 03 05:39:06 PM PDT 24
Peak memory 201448 kb
Host smart-b4571a28-b1a6-4742-a4d1-acd82963133e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961547861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2961547861
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3999584611
Short name T589
Test name
Test status
Simulation time 185027832926 ps
CPU time 222.42 seconds
Started Aug 03 05:30:01 PM PDT 24
Finished Aug 03 05:33:44 PM PDT 24
Peak memory 201444 kb
Host smart-86222a8c-14ee-499c-b87a-87f1d9c2fdc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999584611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3999584611
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.226399232
Short name T782
Test name
Test status
Simulation time 397514179780 ps
CPU time 639.83 seconds
Started Aug 03 05:29:56 PM PDT 24
Finished Aug 03 05:40:36 PM PDT 24
Peak memory 201424 kb
Host smart-798bbf42-f9b2-4870-a81a-c811f24c79c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226399232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.226399232
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.677904972
Short name T350
Test name
Test status
Simulation time 92443614387 ps
CPU time 374.51 seconds
Started Aug 03 05:30:02 PM PDT 24
Finished Aug 03 05:36:17 PM PDT 24
Peak memory 201824 kb
Host smart-2db7d369-3d37-42a3-832f-c6e732d11d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677904972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.677904972
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2319671405
Short name T511
Test name
Test status
Simulation time 44864072822 ps
CPU time 52.37 seconds
Started Aug 03 05:30:02 PM PDT 24
Finished Aug 03 05:30:54 PM PDT 24
Peak memory 201384 kb
Host smart-679d589e-6ded-4717-b38c-81996ceab450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319671405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2319671405
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3520513371
Short name T492
Test name
Test status
Simulation time 2940420101 ps
CPU time 1.55 seconds
Started Aug 03 05:30:04 PM PDT 24
Finished Aug 03 05:30:06 PM PDT 24
Peak memory 201304 kb
Host smart-98c64e5d-517f-4db3-ac53-59a86fb6bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520513371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3520513371
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3279165344
Short name T556
Test name
Test status
Simulation time 5761269727 ps
CPU time 4.45 seconds
Started Aug 03 05:30:01 PM PDT 24
Finished Aug 03 05:30:05 PM PDT 24
Peak memory 201380 kb
Host smart-94a88a27-53c8-44e1-8f20-b7013edb7340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279165344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3279165344
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2731896190
Short name T303
Test name
Test status
Simulation time 658407687911 ps
CPU time 1374.39 seconds
Started Aug 03 05:30:02 PM PDT 24
Finished Aug 03 05:52:56 PM PDT 24
Peak memory 201432 kb
Host smart-09698708-b0fc-494d-80f9-23be773ccb29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731896190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2731896190
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1419468446
Short name T35
Test name
Test status
Simulation time 55541558877 ps
CPU time 37.45 seconds
Started Aug 03 05:30:03 PM PDT 24
Finished Aug 03 05:30:40 PM PDT 24
Peak memory 209784 kb
Host smart-69e3dac2-ba81-459e-8a14-e0b153c032f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419468446 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1419468446
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3374558985
Short name T664
Test name
Test status
Simulation time 459127102 ps
CPU time 1.2 seconds
Started Aug 03 05:30:13 PM PDT 24
Finished Aug 03 05:30:14 PM PDT 24
Peak memory 201244 kb
Host smart-f060dc45-cff7-4a2a-a648-527dc23297ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374558985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3374558985
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3167866098
Short name T227
Test name
Test status
Simulation time 329549589823 ps
CPU time 246.27 seconds
Started Aug 03 05:30:09 PM PDT 24
Finished Aug 03 05:34:16 PM PDT 24
Peak memory 201360 kb
Host smart-67c3928f-97a0-4e62-a134-14a9398a44dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167866098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3167866098
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.356545658
Short name T190
Test name
Test status
Simulation time 489977670231 ps
CPU time 319.09 seconds
Started Aug 03 05:30:09 PM PDT 24
Finished Aug 03 05:35:28 PM PDT 24
Peak memory 201400 kb
Host smart-41392a9f-e296-4343-8580-402f7a76c5bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=356545658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.356545658
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2485872086
Short name T217
Test name
Test status
Simulation time 490570802818 ps
CPU time 106.61 seconds
Started Aug 03 05:30:07 PM PDT 24
Finished Aug 03 05:31:54 PM PDT 24
Peak memory 201448 kb
Host smart-b8f80481-cf96-4ad1-a9bc-bf24f94d2303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485872086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2485872086
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1737191055
Short name T486
Test name
Test status
Simulation time 164117637549 ps
CPU time 385.96 seconds
Started Aug 03 05:30:08 PM PDT 24
Finished Aug 03 05:36:34 PM PDT 24
Peak memory 201412 kb
Host smart-d75d492d-8ecb-4dcc-9ae4-ee74010756a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737191055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1737191055
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3745801241
Short name T362
Test name
Test status
Simulation time 405953593479 ps
CPU time 889.31 seconds
Started Aug 03 05:30:09 PM PDT 24
Finished Aug 03 05:44:59 PM PDT 24
Peak memory 201456 kb
Host smart-d76f5837-1d89-412d-bbe9-4fd3645a3606
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745801241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3745801241
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2023660936
Short name T197
Test name
Test status
Simulation time 124205593061 ps
CPU time 708.3 seconds
Started Aug 03 05:30:13 PM PDT 24
Finished Aug 03 05:42:01 PM PDT 24
Peak memory 201832 kb
Host smart-f73f9977-b168-479a-8d44-ace40045233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023660936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2023660936
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.4170059804
Short name T527
Test name
Test status
Simulation time 26126446432 ps
CPU time 60.33 seconds
Started Aug 03 05:30:13 PM PDT 24
Finished Aug 03 05:31:13 PM PDT 24
Peak memory 201292 kb
Host smart-7b02be81-0bc6-4f15-9018-db31322f72d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170059804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.4170059804
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.692417349
Short name T435
Test name
Test status
Simulation time 4483759630 ps
CPU time 6.49 seconds
Started Aug 03 05:30:15 PM PDT 24
Finished Aug 03 05:30:22 PM PDT 24
Peak memory 201344 kb
Host smart-401958fc-0013-45c5-a505-2f0768858f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692417349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.692417349
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3868249416
Short name T525
Test name
Test status
Simulation time 5739735280 ps
CPU time 15.29 seconds
Started Aug 03 05:30:09 PM PDT 24
Finished Aug 03 05:30:25 PM PDT 24
Peak memory 201328 kb
Host smart-322f8128-606c-4394-bb47-2058fedc2c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868249416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3868249416
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3454620731
Short name T90
Test name
Test status
Simulation time 197492280294 ps
CPU time 471.56 seconds
Started Aug 03 05:30:13 PM PDT 24
Finished Aug 03 05:38:05 PM PDT 24
Peak memory 201464 kb
Host smart-4e2bf4c0-2ef7-4b54-b613-42218341e1d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454620731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3454620731
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3079445913
Short name T709
Test name
Test status
Simulation time 17239539061 ps
CPU time 39.56 seconds
Started Aug 03 05:30:12 PM PDT 24
Finished Aug 03 05:30:52 PM PDT 24
Peak memory 209772 kb
Host smart-416b7993-dec7-4201-862f-5d9081e4b643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079445913 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3079445913
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1470091330
Short name T674
Test name
Test status
Simulation time 425014250 ps
CPU time 1.74 seconds
Started Aug 03 05:30:18 PM PDT 24
Finished Aug 03 05:30:20 PM PDT 24
Peak memory 201216 kb
Host smart-bbe546b2-e923-4ba8-a395-ae47cb2f42a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470091330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1470091330
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.4084975691
Short name T172
Test name
Test status
Simulation time 522158255077 ps
CPU time 538.04 seconds
Started Aug 03 05:30:20 PM PDT 24
Finished Aug 03 05:39:18 PM PDT 24
Peak memory 201448 kb
Host smart-a2317e03-2718-481b-aa1d-a4c0d52779c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084975691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.4084975691
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1742527035
Short name T257
Test name
Test status
Simulation time 327596278748 ps
CPU time 217.68 seconds
Started Aug 03 05:30:13 PM PDT 24
Finished Aug 03 05:33:51 PM PDT 24
Peak memory 201384 kb
Host smart-c54189e4-1f9d-4ec2-a597-441f1f36c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742527035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1742527035
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3820746969
Short name T161
Test name
Test status
Simulation time 482018760203 ps
CPU time 114.07 seconds
Started Aug 03 05:30:16 PM PDT 24
Finished Aug 03 05:32:11 PM PDT 24
Peak memory 201424 kb
Host smart-093e19dc-be6b-4b9e-a957-68e5b5afabb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820746969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3820746969
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.708422497
Short name T676
Test name
Test status
Simulation time 325692998361 ps
CPU time 713.95 seconds
Started Aug 03 05:30:15 PM PDT 24
Finished Aug 03 05:42:09 PM PDT 24
Peak memory 201464 kb
Host smart-b5bc597d-bfb1-4081-8426-9bb5c180d4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708422497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.708422497
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.251361725
Short name T423
Test name
Test status
Simulation time 493066721651 ps
CPU time 501.99 seconds
Started Aug 03 05:30:16 PM PDT 24
Finished Aug 03 05:38:38 PM PDT 24
Peak memory 201416 kb
Host smart-da611789-8b8f-4a39-97bf-e8152fcc9725
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=251361725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.251361725
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.4278747749
Short name T539
Test name
Test status
Simulation time 199163768804 ps
CPU time 286.57 seconds
Started Aug 03 05:30:13 PM PDT 24
Finished Aug 03 05:34:59 PM PDT 24
Peak memory 201448 kb
Host smart-1cddf372-c1f8-4b46-88ef-d85c2b3682c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278747749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.4278747749
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3281973490
Short name T632
Test name
Test status
Simulation time 411044038618 ps
CPU time 504.73 seconds
Started Aug 03 05:30:17 PM PDT 24
Finished Aug 03 05:38:42 PM PDT 24
Peak memory 201400 kb
Host smart-6217a4fd-a028-4934-a2d0-7b3f1f89a64c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281973490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3281973490
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3287115238
Short name T34
Test name
Test status
Simulation time 81481392684 ps
CPU time 290.18 seconds
Started Aug 03 05:30:19 PM PDT 24
Finished Aug 03 05:35:09 PM PDT 24
Peak memory 201884 kb
Host smart-a4e65279-d28a-47e7-8d17-5e7accacfa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287115238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3287115238
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3783746995
Short name T480
Test name
Test status
Simulation time 41606416475 ps
CPU time 46.41 seconds
Started Aug 03 05:30:19 PM PDT 24
Finished Aug 03 05:31:06 PM PDT 24
Peak memory 201300 kb
Host smart-c5579a64-b988-49d5-a3b8-f63eb6f4c19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783746995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3783746995
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.617700638
Short name T403
Test name
Test status
Simulation time 3100868649 ps
CPU time 7.53 seconds
Started Aug 03 05:30:20 PM PDT 24
Finished Aug 03 05:30:28 PM PDT 24
Peak memory 201360 kb
Host smart-4fc89aa6-b71d-4c87-a14c-a40a2eb67e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617700638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.617700638
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.776851648
Short name T97
Test name
Test status
Simulation time 6063264701 ps
CPU time 4.42 seconds
Started Aug 03 05:30:13 PM PDT 24
Finished Aug 03 05:30:17 PM PDT 24
Peak memory 201384 kb
Host smart-3adb06e1-60ae-4e80-90cc-2d68eb2bd5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776851648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.776851648
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2082615237
Short name T793
Test name
Test status
Simulation time 218900886297 ps
CPU time 39.16 seconds
Started Aug 03 05:30:24 PM PDT 24
Finished Aug 03 05:31:04 PM PDT 24
Peak memory 201428 kb
Host smart-2fa81c35-ca02-4433-898b-350849777a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082615237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2082615237
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.228632880
Short name T484
Test name
Test status
Simulation time 445302984 ps
CPU time 0.86 seconds
Started Aug 03 05:30:23 PM PDT 24
Finished Aug 03 05:30:24 PM PDT 24
Peak memory 201248 kb
Host smart-badbc9e0-d7f8-4f1f-b312-5f7dc4c2df9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228632880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.228632880
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2201393738
Short name T254
Test name
Test status
Simulation time 354402875147 ps
CPU time 549.28 seconds
Started Aug 03 05:30:18 PM PDT 24
Finished Aug 03 05:39:28 PM PDT 24
Peak memory 201416 kb
Host smart-6c4bcc0e-a221-46d6-8c3c-2fea65eeeaab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201393738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2201393738
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.593493460
Short name T188
Test name
Test status
Simulation time 487250141425 ps
CPU time 272.95 seconds
Started Aug 03 05:30:20 PM PDT 24
Finished Aug 03 05:34:53 PM PDT 24
Peak memory 201428 kb
Host smart-b8841f90-c790-4112-92ef-6b9e2e1fe4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593493460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.593493460
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.534154532
Short name T379
Test name
Test status
Simulation time 336403324274 ps
CPU time 175.68 seconds
Started Aug 03 05:30:19 PM PDT 24
Finished Aug 03 05:33:15 PM PDT 24
Peak memory 201432 kb
Host smart-55debb0d-dd32-4230-b5d6-1710a0c3cb03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=534154532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.534154532
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1306497668
Short name T748
Test name
Test status
Simulation time 330369205471 ps
CPU time 786.26 seconds
Started Aug 03 05:30:19 PM PDT 24
Finished Aug 03 05:43:26 PM PDT 24
Peak memory 201396 kb
Host smart-761d0a0b-fa07-4c6d-9e3a-f80c898a7f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306497668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1306497668
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2563945388
Short name T638
Test name
Test status
Simulation time 337198972198 ps
CPU time 718.44 seconds
Started Aug 03 05:30:20 PM PDT 24
Finished Aug 03 05:42:19 PM PDT 24
Peak memory 201412 kb
Host smart-c62cd9a9-96f0-4f2a-86f6-319d7bfe4e2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563945388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2563945388
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.4266318454
Short name T249
Test name
Test status
Simulation time 521313539981 ps
CPU time 620.52 seconds
Started Aug 03 05:30:20 PM PDT 24
Finished Aug 03 05:40:41 PM PDT 24
Peak memory 201448 kb
Host smart-053a7e20-1af8-4e05-86a9-32f626345c58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266318454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.4266318454
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.998645319
Short name T109
Test name
Test status
Simulation time 100231710159 ps
CPU time 361.89 seconds
Started Aug 03 05:30:23 PM PDT 24
Finished Aug 03 05:36:25 PM PDT 24
Peak memory 201832 kb
Host smart-21c38479-9742-43b2-8b5c-acfcffced44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998645319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.998645319
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1475552026
Short name T42
Test name
Test status
Simulation time 26795689025 ps
CPU time 57.73 seconds
Started Aug 03 05:30:23 PM PDT 24
Finished Aug 03 05:31:21 PM PDT 24
Peak memory 201300 kb
Host smart-0a82cc2f-07a3-41d0-a027-cf275aa43034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475552026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1475552026
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4061998862
Short name T756
Test name
Test status
Simulation time 4539350733 ps
CPU time 10.57 seconds
Started Aug 03 05:30:28 PM PDT 24
Finished Aug 03 05:30:39 PM PDT 24
Peak memory 201348 kb
Host smart-a75b55c0-931d-434a-a2f0-ddfdcc0bafa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061998862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4061998862
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2807679404
Short name T370
Test name
Test status
Simulation time 5822069318 ps
CPU time 13.56 seconds
Started Aug 03 05:30:20 PM PDT 24
Finished Aug 03 05:30:33 PM PDT 24
Peak memory 201352 kb
Host smart-1aaef80b-d509-42d2-9c8b-e5f4363401d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807679404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2807679404
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1985258745
Short name T637
Test name
Test status
Simulation time 82803622983 ps
CPU time 178.01 seconds
Started Aug 03 05:30:24 PM PDT 24
Finished Aug 03 05:33:22 PM PDT 24
Peak memory 201388 kb
Host smart-0e62a2b7-d526-4fc7-b364-988006e19f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985258745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1985258745
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2094593726
Short name T334
Test name
Test status
Simulation time 125519000871 ps
CPU time 356.27 seconds
Started Aug 03 05:30:23 PM PDT 24
Finished Aug 03 05:36:19 PM PDT 24
Peak memory 217580 kb
Host smart-8f33860a-ebc2-4d08-8440-9f738eeedf19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094593726 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2094593726
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2719804392
Short name T773
Test name
Test status
Simulation time 452988897 ps
CPU time 0.72 seconds
Started Aug 03 05:30:27 PM PDT 24
Finished Aug 03 05:30:28 PM PDT 24
Peak memory 201256 kb
Host smart-41bf1a77-b587-4f4a-9ade-a4a1b3ac6837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719804392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2719804392
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1572418153
Short name T546
Test name
Test status
Simulation time 347578098960 ps
CPU time 198.05 seconds
Started Aug 03 05:30:30 PM PDT 24
Finished Aug 03 05:33:49 PM PDT 24
Peak memory 201420 kb
Host smart-19989ef0-a2e6-467e-af38-261d1375ae48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572418153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1572418153
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2850578198
Short name T332
Test name
Test status
Simulation time 494638397630 ps
CPU time 1086.3 seconds
Started Aug 03 05:30:28 PM PDT 24
Finished Aug 03 05:48:35 PM PDT 24
Peak memory 201500 kb
Host smart-107624f7-c926-4fe1-ac48-476fa8b7380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850578198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2850578198
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2414319286
Short name T445
Test name
Test status
Simulation time 489454218642 ps
CPU time 606.25 seconds
Started Aug 03 05:30:28 PM PDT 24
Finished Aug 03 05:40:34 PM PDT 24
Peak memory 201468 kb
Host smart-3e8a5b4a-d132-4335-b439-70f3820f0fe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414319286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2414319286
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2127099692
Short name T427
Test name
Test status
Simulation time 162616796601 ps
CPU time 394.18 seconds
Started Aug 03 05:30:24 PM PDT 24
Finished Aug 03 05:36:58 PM PDT 24
Peak memory 201452 kb
Host smart-448aee37-591b-4f5b-a948-097d769cc5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127099692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2127099692
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1478747122
Short name T734
Test name
Test status
Simulation time 333199317380 ps
CPU time 193.03 seconds
Started Aug 03 05:30:24 PM PDT 24
Finished Aug 03 05:33:38 PM PDT 24
Peak memory 201360 kb
Host smart-c42bb6fd-e74f-4fc2-955f-a2d0dc6b1b6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478747122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1478747122
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1361504077
Short name T92
Test name
Test status
Simulation time 552181635672 ps
CPU time 331.58 seconds
Started Aug 03 05:30:28 PM PDT 24
Finished Aug 03 05:36:00 PM PDT 24
Peak memory 201416 kb
Host smart-919a8cd4-431f-40bd-8224-2d67c5227e09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361504077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1361504077
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3889175759
Short name T365
Test name
Test status
Simulation time 396566592760 ps
CPU time 959.81 seconds
Started Aug 03 05:30:31 PM PDT 24
Finished Aug 03 05:46:31 PM PDT 24
Peak memory 201432 kb
Host smart-3043a6d8-2f13-4234-b5c4-892ece8c616c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889175759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3889175759
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3494219534
Short name T764
Test name
Test status
Simulation time 102397466833 ps
CPU time 316.88 seconds
Started Aug 03 05:30:30 PM PDT 24
Finished Aug 03 05:35:47 PM PDT 24
Peak memory 201800 kb
Host smart-4fece2ed-119c-493c-ac16-994a9cb53f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494219534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3494219534
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1489253589
Short name T2
Test name
Test status
Simulation time 46544380526 ps
CPU time 28.79 seconds
Started Aug 03 05:30:28 PM PDT 24
Finished Aug 03 05:30:57 PM PDT 24
Peak memory 201320 kb
Host smart-45b4788c-6a85-4205-935e-b6cbf5a0a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489253589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1489253589
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1674979189
Short name T695
Test name
Test status
Simulation time 4858968675 ps
CPU time 11.9 seconds
Started Aug 03 05:30:28 PM PDT 24
Finished Aug 03 05:30:40 PM PDT 24
Peak memory 201508 kb
Host smart-a8942fdc-fd70-4c57-9364-b60d34483611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674979189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1674979189
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1425051750
Short name T728
Test name
Test status
Simulation time 5811957546 ps
CPU time 7.18 seconds
Started Aug 03 05:30:29 PM PDT 24
Finished Aug 03 05:30:36 PM PDT 24
Peak memory 201352 kb
Host smart-20d8e353-83bb-4dc2-8a46-73ea6629e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425051750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1425051750
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.618036152
Short name T520
Test name
Test status
Simulation time 517591119641 ps
CPU time 320.41 seconds
Started Aug 03 05:30:30 PM PDT 24
Finished Aug 03 05:35:50 PM PDT 24
Peak memory 201384 kb
Host smart-5c200ad2-d7d1-4585-bc62-2de80f5ab402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618036152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
618036152
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2981528715
Short name T651
Test name
Test status
Simulation time 281562557786 ps
CPU time 54.29 seconds
Started Aug 03 05:30:28 PM PDT 24
Finished Aug 03 05:31:22 PM PDT 24
Peak memory 209752 kb
Host smart-0db30ce7-10a4-48a5-ad37-28c8bcda21c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981528715 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2981528715
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3760878950
Short name T380
Test name
Test status
Simulation time 309921768 ps
CPU time 0.99 seconds
Started Aug 03 05:30:44 PM PDT 24
Finished Aug 03 05:30:45 PM PDT 24
Peak memory 201216 kb
Host smart-7c5742fe-9c9d-447f-bfbf-11cd34522fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760878950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3760878950
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2222209826
Short name T699
Test name
Test status
Simulation time 524983271333 ps
CPU time 874.87 seconds
Started Aug 03 05:30:35 PM PDT 24
Finished Aug 03 05:45:10 PM PDT 24
Peak memory 201476 kb
Host smart-26acc2d6-81ad-4df7-ad54-a8ae2621d4a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222209826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2222209826
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.572207811
Short name T312
Test name
Test status
Simulation time 536363310688 ps
CPU time 324.06 seconds
Started Aug 03 05:30:36 PM PDT 24
Finished Aug 03 05:36:00 PM PDT 24
Peak memory 201524 kb
Host smart-729481e5-caf7-4be8-907b-89b4f16cccc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572207811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.572207811
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.22773879
Short name T231
Test name
Test status
Simulation time 336564457746 ps
CPU time 398.81 seconds
Started Aug 03 05:30:34 PM PDT 24
Finished Aug 03 05:37:13 PM PDT 24
Peak memory 201444 kb
Host smart-6833c672-6361-49e8-99f3-4a55ebacd041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22773879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.22773879
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1889306024
Short name T449
Test name
Test status
Simulation time 168875778545 ps
CPU time 85.35 seconds
Started Aug 03 05:30:36 PM PDT 24
Finished Aug 03 05:32:01 PM PDT 24
Peak memory 201408 kb
Host smart-7eeb2211-aeef-4936-9f44-e06f2fec8dd8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889306024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1889306024
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3376748298
Short name T508
Test name
Test status
Simulation time 162151516282 ps
CPU time 88.93 seconds
Started Aug 03 05:30:29 PM PDT 24
Finished Aug 03 05:31:58 PM PDT 24
Peak memory 201508 kb
Host smart-8a5d457a-d5ab-407b-bc66-86273c14a0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376748298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3376748298
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.679026025
Short name T735
Test name
Test status
Simulation time 503618120550 ps
CPU time 1219.82 seconds
Started Aug 03 05:30:36 PM PDT 24
Finished Aug 03 05:50:56 PM PDT 24
Peak memory 201460 kb
Host smart-2a70e1b6-281c-48bb-97ac-09b6337212d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=679026025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.679026025
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2060151481
Short name T313
Test name
Test status
Simulation time 186590501484 ps
CPU time 436.96 seconds
Started Aug 03 05:30:37 PM PDT 24
Finished Aug 03 05:37:54 PM PDT 24
Peak memory 201384 kb
Host smart-3e7290ba-89bd-43d2-8c67-49d2f7b031ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060151481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2060151481
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3137750088
Short name T357
Test name
Test status
Simulation time 193266251685 ps
CPU time 66.85 seconds
Started Aug 03 05:30:35 PM PDT 24
Finished Aug 03 05:31:42 PM PDT 24
Peak memory 201408 kb
Host smart-59817b5b-247d-4c06-b419-6cabe92e79cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137750088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3137750088
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3610175107
Short name T647
Test name
Test status
Simulation time 142391657753 ps
CPU time 517.57 seconds
Started Aug 03 05:30:44 PM PDT 24
Finished Aug 03 05:39:22 PM PDT 24
Peak memory 201808 kb
Host smart-9ce4d5e9-4745-449b-ab3c-381ff73aa078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610175107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3610175107
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1238172196
Short name T494
Test name
Test status
Simulation time 38198694087 ps
CPU time 23.35 seconds
Started Aug 03 05:30:42 PM PDT 24
Finished Aug 03 05:31:05 PM PDT 24
Peak memory 201344 kb
Host smart-d153e2c4-aa8a-48da-bb20-4a14cc2e19be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238172196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1238172196
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3313576166
Short name T408
Test name
Test status
Simulation time 3051663765 ps
CPU time 8.19 seconds
Started Aug 03 05:30:36 PM PDT 24
Finished Aug 03 05:30:45 PM PDT 24
Peak memory 201332 kb
Host smart-d73dace3-68b3-465c-882d-eb6d32eec3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313576166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3313576166
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3932706772
Short name T447
Test name
Test status
Simulation time 5907793934 ps
CPU time 14.51 seconds
Started Aug 03 05:30:28 PM PDT 24
Finished Aug 03 05:30:42 PM PDT 24
Peak memory 201384 kb
Host smart-f5b111a5-10d3-45a8-aa35-a2c983c83d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932706772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3932706772
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3032353540
Short name T238
Test name
Test status
Simulation time 739167096064 ps
CPU time 1787.49 seconds
Started Aug 03 05:30:42 PM PDT 24
Finished Aug 03 06:00:30 PM PDT 24
Peak memory 201428 kb
Host smart-e1a2fc7a-5ac6-4e31-bd80-43e207d0e956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032353540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3032353540
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2870974517
Short name T278
Test name
Test status
Simulation time 265069590782 ps
CPU time 432.26 seconds
Started Aug 03 05:30:42 PM PDT 24
Finished Aug 03 05:37:54 PM PDT 24
Peak memory 210136 kb
Host smart-f67e3e47-b2b7-4058-b535-4664f5e9226d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870974517 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2870974517
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3106860259
Short name T679
Test name
Test status
Simulation time 354749038 ps
CPU time 1.47 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:28:38 PM PDT 24
Peak memory 201216 kb
Host smart-74223408-4a70-4f0c-878b-b921f7b18d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106860259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3106860259
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1790605726
Short name T283
Test name
Test status
Simulation time 506617950785 ps
CPU time 1136.57 seconds
Started Aug 03 05:28:37 PM PDT 24
Finished Aug 03 05:47:34 PM PDT 24
Peak memory 201404 kb
Host smart-17681b99-c6cc-43cd-8ccb-a86f0c25b676
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790605726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1790605726
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1130408173
Short name T259
Test name
Test status
Simulation time 453752230242 ps
CPU time 1088.06 seconds
Started Aug 03 05:28:35 PM PDT 24
Finished Aug 03 05:46:43 PM PDT 24
Peak memory 201460 kb
Host smart-61dcbcff-74eb-4455-b35f-122b53dd958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130408173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1130408173
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3823773460
Short name T237
Test name
Test status
Simulation time 493053620536 ps
CPU time 310.67 seconds
Started Aug 03 05:28:34 PM PDT 24
Finished Aug 03 05:33:45 PM PDT 24
Peak memory 201392 kb
Host smart-52fc6518-c679-4dba-9d36-a6e540d12434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823773460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3823773460
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3952293735
Short name T392
Test name
Test status
Simulation time 495071724673 ps
CPU time 1162.63 seconds
Started Aug 03 05:28:35 PM PDT 24
Finished Aug 03 05:47:58 PM PDT 24
Peak memory 201496 kb
Host smart-ff44c937-c7f7-4d2f-a825-92591379af6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952293735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3952293735
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.4163812563
Short name T602
Test name
Test status
Simulation time 164830546042 ps
CPU time 27.27 seconds
Started Aug 03 05:28:34 PM PDT 24
Finished Aug 03 05:29:01 PM PDT 24
Peak memory 201456 kb
Host smart-7bbb3308-96ee-423c-ba06-f415851593ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163812563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.4163812563
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1777858022
Short name T477
Test name
Test status
Simulation time 326931464558 ps
CPU time 752.15 seconds
Started Aug 03 05:28:34 PM PDT 24
Finished Aug 03 05:41:07 PM PDT 24
Peak memory 201448 kb
Host smart-424c756f-e385-4d03-9184-15bf92f29b11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777858022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1777858022
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1003269890
Short name T620
Test name
Test status
Simulation time 379686683291 ps
CPU time 64.27 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:29:40 PM PDT 24
Peak memory 201448 kb
Host smart-4a4f7b99-0161-4c44-acef-51d076bc5905
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003269890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1003269890
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.723220209
Short name T105
Test name
Test status
Simulation time 603766448776 ps
CPU time 349.75 seconds
Started Aug 03 05:28:35 PM PDT 24
Finished Aug 03 05:34:25 PM PDT 24
Peak memory 201448 kb
Host smart-ccffa556-bf9b-43a5-bb87-4fa41fb8cf5b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723220209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.723220209
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1868620925
Short name T468
Test name
Test status
Simulation time 78211652212 ps
CPU time 358.03 seconds
Started Aug 03 05:28:35 PM PDT 24
Finished Aug 03 05:34:33 PM PDT 24
Peak memory 201824 kb
Host smart-3c0ccc76-c91c-46d8-82cd-f8c6f87a514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868620925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1868620925
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1224943004
Short name T780
Test name
Test status
Simulation time 46933473738 ps
CPU time 54.4 seconds
Started Aug 03 05:28:38 PM PDT 24
Finished Aug 03 05:29:32 PM PDT 24
Peak memory 201324 kb
Host smart-7787ebb7-8b6b-4ad8-8dc9-372fc535e338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224943004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1224943004
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.4057279664
Short name T475
Test name
Test status
Simulation time 5116231213 ps
CPU time 6.6 seconds
Started Aug 03 05:28:38 PM PDT 24
Finished Aug 03 05:28:44 PM PDT 24
Peak memory 201360 kb
Host smart-3edfdcf7-1f91-482a-8201-c21fccab53c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057279664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.4057279664
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1200009163
Short name T70
Test name
Test status
Simulation time 3756056318 ps
CPU time 3.04 seconds
Started Aug 03 05:28:35 PM PDT 24
Finished Aug 03 05:28:38 PM PDT 24
Peak memory 217180 kb
Host smart-8167c374-feed-454b-adb0-919a12abf63b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200009163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1200009163
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.822893760
Short name T544
Test name
Test status
Simulation time 5630248106 ps
CPU time 14.15 seconds
Started Aug 03 05:28:38 PM PDT 24
Finished Aug 03 05:28:52 PM PDT 24
Peak memory 201336 kb
Host smart-cf9be55f-2231-4e59-a14b-b1e4319ec32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822893760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.822893760
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.142036171
Short name T309
Test name
Test status
Simulation time 376796646743 ps
CPU time 78.94 seconds
Started Aug 03 05:28:37 PM PDT 24
Finished Aug 03 05:29:56 PM PDT 24
Peak memory 201484 kb
Host smart-a6ca021e-675e-4074-8242-27fce1513f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142036171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.142036171
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3994294998
Short name T478
Test name
Test status
Simulation time 342510910 ps
CPU time 1.38 seconds
Started Aug 03 05:31:10 PM PDT 24
Finished Aug 03 05:31:11 PM PDT 24
Peak memory 201244 kb
Host smart-f1292db1-f482-4c54-91ba-bae649760352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994294998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3994294998
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3159702258
Short name T670
Test name
Test status
Simulation time 165964283223 ps
CPU time 47.46 seconds
Started Aug 03 05:30:42 PM PDT 24
Finished Aug 03 05:31:30 PM PDT 24
Peak memory 201520 kb
Host smart-cf2173eb-86cb-4bd6-9c5f-33db2bce7c47
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159702258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3159702258
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.940456844
Short name T142
Test name
Test status
Simulation time 350361812343 ps
CPU time 208.96 seconds
Started Aug 03 05:30:43 PM PDT 24
Finished Aug 03 05:34:12 PM PDT 24
Peak memory 201432 kb
Host smart-ac37f145-457c-4df7-998a-16a95d3543d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940456844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.940456844
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1060215968
Short name T666
Test name
Test status
Simulation time 483737025504 ps
CPU time 311.15 seconds
Started Aug 03 05:30:44 PM PDT 24
Finished Aug 03 05:35:55 PM PDT 24
Peak memory 201464 kb
Host smart-0c909bff-87d4-45d8-aa5d-d50354ca7cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060215968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1060215968
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1179556466
Short name T101
Test name
Test status
Simulation time 164067009161 ps
CPU time 175.44 seconds
Started Aug 03 05:30:44 PM PDT 24
Finished Aug 03 05:33:39 PM PDT 24
Peak memory 201448 kb
Host smart-48c43c90-4c26-4a6a-bf98-e3fa24799772
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179556466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1179556466
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2148411164
Short name T252
Test name
Test status
Simulation time 328791373068 ps
CPU time 305.74 seconds
Started Aug 03 05:30:41 PM PDT 24
Finished Aug 03 05:35:47 PM PDT 24
Peak memory 201488 kb
Host smart-a43ce0ab-b709-4dbf-b64c-f7edeca45586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148411164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2148411164
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1319695823
Short name T563
Test name
Test status
Simulation time 334832622245 ps
CPU time 796.74 seconds
Started Aug 03 05:30:42 PM PDT 24
Finished Aug 03 05:43:59 PM PDT 24
Peak memory 201448 kb
Host smart-8201f250-dccd-4780-a664-8c28840746d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319695823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1319695823
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1874916428
Short name T783
Test name
Test status
Simulation time 185292099416 ps
CPU time 438.29 seconds
Started Aug 03 05:30:44 PM PDT 24
Finished Aug 03 05:38:02 PM PDT 24
Peak memory 201412 kb
Host smart-5c3ff05c-0a47-48bc-9b73-306f973f8f59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874916428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1874916428
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1192503415
Short name T591
Test name
Test status
Simulation time 406536304900 ps
CPU time 152.26 seconds
Started Aug 03 05:30:46 PM PDT 24
Finished Aug 03 05:33:18 PM PDT 24
Peak memory 201412 kb
Host smart-ba8d870c-edd8-4d01-a730-52550aee6c90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192503415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1192503415
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1759107754
Short name T54
Test name
Test status
Simulation time 84068113672 ps
CPU time 482.12 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:43:00 PM PDT 24
Peak memory 201880 kb
Host smart-6dc0887d-9225-4170-bf34-4a41f68b2e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759107754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1759107754
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2486419276
Short name T766
Test name
Test status
Simulation time 27835250572 ps
CPU time 12.69 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:35:11 PM PDT 24
Peak memory 201348 kb
Host smart-0adf0af1-57f4-48b9-8e1f-3cadae16f4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486419276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2486419276
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1449273226
Short name T422
Test name
Test status
Simulation time 4880172900 ps
CPU time 6.98 seconds
Started Aug 03 05:31:01 PM PDT 24
Finished Aug 03 05:31:08 PM PDT 24
Peak memory 201368 kb
Host smart-b682ee87-a9a9-4093-b821-547513721c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449273226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1449273226
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.305427136
Short name T776
Test name
Test status
Simulation time 5813485112 ps
CPU time 2.37 seconds
Started Aug 03 05:30:42 PM PDT 24
Finished Aug 03 05:30:45 PM PDT 24
Peak memory 201384 kb
Host smart-66e8ffa4-5645-4e20-a2b9-15dd61996ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305427136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.305427136
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1876533132
Short name T565
Test name
Test status
Simulation time 334028886905 ps
CPU time 814.49 seconds
Started Aug 03 05:32:39 PM PDT 24
Finished Aug 03 05:46:13 PM PDT 24
Peak memory 201424 kb
Host smart-bf46682f-ba80-4f66-a924-e5008cdb3ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876533132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1876533132
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2119730758
Short name T547
Test name
Test status
Simulation time 441037962 ps
CPU time 0.67 seconds
Started Aug 03 05:30:53 PM PDT 24
Finished Aug 03 05:30:54 PM PDT 24
Peak memory 201240 kb
Host smart-a934b6d6-3f43-41c4-b6de-0b498142ceb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119730758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2119730758
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.434309614
Short name T580
Test name
Test status
Simulation time 515311808859 ps
CPU time 594.51 seconds
Started Aug 03 05:30:54 PM PDT 24
Finished Aug 03 05:40:49 PM PDT 24
Peak memory 201428 kb
Host smart-38c60f85-79e1-4bf4-891c-411d4a3b02b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434309614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.434309614
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2652890839
Short name T323
Test name
Test status
Simulation time 328663457607 ps
CPU time 759.18 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:47:37 PM PDT 24
Peak memory 201492 kb
Host smart-d5856bb2-732d-42af-9d24-d68c6d9b439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652890839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2652890839
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3465736886
Short name T691
Test name
Test status
Simulation time 485682813362 ps
CPU time 283.25 seconds
Started Aug 03 05:30:52 PM PDT 24
Finished Aug 03 05:35:35 PM PDT 24
Peak memory 201360 kb
Host smart-0c4c09e0-b5cb-4aed-aef2-232d745dcc32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465736886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3465736886
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1130171972
Short name T268
Test name
Test status
Simulation time 329013358811 ps
CPU time 785.11 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:48:03 PM PDT 24
Peak memory 201432 kb
Host smart-142268c5-b75f-4008-a7e9-ca56cc291fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130171972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1130171972
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3459659873
Short name T792
Test name
Test status
Simulation time 320409999060 ps
CPU time 184.14 seconds
Started Aug 03 05:35:02 PM PDT 24
Finished Aug 03 05:38:07 PM PDT 24
Peak memory 201364 kb
Host smart-bc9892cb-4cbd-4f93-a2e5-663fba81d2db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459659873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3459659873
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1371949534
Short name T503
Test name
Test status
Simulation time 580695256079 ps
CPU time 686.23 seconds
Started Aug 03 05:30:51 PM PDT 24
Finished Aug 03 05:42:17 PM PDT 24
Peak memory 201460 kb
Host smart-3c69eba5-ce4e-4a01-936d-80305e900dd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371949534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1371949534
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1507770893
Short name T530
Test name
Test status
Simulation time 204615690978 ps
CPU time 78.32 seconds
Started Aug 03 05:30:51 PM PDT 24
Finished Aug 03 05:32:09 PM PDT 24
Peak memory 201420 kb
Host smart-467002d3-7b8c-481e-95a4-b6ea0f4869cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507770893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1507770893
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.902675487
Short name T199
Test name
Test status
Simulation time 122029031327 ps
CPU time 519.59 seconds
Started Aug 03 05:30:51 PM PDT 24
Finished Aug 03 05:39:31 PM PDT 24
Peak memory 201888 kb
Host smart-b5697a16-4229-4d88-bb4d-4ef4afb580a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902675487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.902675487
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1739554728
Short name T455
Test name
Test status
Simulation time 28630755754 ps
CPU time 14.2 seconds
Started Aug 03 05:30:53 PM PDT 24
Finished Aug 03 05:31:07 PM PDT 24
Peak memory 201332 kb
Host smart-5db18b2a-6e93-4dd0-a7ec-312ec4332b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739554728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1739554728
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.4070761488
Short name T359
Test name
Test status
Simulation time 4862339952 ps
CPU time 12.6 seconds
Started Aug 03 05:30:50 PM PDT 24
Finished Aug 03 05:31:03 PM PDT 24
Peak memory 201372 kb
Host smart-d40c98ae-d6e0-44f4-9f99-c8ad30bdf238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070761488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.4070761488
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1492994572
Short name T373
Test name
Test status
Simulation time 5786225043 ps
CPU time 1.58 seconds
Started Aug 03 05:34:57 PM PDT 24
Finished Aug 03 05:34:58 PM PDT 24
Peak memory 201384 kb
Host smart-2091bd85-e4ca-4928-a29d-a33e82599387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492994572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1492994572
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2712506275
Short name T260
Test name
Test status
Simulation time 263948271080 ps
CPU time 630.38 seconds
Started Aug 03 05:30:50 PM PDT 24
Finished Aug 03 05:41:21 PM PDT 24
Peak memory 201448 kb
Host smart-48b1d28f-6f25-4323-8fad-2b9e885a337b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712506275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2712506275
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.4134832182
Short name T326
Test name
Test status
Simulation time 131111375721 ps
CPU time 208.37 seconds
Started Aug 03 05:30:50 PM PDT 24
Finished Aug 03 05:34:19 PM PDT 24
Peak memory 210132 kb
Host smart-93e6bf48-16e6-4b95-81d2-415689303520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134832182 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.4134832182
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.532155244
Short name T426
Test name
Test status
Simulation time 364863441 ps
CPU time 0.81 seconds
Started Aug 03 05:31:01 PM PDT 24
Finished Aug 03 05:31:02 PM PDT 24
Peak memory 201204 kb
Host smart-a053b179-e8c7-405b-83c0-88c65986a321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532155244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.532155244
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4156408061
Short name T327
Test name
Test status
Simulation time 159957646243 ps
CPU time 91.17 seconds
Started Aug 03 05:30:58 PM PDT 24
Finished Aug 03 05:32:30 PM PDT 24
Peak memory 201428 kb
Host smart-0d6da058-fbb1-4c3f-ab5a-979419e690f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156408061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4156408061
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.320762665
Short name T531
Test name
Test status
Simulation time 186962589490 ps
CPU time 110.16 seconds
Started Aug 03 05:31:04 PM PDT 24
Finished Aug 03 05:32:55 PM PDT 24
Peak memory 201452 kb
Host smart-8626ae78-5668-4bb1-84eb-b09ad8d98144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320762665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.320762665
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1820773089
Short name T253
Test name
Test status
Simulation time 162955361054 ps
CPU time 123.06 seconds
Started Aug 03 05:30:57 PM PDT 24
Finished Aug 03 05:33:00 PM PDT 24
Peak memory 201468 kb
Host smart-d70e52f2-9b25-43d5-9942-6639a751db3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820773089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1820773089
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.934790505
Short name T566
Test name
Test status
Simulation time 167550072278 ps
CPU time 100.76 seconds
Started Aug 03 05:30:58 PM PDT 24
Finished Aug 03 05:32:38 PM PDT 24
Peak memory 201496 kb
Host smart-c973905f-2ec7-4d16-9f32-c3b71be20133
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=934790505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.934790505
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3044984182
Short name T183
Test name
Test status
Simulation time 336426199000 ps
CPU time 184.08 seconds
Started Aug 03 05:30:52 PM PDT 24
Finished Aug 03 05:33:56 PM PDT 24
Peak memory 201460 kb
Host smart-9ec0b8b3-533a-49b8-ad17-874d8c9ba746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044984182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3044984182
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2948824239
Short name T564
Test name
Test status
Simulation time 325757327017 ps
CPU time 749.52 seconds
Started Aug 03 05:30:54 PM PDT 24
Finished Aug 03 05:43:24 PM PDT 24
Peak memory 201452 kb
Host smart-e057cd3c-bd5a-4b7f-9003-8db36bed6d47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948824239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2948824239
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.60852087
Short name T560
Test name
Test status
Simulation time 185028484675 ps
CPU time 422.95 seconds
Started Aug 03 05:30:58 PM PDT 24
Finished Aug 03 05:38:02 PM PDT 24
Peak memory 201448 kb
Host smart-12dfe4d5-242f-464f-a15a-1935496fb50a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60852087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_w
akeup.60852087
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3351291683
Short name T462
Test name
Test status
Simulation time 598169262880 ps
CPU time 662.89 seconds
Started Aug 03 05:30:58 PM PDT 24
Finished Aug 03 05:42:01 PM PDT 24
Peak memory 201460 kb
Host smart-a8a6630f-019a-4f8c-8b09-e1da384ec43d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351291683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3351291683
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3087924346
Short name T205
Test name
Test status
Simulation time 65983253283 ps
CPU time 303.51 seconds
Started Aug 03 05:31:02 PM PDT 24
Finished Aug 03 05:36:05 PM PDT 24
Peak memory 201888 kb
Host smart-32fc169b-089c-4a32-b09f-f506b46d835a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087924346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3087924346
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.81519825
Short name T646
Test name
Test status
Simulation time 34356969108 ps
CPU time 74.15 seconds
Started Aug 03 05:31:01 PM PDT 24
Finished Aug 03 05:32:15 PM PDT 24
Peak memory 201372 kb
Host smart-7bc3d737-879b-4e28-81af-f9e920f7dda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81519825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.81519825
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.283858411
Short name T363
Test name
Test status
Simulation time 4214698898 ps
CPU time 4.27 seconds
Started Aug 03 05:31:03 PM PDT 24
Finished Aug 03 05:31:08 PM PDT 24
Peak memory 201288 kb
Host smart-9722a6f7-81a9-41a8-bcc3-49dfa9adb44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283858411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.283858411
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2923673416
Short name T640
Test name
Test status
Simulation time 5621933672 ps
CPU time 13.35 seconds
Started Aug 03 05:30:51 PM PDT 24
Finished Aug 03 05:31:04 PM PDT 24
Peak memory 201360 kb
Host smart-50c991c6-d1ef-4c7d-876b-d5fce978b54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923673416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2923673416
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2245454393
Short name T24
Test name
Test status
Simulation time 130921667864 ps
CPU time 114.77 seconds
Started Aug 03 05:31:01 PM PDT 24
Finished Aug 03 05:32:56 PM PDT 24
Peak memory 217612 kb
Host smart-8007ee50-a43e-45cd-a13e-c7bd7c6229ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245454393 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2245454393
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4183706564
Short name T76
Test name
Test status
Simulation time 429678804 ps
CPU time 1.62 seconds
Started Aug 03 05:31:14 PM PDT 24
Finished Aug 03 05:31:15 PM PDT 24
Peak memory 201156 kb
Host smart-047f0256-fe49-47e3-ad83-a7c040004126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183706564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4183706564
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1153626719
Short name T33
Test name
Test status
Simulation time 183937738473 ps
CPU time 219.42 seconds
Started Aug 03 05:31:10 PM PDT 24
Finished Aug 03 05:34:50 PM PDT 24
Peak memory 201452 kb
Host smart-3ac8ec69-3ec4-4354-a445-1309baaa508b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153626719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1153626719
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.619660386
Short name T755
Test name
Test status
Simulation time 330150163332 ps
CPU time 387.8 seconds
Started Aug 03 05:31:08 PM PDT 24
Finished Aug 03 05:37:36 PM PDT 24
Peak memory 201652 kb
Host smart-f395e5ce-87b7-4e6b-ab1e-d01ad62c9be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619660386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.619660386
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3768277492
Short name T456
Test name
Test status
Simulation time 169155579608 ps
CPU time 330.43 seconds
Started Aug 03 05:31:10 PM PDT 24
Finished Aug 03 05:36:40 PM PDT 24
Peak memory 201476 kb
Host smart-d6807766-a3f9-49ce-8c78-df1e50023ef6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768277492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3768277492
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1233777281
Short name T219
Test name
Test status
Simulation time 169586965043 ps
CPU time 179.54 seconds
Started Aug 03 05:31:02 PM PDT 24
Finished Aug 03 05:34:02 PM PDT 24
Peak memory 201460 kb
Host smart-1fd7542a-e1a0-4efa-b33d-ee8480f396a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233777281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1233777281
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3426159674
Short name T100
Test name
Test status
Simulation time 488834548803 ps
CPU time 1169.1 seconds
Started Aug 03 05:31:01 PM PDT 24
Finished Aug 03 05:50:30 PM PDT 24
Peak memory 201380 kb
Host smart-b48ce48b-fd0e-4302-b9f0-58ae75eb1951
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426159674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3426159674
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3475413415
Short name T631
Test name
Test status
Simulation time 202416504687 ps
CPU time 110.05 seconds
Started Aug 03 05:31:07 PM PDT 24
Finished Aug 03 05:32:58 PM PDT 24
Peak memory 201444 kb
Host smart-f1b78414-eb10-4f0f-a0b0-77942e95c97f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475413415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3475413415
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1641420585
Short name T210
Test name
Test status
Simulation time 114662248458 ps
CPU time 381.1 seconds
Started Aug 03 05:31:14 PM PDT 24
Finished Aug 03 05:37:35 PM PDT 24
Peak memory 201816 kb
Host smart-944e591e-b83c-4b4d-85ba-48a832db308f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641420585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1641420585
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2947484073
Short name T583
Test name
Test status
Simulation time 23788064141 ps
CPU time 7.29 seconds
Started Aug 03 05:31:13 PM PDT 24
Finished Aug 03 05:31:20 PM PDT 24
Peak memory 201352 kb
Host smart-278b3b78-859f-4f04-941e-90a848140694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947484073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2947484073
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2640441914
Short name T43
Test name
Test status
Simulation time 5091161852 ps
CPU time 4.54 seconds
Started Aug 03 05:31:13 PM PDT 24
Finished Aug 03 05:31:17 PM PDT 24
Peak memory 201368 kb
Host smart-81fb42ca-0653-4827-ba66-55fee02abf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640441914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2640441914
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3602312899
Short name T374
Test name
Test status
Simulation time 5966979514 ps
CPU time 7.26 seconds
Started Aug 03 05:31:31 PM PDT 24
Finished Aug 03 05:31:39 PM PDT 24
Peak memory 201364 kb
Host smart-ee17bff2-5b1e-4212-971b-bf57af4fba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602312899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3602312899
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1827486790
Short name T656
Test name
Test status
Simulation time 175204412432 ps
CPU time 104.85 seconds
Started Aug 03 05:31:13 PM PDT 24
Finished Aug 03 05:32:58 PM PDT 24
Peak memory 201460 kb
Host smart-c4885ae7-fdad-47de-ae06-8a7906b774a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827486790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1827486790
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4204247985
Short name T715
Test name
Test status
Simulation time 200273928286 ps
CPU time 239.65 seconds
Started Aug 03 05:31:12 PM PDT 24
Finished Aug 03 05:35:12 PM PDT 24
Peak memory 217900 kb
Host smart-1b5a186b-257d-40bc-8099-8e32ed0f190f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204247985 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4204247985
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1051804329
Short name T677
Test name
Test status
Simulation time 397131120 ps
CPU time 1.53 seconds
Started Aug 03 05:31:18 PM PDT 24
Finished Aug 03 05:31:20 PM PDT 24
Peak memory 201180 kb
Host smart-56df5a8c-d85c-4fb8-a88e-d46f2282f938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051804329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1051804329
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2173895169
Short name T613
Test name
Test status
Simulation time 209812066746 ps
CPU time 93.08 seconds
Started Aug 03 05:31:18 PM PDT 24
Finished Aug 03 05:32:51 PM PDT 24
Peak memory 201448 kb
Host smart-239b40ab-884f-4a7e-82b6-a54bfc9f90e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173895169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2173895169
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1315845971
Short name T498
Test name
Test status
Simulation time 162905345201 ps
CPU time 155.5 seconds
Started Aug 03 05:31:20 PM PDT 24
Finished Aug 03 05:33:56 PM PDT 24
Peak memory 201328 kb
Host smart-7d8f6cd6-67be-4f48-9333-4e199598f56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315845971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1315845971
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.288054261
Short name T420
Test name
Test status
Simulation time 165086476218 ps
CPU time 351.03 seconds
Started Aug 03 05:31:14 PM PDT 24
Finished Aug 03 05:37:05 PM PDT 24
Peak memory 201396 kb
Host smart-075a204f-392e-4240-b4e9-2f5295e5ce1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=288054261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.288054261
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.599295943
Short name T175
Test name
Test status
Simulation time 328327803570 ps
CPU time 207.58 seconds
Started Aug 03 05:31:20 PM PDT 24
Finished Aug 03 05:34:48 PM PDT 24
Peak memory 201372 kb
Host smart-e8522e67-2132-47d2-8e25-553811d6f9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599295943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.599295943
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.4040969709
Short name T752
Test name
Test status
Simulation time 491408089590 ps
CPU time 283.08 seconds
Started Aug 03 05:31:13 PM PDT 24
Finished Aug 03 05:35:56 PM PDT 24
Peak memory 201444 kb
Host smart-52390766-ea76-4153-87f2-6c4bc9356ea6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040969709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.4040969709
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3550056750
Short name T641
Test name
Test status
Simulation time 178066684057 ps
CPU time 216.85 seconds
Started Aug 03 05:31:20 PM PDT 24
Finished Aug 03 05:34:57 PM PDT 24
Peak memory 201364 kb
Host smart-27e97d38-af76-4273-b0fd-38cdec7df341
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550056750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3550056750
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3842913022
Short name T430
Test name
Test status
Simulation time 589390887755 ps
CPU time 309.64 seconds
Started Aug 03 05:31:18 PM PDT 24
Finished Aug 03 05:36:27 PM PDT 24
Peak memory 201380 kb
Host smart-bb350042-3169-4dca-a4d2-2f10506733a9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842913022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3842913022
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.848523098
Short name T716
Test name
Test status
Simulation time 89218631007 ps
CPU time 473.64 seconds
Started Aug 03 05:31:18 PM PDT 24
Finished Aug 03 05:39:12 PM PDT 24
Peak memory 201888 kb
Host smart-d65c1ffb-eb54-4b24-a78b-51a8ff2d5e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848523098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.848523098
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.375564562
Short name T366
Test name
Test status
Simulation time 34016850303 ps
CPU time 22.79 seconds
Started Aug 03 05:31:18 PM PDT 24
Finished Aug 03 05:31:40 PM PDT 24
Peak memory 201388 kb
Host smart-47a0c635-5224-45df-b3bf-5fc09bc5fde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375564562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.375564562
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.619899364
Short name T415
Test name
Test status
Simulation time 3848070197 ps
CPU time 2.49 seconds
Started Aug 03 05:31:19 PM PDT 24
Finished Aug 03 05:31:22 PM PDT 24
Peak memory 201360 kb
Host smart-7f683867-8b90-49dc-9938-eb1ec96f84e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619899364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.619899364
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.593199574
Short name T521
Test name
Test status
Simulation time 5760185067 ps
CPU time 4.41 seconds
Started Aug 03 05:31:20 PM PDT 24
Finished Aug 03 05:31:24 PM PDT 24
Peak memory 201212 kb
Host smart-69720102-b420-4d67-b6fd-fa5065227165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593199574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.593199574
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2596329891
Short name T39
Test name
Test status
Simulation time 171322775325 ps
CPU time 382.02 seconds
Started Aug 03 05:31:17 PM PDT 24
Finished Aug 03 05:37:39 PM PDT 24
Peak memory 201588 kb
Host smart-58a10b76-cdc4-4472-9b84-39c4614b9b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596329891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2596329891
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3531327567
Short name T22
Test name
Test status
Simulation time 45606188307 ps
CPU time 58.97 seconds
Started Aug 03 05:31:18 PM PDT 24
Finished Aug 03 05:32:18 PM PDT 24
Peak memory 210128 kb
Host smart-cc97a46e-44a6-4353-a810-9b7b8171e9f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531327567 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3531327567
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.674720955
Short name T763
Test name
Test status
Simulation time 283067994 ps
CPU time 1.18 seconds
Started Aug 03 05:31:28 PM PDT 24
Finished Aug 03 05:31:30 PM PDT 24
Peak memory 201196 kb
Host smart-3210714b-5c19-4d53-a9c6-3d0add63e022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674720955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.674720955
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3676102665
Short name T741
Test name
Test status
Simulation time 321854015850 ps
CPU time 211.41 seconds
Started Aug 03 05:31:25 PM PDT 24
Finished Aug 03 05:34:56 PM PDT 24
Peak memory 201456 kb
Host smart-b0d717ed-6e79-4889-acfc-42f6ce944d5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676102665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3676102665
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3269442758
Short name T215
Test name
Test status
Simulation time 525565853927 ps
CPU time 1301.04 seconds
Started Aug 03 05:31:23 PM PDT 24
Finished Aug 03 05:53:05 PM PDT 24
Peak memory 201420 kb
Host smart-2f078190-7395-47e2-8a40-9416033d554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269442758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3269442758
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.4109301815
Short name T178
Test name
Test status
Simulation time 328593800453 ps
CPU time 186.95 seconds
Started Aug 03 05:31:23 PM PDT 24
Finished Aug 03 05:34:30 PM PDT 24
Peak memory 201456 kb
Host smart-4fb6fd12-4f13-470a-ac06-cf77a07dbf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109301815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.4109301815
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.395340638
Short name T159
Test name
Test status
Simulation time 323403863229 ps
CPU time 709.54 seconds
Started Aug 03 05:31:24 PM PDT 24
Finished Aug 03 05:43:14 PM PDT 24
Peak memory 201536 kb
Host smart-8ae8ac28-73e3-49ea-a832-58083568dfad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=395340638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.395340638
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.671214175
Short name T559
Test name
Test status
Simulation time 500348760103 ps
CPU time 644.85 seconds
Started Aug 03 05:31:35 PM PDT 24
Finished Aug 03 05:42:20 PM PDT 24
Peak memory 201372 kb
Host smart-c77d4465-0401-44e0-a5cd-0b7ebe5a0847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671214175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.671214175
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3166043396
Short name T703
Test name
Test status
Simulation time 166396205577 ps
CPU time 373.09 seconds
Started Aug 03 05:31:23 PM PDT 24
Finished Aug 03 05:37:36 PM PDT 24
Peak memory 201464 kb
Host smart-b02cd624-e777-45dc-a87a-7ab22158c1d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166043396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3166043396
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.705086588
Short name T26
Test name
Test status
Simulation time 258581386191 ps
CPU time 278.6 seconds
Started Aug 03 05:31:24 PM PDT 24
Finished Aug 03 05:36:02 PM PDT 24
Peak memory 201456 kb
Host smart-235c3e96-a562-417b-86a7-17fa23d16516
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705086588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.705086588
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1203466386
Short name T386
Test name
Test status
Simulation time 188898945417 ps
CPU time 203.31 seconds
Started Aug 03 05:31:25 PM PDT 24
Finished Aug 03 05:34:48 PM PDT 24
Peak memory 201476 kb
Host smart-cb4c13d5-9fc9-48dc-ab42-37038ac95eeb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203466386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1203466386
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3948691051
Short name T344
Test name
Test status
Simulation time 119131053053 ps
CPU time 425.27 seconds
Started Aug 03 05:31:31 PM PDT 24
Finished Aug 03 05:38:36 PM PDT 24
Peak memory 201820 kb
Host smart-c48e69d9-9ffd-4db0-9eca-edecb0d17206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948691051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3948691051
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.416274479
Short name T786
Test name
Test status
Simulation time 31993564174 ps
CPU time 39.5 seconds
Started Aug 03 05:31:23 PM PDT 24
Finished Aug 03 05:32:03 PM PDT 24
Peak memory 201300 kb
Host smart-da37ed5e-123e-42a3-b350-b7615129d3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416274479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.416274479
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.996299185
Short name T561
Test name
Test status
Simulation time 4041681201 ps
CPU time 2.55 seconds
Started Aug 03 05:31:24 PM PDT 24
Finished Aug 03 05:31:27 PM PDT 24
Peak memory 201340 kb
Host smart-dec86c05-e88c-4605-a92b-c2dd7d572c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996299185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.996299185
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1401149682
Short name T391
Test name
Test status
Simulation time 6062789961 ps
CPU time 12.95 seconds
Started Aug 03 05:31:18 PM PDT 24
Finished Aug 03 05:31:31 PM PDT 24
Peak memory 201332 kb
Host smart-b0815a58-b26a-434e-843d-828155d0f0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401149682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1401149682
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.895931234
Short name T20
Test name
Test status
Simulation time 294807976023 ps
CPU time 66.92 seconds
Started Aug 03 05:31:28 PM PDT 24
Finished Aug 03 05:32:35 PM PDT 24
Peak memory 201588 kb
Host smart-5c128be6-fd27-4d69-af4f-2af22d558615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895931234 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.895931234
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2359689544
Short name T584
Test name
Test status
Simulation time 331657542 ps
CPU time 0.81 seconds
Started Aug 03 05:35:06 PM PDT 24
Finished Aug 03 05:35:07 PM PDT 24
Peak memory 201196 kb
Host smart-bd43219c-9678-446c-8453-bb93e047d6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359689544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2359689544
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.529619986
Short name T288
Test name
Test status
Simulation time 172036381670 ps
CPU time 111.06 seconds
Started Aug 03 05:31:28 PM PDT 24
Finished Aug 03 05:33:20 PM PDT 24
Peak memory 201516 kb
Host smart-f96c45ec-0eb4-43a5-88c9-7915fabd3970
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529619986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.529619986
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3000019817
Short name T330
Test name
Test status
Simulation time 361831997448 ps
CPU time 806.21 seconds
Started Aug 03 05:31:33 PM PDT 24
Finished Aug 03 05:44:59 PM PDT 24
Peak memory 201400 kb
Host smart-8a4a7928-497c-408f-be82-c592968ba3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000019817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3000019817
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3764505574
Short name T282
Test name
Test status
Simulation time 161836374190 ps
CPU time 367.68 seconds
Started Aug 03 05:31:29 PM PDT 24
Finished Aug 03 05:37:37 PM PDT 24
Peak memory 201472 kb
Host smart-6755e257-be6e-405f-bdc6-a3a4bc64e79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764505574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3764505574
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4233309132
Short name T672
Test name
Test status
Simulation time 493945525263 ps
CPU time 1186.91 seconds
Started Aug 03 05:31:33 PM PDT 24
Finished Aug 03 05:51:20 PM PDT 24
Peak memory 201392 kb
Host smart-9f1cd7f8-0b4b-4437-a53d-9d0b45a1b634
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233309132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4233309132
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2102286154
Short name T448
Test name
Test status
Simulation time 488721946466 ps
CPU time 289.92 seconds
Started Aug 03 05:31:33 PM PDT 24
Finished Aug 03 05:36:23 PM PDT 24
Peak memory 201408 kb
Host smart-8760f9e9-de71-4fbe-907f-e98c678985ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102286154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2102286154
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.375024224
Short name T218
Test name
Test status
Simulation time 171756316792 ps
CPU time 175.69 seconds
Started Aug 03 05:31:29 PM PDT 24
Finished Aug 03 05:34:25 PM PDT 24
Peak memory 201428 kb
Host smart-9aed3434-6b9b-4911-b77b-5b31ebc90f86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375024224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.375024224
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3855203407
Short name T147
Test name
Test status
Simulation time 205852449015 ps
CPU time 441 seconds
Started Aug 03 05:31:29 PM PDT 24
Finished Aug 03 05:38:50 PM PDT 24
Peak memory 201444 kb
Host smart-5cae13fd-b110-47d1-a268-8dbced1fb9a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855203407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3855203407
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.702921198
Short name T7
Test name
Test status
Simulation time 66134520929 ps
CPU time 274.64 seconds
Started Aug 03 05:34:57 PM PDT 24
Finished Aug 03 05:39:32 PM PDT 24
Peak memory 201828 kb
Host smart-288caa95-247c-4a6f-90c3-6cbdbf0b6475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702921198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.702921198
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3350142110
Short name T653
Test name
Test status
Simulation time 37844148738 ps
CPU time 89.01 seconds
Started Aug 03 05:34:56 PM PDT 24
Finished Aug 03 05:36:25 PM PDT 24
Peak memory 201384 kb
Host smart-026a6315-f925-4f05-9dee-4befd266038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350142110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3350142110
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.235325564
Short name T732
Test name
Test status
Simulation time 4713592978 ps
CPU time 11.1 seconds
Started Aug 03 05:31:33 PM PDT 24
Finished Aug 03 05:31:44 PM PDT 24
Peak memory 201312 kb
Host smart-56eb5e88-89b8-4830-baa6-2162e526c80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235325564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.235325564
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.450411751
Short name T353
Test name
Test status
Simulation time 5672754157 ps
CPU time 13.98 seconds
Started Aug 03 05:31:28 PM PDT 24
Finished Aug 03 05:31:42 PM PDT 24
Peak memory 201348 kb
Host smart-baf692a0-2725-49dd-a806-01de0a24ee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450411751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.450411751
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2089847007
Short name T208
Test name
Test status
Simulation time 85025529819 ps
CPU time 269.05 seconds
Started Aug 03 05:33:05 PM PDT 24
Finished Aug 03 05:37:34 PM PDT 24
Peak memory 210012 kb
Host smart-3eb95e35-bec3-4351-a192-e18378cdcce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089847007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2089847007
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.147563145
Short name T83
Test name
Test status
Simulation time 86174047930 ps
CPU time 97.64 seconds
Started Aug 03 05:34:56 PM PDT 24
Finished Aug 03 05:36:34 PM PDT 24
Peak memory 210172 kb
Host smart-c51267b8-27b5-42f8-bc59-846582fa84e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147563145 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.147563145
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1849953428
Short name T629
Test name
Test status
Simulation time 354223559 ps
CPU time 1.36 seconds
Started Aug 03 05:35:04 PM PDT 24
Finished Aug 03 05:35:05 PM PDT 24
Peak memory 201240 kb
Host smart-fdad7532-f57e-43de-b228-5c6fe5d7488f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849953428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1849953428
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.913373736
Short name T328
Test name
Test status
Simulation time 551679780751 ps
CPU time 303.71 seconds
Started Aug 03 05:31:38 PM PDT 24
Finished Aug 03 05:36:42 PM PDT 24
Peak memory 201452 kb
Host smart-fa998145-9192-4115-80ab-e95462b7d954
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913373736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.913373736
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.331508683
Short name T289
Test name
Test status
Simulation time 326198795220 ps
CPU time 759.07 seconds
Started Aug 03 05:31:39 PM PDT 24
Finished Aug 03 05:44:18 PM PDT 24
Peak memory 201340 kb
Host smart-03f36fce-c921-4dc6-b2b7-ec028afa5d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331508683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.331508683
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.81388937
Short name T551
Test name
Test status
Simulation time 494598880929 ps
CPU time 559.45 seconds
Started Aug 03 05:31:38 PM PDT 24
Finished Aug 03 05:40:58 PM PDT 24
Peak memory 201444 kb
Host smart-4d610179-2c38-49d4-9a06-66fde4e9252a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=81388937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt
_fixed.81388937
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2300567305
Short name T166
Test name
Test status
Simulation time 168990512112 ps
CPU time 370.76 seconds
Started Aug 03 05:35:01 PM PDT 24
Finished Aug 03 05:41:12 PM PDT 24
Peak memory 201404 kb
Host smart-f7e87a2a-3ee2-4a49-999e-e43da1c36100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300567305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2300567305
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1713618356
Short name T404
Test name
Test status
Simulation time 491105442502 ps
CPU time 155.92 seconds
Started Aug 03 05:31:41 PM PDT 24
Finished Aug 03 05:34:17 PM PDT 24
Peak memory 201464 kb
Host smart-79998ec2-a21c-44d9-ad76-9e8977f86083
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713618356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1713618356
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.206453533
Short name T261
Test name
Test status
Simulation time 561603107825 ps
CPU time 289.24 seconds
Started Aug 03 05:31:38 PM PDT 24
Finished Aug 03 05:36:28 PM PDT 24
Peak memory 201460 kb
Host smart-c16cfbc4-7ea0-4543-93fd-bcbaa61459d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206453533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.206453533
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.360714219
Short name T605
Test name
Test status
Simulation time 603021754967 ps
CPU time 676.88 seconds
Started Aug 03 05:31:39 PM PDT 24
Finished Aug 03 05:42:56 PM PDT 24
Peak memory 201408 kb
Host smart-b5259073-697e-40e6-9525-6e42a8c540b3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360714219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.360714219
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3368512228
Short name T684
Test name
Test status
Simulation time 94316233386 ps
CPU time 493.41 seconds
Started Aug 03 05:31:38 PM PDT 24
Finished Aug 03 05:39:52 PM PDT 24
Peak memory 201832 kb
Host smart-f89e9e34-c12b-4fe0-8fb4-b4537c211e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368512228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3368512228
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3047509981
Short name T451
Test name
Test status
Simulation time 31031572533 ps
CPU time 27.22 seconds
Started Aug 03 05:31:39 PM PDT 24
Finished Aug 03 05:32:06 PM PDT 24
Peak memory 201512 kb
Host smart-8c7f384e-117e-4bcc-a80b-e60803113c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047509981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3047509981
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3792037776
Short name T569
Test name
Test status
Simulation time 3171186316 ps
CPU time 4.71 seconds
Started Aug 03 05:31:41 PM PDT 24
Finished Aug 03 05:31:45 PM PDT 24
Peak memory 201300 kb
Host smart-5c3b3dd7-37da-4d0a-9a88-db5078fd6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792037776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3792037776
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.339637659
Short name T725
Test name
Test status
Simulation time 5822430699 ps
CPU time 4.27 seconds
Started Aug 03 05:35:01 PM PDT 24
Finished Aug 03 05:35:05 PM PDT 24
Peak memory 201348 kb
Host smart-6154c0d1-33d7-4822-89a9-1fb6b4321f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339637659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.339637659
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2883948863
Short name T767
Test name
Test status
Simulation time 446053959451 ps
CPU time 692.72 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:46:31 PM PDT 24
Peak memory 210004 kb
Host smart-1a0671de-a6db-436b-8f2b-d6dbf73acca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883948863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2883948863
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3867708997
Short name T263
Test name
Test status
Simulation time 56207566202 ps
CPU time 76.84 seconds
Started Aug 03 05:31:37 PM PDT 24
Finished Aug 03 05:32:54 PM PDT 24
Peak memory 210184 kb
Host smart-e50533a8-fb6c-43da-833e-f310a099ed9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867708997 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3867708997
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2026917263
Short name T739
Test name
Test status
Simulation time 559076309 ps
CPU time 0.94 seconds
Started Aug 03 05:32:05 PM PDT 24
Finished Aug 03 05:32:06 PM PDT 24
Peak memory 201264 kb
Host smart-574ad6ac-6867-454c-a864-0628899b823c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026917263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2026917263
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3831874017
Short name T789
Test name
Test status
Simulation time 227644577582 ps
CPU time 115.22 seconds
Started Aug 03 05:31:49 PM PDT 24
Finished Aug 03 05:33:45 PM PDT 24
Peak memory 201444 kb
Host smart-fde274f4-cdff-475b-b1cf-7d0e70ff4ec6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831874017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3831874017
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.4152161273
Short name T770
Test name
Test status
Simulation time 166085569868 ps
CPU time 204.05 seconds
Started Aug 03 05:31:50 PM PDT 24
Finished Aug 03 05:35:15 PM PDT 24
Peak memory 201348 kb
Host smart-2886759f-ea87-4ea6-be90-f44e8ec14afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152161273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.4152161273
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3036553435
Short name T280
Test name
Test status
Simulation time 156208950277 ps
CPU time 85.6 seconds
Started Aug 03 05:35:04 PM PDT 24
Finished Aug 03 05:36:30 PM PDT 24
Peak memory 201424 kb
Host smart-c76e11aa-1813-4de3-a355-93539614be88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036553435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3036553435
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.13133112
Short name T230
Test name
Test status
Simulation time 498862267966 ps
CPU time 1228.42 seconds
Started Aug 03 05:32:50 PM PDT 24
Finished Aug 03 05:53:18 PM PDT 24
Peak memory 201360 kb
Host smart-d8c2bb8a-37eb-4e49-adf1-b535298f7ee1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=13133112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt
_fixed.13133112
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.192476119
Short name T314
Test name
Test status
Simulation time 494951766735 ps
CPU time 1063.46 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:52:41 PM PDT 24
Peak memory 201432 kb
Host smart-81409e99-0172-4cdd-96e5-c1e1d430c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192476119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.192476119
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1238251675
Short name T689
Test name
Test status
Simulation time 169512190998 ps
CPU time 404.57 seconds
Started Aug 03 05:35:00 PM PDT 24
Finished Aug 03 05:41:44 PM PDT 24
Peak memory 201432 kb
Host smart-f6a11d1f-f2c2-452d-88d3-4a2bd27035d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238251675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1238251675
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1199478490
Short name T262
Test name
Test status
Simulation time 192363666570 ps
CPU time 114.06 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:36:52 PM PDT 24
Peak memory 201472 kb
Host smart-10476e62-d96e-4aa5-8455-f37b4f31d6ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199478490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1199478490
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.795805976
Short name T13
Test name
Test status
Simulation time 602416358086 ps
CPU time 1369.88 seconds
Started Aug 03 05:31:49 PM PDT 24
Finished Aug 03 05:54:39 PM PDT 24
Peak memory 201452 kb
Host smart-6f4b091e-c575-487b-9e94-1a365ceb38ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795805976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.795805976
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.93949567
Short name T206
Test name
Test status
Simulation time 138023175139 ps
CPU time 494.82 seconds
Started Aug 03 05:31:51 PM PDT 24
Finished Aug 03 05:40:05 PM PDT 24
Peak memory 201788 kb
Host smart-e5497c6b-ae05-43a9-8104-066318889ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93949567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.93949567
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2974026977
Short name T460
Test name
Test status
Simulation time 44820900137 ps
CPU time 7.5 seconds
Started Aug 03 05:31:50 PM PDT 24
Finished Aug 03 05:31:57 PM PDT 24
Peak memory 201292 kb
Host smart-1fbf379d-e766-4441-a175-414480777161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974026977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2974026977
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2836144804
Short name T429
Test name
Test status
Simulation time 5493780233 ps
CPU time 1.38 seconds
Started Aug 03 05:31:49 PM PDT 24
Finished Aug 03 05:31:51 PM PDT 24
Peak memory 201336 kb
Host smart-36371e2b-ca30-4076-92de-7d1d78ff2e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836144804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2836144804
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.616714409
Short name T137
Test name
Test status
Simulation time 5931213096 ps
CPU time 13.77 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:35:12 PM PDT 24
Peak memory 201388 kb
Host smart-ffa72373-23fd-4417-9eae-894d3ae3e744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616714409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.616714409
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1247777964
Short name T37
Test name
Test status
Simulation time 380423329790 ps
CPU time 769.66 seconds
Started Aug 03 05:31:49 PM PDT 24
Finished Aug 03 05:44:39 PM PDT 24
Peak memory 201424 kb
Host smart-cb8de56d-7733-4846-b2a7-da32309452b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247777964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1247777964
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3916252054
Short name T94
Test name
Test status
Simulation time 185341337515 ps
CPU time 119.04 seconds
Started Aug 03 05:31:51 PM PDT 24
Finished Aug 03 05:33:50 PM PDT 24
Peak memory 209784 kb
Host smart-09c88e7f-2e50-4115-bc44-128a44da5f8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916252054 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3916252054
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3212396466
Short name T385
Test name
Test status
Simulation time 373770119 ps
CPU time 0.97 seconds
Started Aug 03 05:32:00 PM PDT 24
Finished Aug 03 05:32:01 PM PDT 24
Peak memory 201256 kb
Host smart-0bbd30f5-de5a-4225-95aa-da9a33eaed60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212396466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3212396466
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3975069706
Short name T667
Test name
Test status
Simulation time 327635649711 ps
CPU time 332.93 seconds
Started Aug 03 05:35:01 PM PDT 24
Finished Aug 03 05:40:34 PM PDT 24
Peak memory 201368 kb
Host smart-3db06aba-c903-409d-8f53-3891d5c298d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975069706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3975069706
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.259065616
Short name T187
Test name
Test status
Simulation time 353718786730 ps
CPU time 167.78 seconds
Started Aug 03 05:35:11 PM PDT 24
Finished Aug 03 05:37:59 PM PDT 24
Peak memory 201420 kb
Host smart-ddff404f-5ddf-430a-b370-03586e972809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259065616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.259065616
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2253431041
Short name T509
Test name
Test status
Simulation time 499524586697 ps
CPU time 280.9 seconds
Started Aug 03 05:35:01 PM PDT 24
Finished Aug 03 05:39:43 PM PDT 24
Peak memory 201368 kb
Host smart-347139ef-1396-46af-93d5-a2117cb4a8c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253431041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2253431041
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2366299549
Short name T179
Test name
Test status
Simulation time 496568093626 ps
CPU time 244.83 seconds
Started Aug 03 05:35:02 PM PDT 24
Finished Aug 03 05:39:07 PM PDT 24
Peak memory 201392 kb
Host smart-2d4daec1-2516-4b1d-8b45-69dad1470d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366299549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2366299549
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2337638150
Short name T537
Test name
Test status
Simulation time 328100465821 ps
CPU time 49.27 seconds
Started Aug 03 05:35:05 PM PDT 24
Finished Aug 03 05:35:55 PM PDT 24
Peak memory 201572 kb
Host smart-3307f09b-6fdf-4bb3-be4c-7d0a74e9f9e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337638150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2337638150
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.731226461
Short name T335
Test name
Test status
Simulation time 188875549107 ps
CPU time 99.66 seconds
Started Aug 03 05:35:04 PM PDT 24
Finished Aug 03 05:36:43 PM PDT 24
Peak memory 201596 kb
Host smart-f71b912d-4975-4103-bd25-0952bf27eb27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731226461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.731226461
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1074322442
Short name T683
Test name
Test status
Simulation time 597142675817 ps
CPU time 312.32 seconds
Started Aug 03 05:35:03 PM PDT 24
Finished Aug 03 05:40:15 PM PDT 24
Peak memory 201432 kb
Host smart-682991ed-36bb-4e17-a875-51e61827485f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074322442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1074322442
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3173692953
Short name T459
Test name
Test status
Simulation time 135501304475 ps
CPU time 719.56 seconds
Started Aug 03 05:31:59 PM PDT 24
Finished Aug 03 05:43:58 PM PDT 24
Peak memory 201892 kb
Host smart-39fccd61-9e23-4699-ba54-e967cea9cb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173692953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3173692953
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3166147412
Short name T581
Test name
Test status
Simulation time 24277411005 ps
CPU time 60.36 seconds
Started Aug 03 05:32:00 PM PDT 24
Finished Aug 03 05:33:00 PM PDT 24
Peak memory 201336 kb
Host smart-a634ba72-1766-4f16-abc4-318d6d8e30bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166147412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3166147412
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3335439778
Short name T496
Test name
Test status
Simulation time 3481029567 ps
CPU time 8.11 seconds
Started Aug 03 05:33:08 PM PDT 24
Finished Aug 03 05:33:16 PM PDT 24
Peak memory 201340 kb
Host smart-ad08b9e0-8e0a-4e04-8ebb-1c4357f10f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335439778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3335439778
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.786769888
Short name T579
Test name
Test status
Simulation time 5901969764 ps
CPU time 13.35 seconds
Started Aug 03 05:35:01 PM PDT 24
Finished Aug 03 05:35:14 PM PDT 24
Peak memory 201356 kb
Host smart-c5611af7-f382-4585-9e98-7e5aa6ea9320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786769888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.786769888
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1946032951
Short name T102
Test name
Test status
Simulation time 172441406364 ps
CPU time 53.18 seconds
Started Aug 03 05:32:01 PM PDT 24
Finished Aug 03 05:32:55 PM PDT 24
Peak memory 209788 kb
Host smart-08098c0a-a83a-4bf6-bdae-4b641d435290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946032951 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1946032951
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1944019018
Short name T505
Test name
Test status
Simulation time 376844880 ps
CPU time 0.85 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:28:41 PM PDT 24
Peak memory 201204 kb
Host smart-0c0f67ce-9d7e-4732-b942-dacaef5de096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944019018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1944019018
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.606971732
Short name T151
Test name
Test status
Simulation time 349698409259 ps
CPU time 796.27 seconds
Started Aug 03 05:28:41 PM PDT 24
Finished Aug 03 05:41:57 PM PDT 24
Peak memory 201420 kb
Host smart-b6f8b97d-8b21-4297-a1db-492d79688809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606971732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.606971732
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1520106027
Short name T726
Test name
Test status
Simulation time 326247063826 ps
CPU time 188.87 seconds
Started Aug 03 05:28:38 PM PDT 24
Finished Aug 03 05:31:47 PM PDT 24
Peak memory 201428 kb
Host smart-b42378ab-9bb8-4bb7-97ab-8e1b0c403c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520106027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1520106027
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4001538624
Short name T586
Test name
Test status
Simulation time 167457682379 ps
CPU time 197.9 seconds
Started Aug 03 05:28:35 PM PDT 24
Finished Aug 03 05:31:53 PM PDT 24
Peak memory 201392 kb
Host smart-01569162-31eb-4f87-a169-1d9eef52b8b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001538624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4001538624
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2038054339
Short name T499
Test name
Test status
Simulation time 485682739905 ps
CPU time 605.62 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:38:42 PM PDT 24
Peak memory 201424 kb
Host smart-159e8fa7-f4b8-44e1-9e5f-3ec9382cc9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038054339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2038054339
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3206679832
Short name T754
Test name
Test status
Simulation time 161945970138 ps
CPU time 31.49 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:29:08 PM PDT 24
Peak memory 201388 kb
Host smart-a02863c8-7176-490a-b81f-eec9197dfa4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206679832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3206679832
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2138528400
Short name T246
Test name
Test status
Simulation time 548472948995 ps
CPU time 380.68 seconds
Started Aug 03 05:28:34 PM PDT 24
Finished Aug 03 05:34:55 PM PDT 24
Peak memory 201408 kb
Host smart-147c1802-0c69-41cb-a907-bd970368789b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138528400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2138528400
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3243502078
Short name T600
Test name
Test status
Simulation time 617521221770 ps
CPU time 698.08 seconds
Started Aug 03 05:28:47 PM PDT 24
Finished Aug 03 05:40:25 PM PDT 24
Peak memory 201444 kb
Host smart-bdaf3f9a-4828-43e9-96c3-b85282c051f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243502078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3243502078
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3514667519
Short name T518
Test name
Test status
Simulation time 69287016917 ps
CPU time 258.82 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:32:58 PM PDT 24
Peak memory 201848 kb
Host smart-2dcb4b8c-fb69-458c-a9cf-cd4748c33724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514667519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3514667519
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4239757635
Short name T397
Test name
Test status
Simulation time 32341693015 ps
CPU time 72.4 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:29:51 PM PDT 24
Peak memory 201324 kb
Host smart-4f5f1121-7d6b-442f-a1a7-af9831b5e102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239757635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4239757635
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1922799063
Short name T371
Test name
Test status
Simulation time 3598725991 ps
CPU time 8.8 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:28:48 PM PDT 24
Peak memory 201328 kb
Host smart-ef5908ef-ce63-40a1-b9e3-c6424f4470e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922799063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1922799063
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.701612149
Short name T4
Test name
Test status
Simulation time 8145984493 ps
CPU time 5.16 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:28:44 PM PDT 24
Peak memory 217160 kb
Host smart-a7eb2efd-1304-48cb-832d-49cea3343436
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701612149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.701612149
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.728462552
Short name T107
Test name
Test status
Simulation time 5973996710 ps
CPU time 4.13 seconds
Started Aug 03 05:28:36 PM PDT 24
Finished Aug 03 05:28:40 PM PDT 24
Peak memory 201372 kb
Host smart-276a6e2c-d495-4b4c-922b-6a8b47122bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728462552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.728462552
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.964388621
Short name T704
Test name
Test status
Simulation time 520804265 ps
CPU time 0.71 seconds
Started Aug 03 05:32:05 PM PDT 24
Finished Aug 03 05:32:06 PM PDT 24
Peak memory 201196 kb
Host smart-73974db7-e616-4fbc-a591-efa6321dbdfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964388621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.964388621
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3478406644
Short name T596
Test name
Test status
Simulation time 192064175739 ps
CPU time 350.19 seconds
Started Aug 03 05:32:04 PM PDT 24
Finished Aug 03 05:37:55 PM PDT 24
Peak memory 201496 kb
Host smart-020721f7-0bb9-43f3-949a-8c3d356fde36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478406644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3478406644
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.446110817
Short name T643
Test name
Test status
Simulation time 328687352530 ps
CPU time 617.32 seconds
Started Aug 03 05:32:02 PM PDT 24
Finished Aug 03 05:42:19 PM PDT 24
Peak memory 201384 kb
Host smart-5eebb1b2-752a-4f1f-825b-eb3734a78adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446110817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.446110817
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2931040786
Short name T394
Test name
Test status
Simulation time 328582905121 ps
CPU time 99.91 seconds
Started Aug 03 05:32:00 PM PDT 24
Finished Aug 03 05:33:40 PM PDT 24
Peak memory 201388 kb
Host smart-afeb7b71-2d16-4b34-b89f-8dcd5bd3b0d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931040786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2931040786
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2270561406
Short name T156
Test name
Test status
Simulation time 490139892627 ps
CPU time 556.23 seconds
Started Aug 03 05:31:59 PM PDT 24
Finished Aug 03 05:41:15 PM PDT 24
Peak memory 201416 kb
Host smart-65bb7840-135d-4285-8433-59d8d87b1bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270561406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2270561406
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.512158656
Short name T424
Test name
Test status
Simulation time 318846031822 ps
CPU time 309.91 seconds
Started Aug 03 05:32:00 PM PDT 24
Finished Aug 03 05:37:10 PM PDT 24
Peak memory 201424 kb
Host smart-44902723-ef9d-47e0-81e7-6a9ef0db6b21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=512158656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.512158656
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.372012209
Short name T140
Test name
Test status
Simulation time 170421789045 ps
CPU time 86.87 seconds
Started Aug 03 05:31:58 PM PDT 24
Finished Aug 03 05:33:25 PM PDT 24
Peak memory 201452 kb
Host smart-b2ac8912-989a-4b50-b5de-01cb6f01913f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372012209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.372012209
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3039042413
Short name T488
Test name
Test status
Simulation time 199230335770 ps
CPU time 84.79 seconds
Started Aug 03 05:32:04 PM PDT 24
Finished Aug 03 05:33:28 PM PDT 24
Peak memory 201444 kb
Host smart-bf2ed6fd-879f-447f-87e7-e6e2bed6bb15
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039042413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3039042413
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3177185137
Short name T200
Test name
Test status
Simulation time 81543046967 ps
CPU time 432.31 seconds
Started Aug 03 05:32:06 PM PDT 24
Finished Aug 03 05:39:18 PM PDT 24
Peak memory 201832 kb
Host smart-b14efc35-5e97-419f-b681-2403d7d840c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177185137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3177185137
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3521092142
Short name T425
Test name
Test status
Simulation time 46585776795 ps
CPU time 55.3 seconds
Started Aug 03 05:32:06 PM PDT 24
Finished Aug 03 05:33:01 PM PDT 24
Peak memory 201292 kb
Host smart-7c248a22-45b1-4693-b238-705f2193db55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521092142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3521092142
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.926842621
Short name T372
Test name
Test status
Simulation time 3864695343 ps
CPU time 2.86 seconds
Started Aug 03 05:32:04 PM PDT 24
Finished Aug 03 05:32:07 PM PDT 24
Peak memory 201360 kb
Host smart-6e7fd72e-4797-4143-a930-ce5c2d4e8eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926842621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.926842621
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3660092608
Short name T410
Test name
Test status
Simulation time 5887811389 ps
CPU time 7.4 seconds
Started Aug 03 05:32:01 PM PDT 24
Finished Aug 03 05:32:09 PM PDT 24
Peak memory 201324 kb
Host smart-a94d4a0b-62fd-469f-9c6b-b3de9d16b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660092608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3660092608
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3570585376
Short name T616
Test name
Test status
Simulation time 65398936514 ps
CPU time 57.45 seconds
Started Aug 03 05:32:06 PM PDT 24
Finished Aug 03 05:33:03 PM PDT 24
Peak memory 201656 kb
Host smart-c75a4801-c57b-4946-b298-74a1f8bc5545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570585376 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3570585376
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1231188530
Short name T588
Test name
Test status
Simulation time 607092822 ps
CPU time 0.69 seconds
Started Aug 03 05:32:15 PM PDT 24
Finished Aug 03 05:32:15 PM PDT 24
Peak memory 201244 kb
Host smart-5cc95e18-97d2-4ae3-a8ec-7ba19d49a387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231188530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1231188530
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3182889569
Short name T302
Test name
Test status
Simulation time 164522147080 ps
CPU time 85.29 seconds
Started Aug 03 05:35:02 PM PDT 24
Finished Aug 03 05:36:28 PM PDT 24
Peak memory 201432 kb
Host smart-d7606850-49ad-4dbc-88a8-c3a6e349e338
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182889569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3182889569
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2625409799
Short name T336
Test name
Test status
Simulation time 360935784065 ps
CPU time 349.07 seconds
Started Aug 03 05:35:06 PM PDT 24
Finished Aug 03 05:40:55 PM PDT 24
Peak memory 201404 kb
Host smart-0c8b07e0-5427-43b2-953d-4fa01bfb136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625409799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2625409799
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3210986001
Short name T270
Test name
Test status
Simulation time 332957655717 ps
CPU time 124.84 seconds
Started Aug 03 05:35:04 PM PDT 24
Finished Aug 03 05:37:09 PM PDT 24
Peak memory 201496 kb
Host smart-2c71a341-20c0-42cd-8d1c-05eb3827fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210986001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3210986001
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2913799067
Short name T639
Test name
Test status
Simulation time 326955249834 ps
CPU time 811.67 seconds
Started Aug 03 05:35:06 PM PDT 24
Finished Aug 03 05:48:38 PM PDT 24
Peak memory 201408 kb
Host smart-8e90180f-dcaa-4344-8a67-62c39edbbdaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913799067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2913799067
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2859621940
Short name T774
Test name
Test status
Simulation time 482745834368 ps
CPU time 544.76 seconds
Started Aug 03 05:35:25 PM PDT 24
Finished Aug 03 05:44:30 PM PDT 24
Peak memory 201372 kb
Host smart-e544078c-9bc3-4c18-962a-ffdc32776595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859621940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2859621940
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3076830266
Short name T358
Test name
Test status
Simulation time 325824724079 ps
CPU time 388.69 seconds
Started Aug 03 05:35:06 PM PDT 24
Finished Aug 03 05:41:34 PM PDT 24
Peak memory 201396 kb
Host smart-9a1233a7-3cee-4529-95b5-0b23306a58ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076830266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3076830266
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.504563415
Short name T285
Test name
Test status
Simulation time 406026923999 ps
CPU time 975.64 seconds
Started Aug 03 05:35:10 PM PDT 24
Finished Aug 03 05:51:26 PM PDT 24
Peak memory 201444 kb
Host smart-91be5d95-857d-4e45-9b15-a08dfe7f092a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504563415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.504563415
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3688310184
Short name T671
Test name
Test status
Simulation time 199069841322 ps
CPU time 104.43 seconds
Started Aug 03 05:32:24 PM PDT 24
Finished Aug 03 05:34:09 PM PDT 24
Peak memory 201416 kb
Host smart-4660151a-7b4e-4ebe-bdbd-6f2350635bec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688310184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3688310184
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1207618015
Short name T40
Test name
Test status
Simulation time 42659413293 ps
CPU time 48.32 seconds
Started Aug 03 05:32:15 PM PDT 24
Finished Aug 03 05:33:03 PM PDT 24
Peak memory 201368 kb
Host smart-7593ccf2-81e8-4405-ade7-4788ac0a42d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207618015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1207618015
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.352820233
Short name T411
Test name
Test status
Simulation time 4882126036 ps
CPU time 12.81 seconds
Started Aug 03 05:32:17 PM PDT 24
Finished Aug 03 05:32:30 PM PDT 24
Peak memory 201360 kb
Host smart-aca17bf2-d7c1-4e2f-9355-e48dc00bc57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352820233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.352820233
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.837412496
Short name T360
Test name
Test status
Simulation time 5856835812 ps
CPU time 6.66 seconds
Started Aug 03 05:32:04 PM PDT 24
Finished Aug 03 05:32:11 PM PDT 24
Peak memory 201360 kb
Host smart-21041a2e-9115-455f-b49b-81defc7a2b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837412496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.837412496
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3814567046
Short name T543
Test name
Test status
Simulation time 142173487255 ps
CPU time 548.81 seconds
Started Aug 03 05:32:17 PM PDT 24
Finished Aug 03 05:41:26 PM PDT 24
Peak memory 201900 kb
Host smart-ebaebfa1-461b-4fba-8b17-f943d647305b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814567046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3814567046
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2053513915
Short name T293
Test name
Test status
Simulation time 76505536727 ps
CPU time 176.88 seconds
Started Aug 03 05:32:16 PM PDT 24
Finished Aug 03 05:35:13 PM PDT 24
Peak memory 209784 kb
Host smart-9dfd26f2-3ada-4d50-b1cd-eba812ac1b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053513915 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2053513915
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1298155982
Short name T384
Test name
Test status
Simulation time 370691326 ps
CPU time 0.71 seconds
Started Aug 03 05:32:47 PM PDT 24
Finished Aug 03 05:32:48 PM PDT 24
Peak memory 201256 kb
Host smart-d0758d65-2118-4305-9457-2864af578c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298155982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1298155982
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3938204646
Short name T244
Test name
Test status
Simulation time 512892896206 ps
CPU time 984.85 seconds
Started Aug 03 05:34:57 PM PDT 24
Finished Aug 03 05:51:22 PM PDT 24
Peak memory 201460 kb
Host smart-a8edbe24-55e7-4131-a8e5-a8c7469d5868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938204646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3938204646
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.487792721
Short name T662
Test name
Test status
Simulation time 324852433639 ps
CPU time 224.87 seconds
Started Aug 03 05:35:05 PM PDT 24
Finished Aug 03 05:38:50 PM PDT 24
Peak memory 201420 kb
Host smart-dbc6e713-3dbf-41d3-8f9e-7c098e33f58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487792721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.487792721
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4233545038
Short name T375
Test name
Test status
Simulation time 488832402785 ps
CPU time 291.33 seconds
Started Aug 03 05:35:04 PM PDT 24
Finished Aug 03 05:39:55 PM PDT 24
Peak memory 201428 kb
Host smart-5887dc9b-5387-44cf-beda-ef95f41b149b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233545038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4233545038
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1345601484
Short name T320
Test name
Test status
Simulation time 164010898627 ps
CPU time 90.36 seconds
Started Aug 03 05:35:04 PM PDT 24
Finished Aug 03 05:36:34 PM PDT 24
Peak memory 201456 kb
Host smart-6c442faf-ba34-4a1b-974c-0593fa773ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345601484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1345601484
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2430532720
Short name T367
Test name
Test status
Simulation time 328422455402 ps
CPU time 834.19 seconds
Started Aug 03 05:35:06 PM PDT 24
Finished Aug 03 05:49:00 PM PDT 24
Peak memory 201400 kb
Host smart-3deaf5f2-4e6a-4beb-b7ea-c346edceef07
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430532720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2430532720
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1625253916
Short name T221
Test name
Test status
Simulation time 355354767954 ps
CPU time 207.28 seconds
Started Aug 03 05:35:07 PM PDT 24
Finished Aug 03 05:38:35 PM PDT 24
Peak memory 201428 kb
Host smart-88acea2c-7b74-4c70-a447-9479748ec513
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625253916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1625253916
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.635106653
Short name T354
Test name
Test status
Simulation time 203792807003 ps
CPU time 280.29 seconds
Started Aug 03 05:33:24 PM PDT 24
Finished Aug 03 05:38:04 PM PDT 24
Peak memory 201508 kb
Host smart-e2a8b96f-013b-4bf9-9ea2-492ddfa43a35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635106653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.635106653
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2220107545
Short name T52
Test name
Test status
Simulation time 76014994528 ps
CPU time 376.98 seconds
Started Aug 03 05:32:24 PM PDT 24
Finished Aug 03 05:38:41 PM PDT 24
Peak memory 201864 kb
Host smart-45f01b57-9324-498d-9652-af5fce06ce5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220107545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2220107545
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3879780832
Short name T387
Test name
Test status
Simulation time 45433391021 ps
CPU time 57.17 seconds
Started Aug 03 05:34:56 PM PDT 24
Finished Aug 03 05:35:54 PM PDT 24
Peak memory 201388 kb
Host smart-a699916a-d84f-47c9-a3d3-6f85b11caac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879780832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3879780832
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3476258746
Short name T558
Test name
Test status
Simulation time 3698655103 ps
CPU time 5.06 seconds
Started Aug 03 05:34:55 PM PDT 24
Finished Aug 03 05:35:00 PM PDT 24
Peak memory 201344 kb
Host smart-e4e73974-8fd4-4df9-bdde-71852862330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476258746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3476258746
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.996866295
Short name T785
Test name
Test status
Simulation time 5735085433 ps
CPU time 7.78 seconds
Started Aug 03 05:32:17 PM PDT 24
Finished Aug 03 05:32:25 PM PDT 24
Peak memory 201364 kb
Host smart-b6dbeeda-d356-4cfc-83d4-d46c61899d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996866295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.996866295
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.393813478
Short name T663
Test name
Test status
Simulation time 358853622 ps
CPU time 0.69 seconds
Started Aug 03 05:32:36 PM PDT 24
Finished Aug 03 05:32:36 PM PDT 24
Peak memory 201240 kb
Host smart-ebcd8793-181e-455b-95c7-e3e126f009f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393813478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.393813478
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1807301253
Short name T216
Test name
Test status
Simulation time 204419152581 ps
CPU time 117 seconds
Started Aug 03 05:32:30 PM PDT 24
Finished Aug 03 05:34:27 PM PDT 24
Peak memory 201332 kb
Host smart-961c8f5a-9fa9-4a64-92b7-84f8e83511e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807301253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1807301253
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1083686386
Short name T93
Test name
Test status
Simulation time 360180783045 ps
CPU time 854.71 seconds
Started Aug 03 05:32:30 PM PDT 24
Finished Aug 03 05:46:45 PM PDT 24
Peak memory 201500 kb
Host smart-c2c45169-3fd6-46db-afaa-1d2135f00e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083686386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1083686386
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2890669884
Short name T765
Test name
Test status
Simulation time 335893916879 ps
CPU time 205.75 seconds
Started Aug 03 05:32:30 PM PDT 24
Finished Aug 03 05:35:56 PM PDT 24
Peak memory 201448 kb
Host smart-0093be01-d5d5-46ca-b8a1-a59fb2a9680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890669884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2890669884
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2714835315
Short name T540
Test name
Test status
Simulation time 172079420267 ps
CPU time 101.83 seconds
Started Aug 03 05:32:31 PM PDT 24
Finished Aug 03 05:34:13 PM PDT 24
Peak memory 201444 kb
Host smart-9225e7d3-22ee-4419-b83a-e4b6fddedc27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714835315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2714835315
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2586755050
Short name T512
Test name
Test status
Simulation time 161560056778 ps
CPU time 82.89 seconds
Started Aug 03 05:32:31 PM PDT 24
Finished Aug 03 05:33:54 PM PDT 24
Peak memory 201488 kb
Host smart-bb417b60-d132-4b4b-b462-633dad30f907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586755050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2586755050
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.4108599160
Short name T407
Test name
Test status
Simulation time 325830029878 ps
CPU time 398.82 seconds
Started Aug 03 05:32:30 PM PDT 24
Finished Aug 03 05:39:09 PM PDT 24
Peak memory 201448 kb
Host smart-ffac0d08-b358-4349-9eb1-d77089714454
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108599160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.4108599160
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2547211889
Short name T723
Test name
Test status
Simulation time 355463060354 ps
CPU time 196.42 seconds
Started Aug 03 05:32:30 PM PDT 24
Finished Aug 03 05:35:46 PM PDT 24
Peak memory 201468 kb
Host smart-af08a916-23ff-486a-9020-b31b4ff86258
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547211889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2547211889
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1429414912
Short name T705
Test name
Test status
Simulation time 201811549765 ps
CPU time 122.32 seconds
Started Aug 03 05:32:29 PM PDT 24
Finished Aug 03 05:34:32 PM PDT 24
Peak memory 201416 kb
Host smart-cbb96624-7092-4bb8-b631-1505e4adedf9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429414912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1429414912
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.162535997
Short name T470
Test name
Test status
Simulation time 126982389310 ps
CPU time 448.03 seconds
Started Aug 03 05:32:36 PM PDT 24
Finished Aug 03 05:40:04 PM PDT 24
Peak memory 201820 kb
Host smart-75393675-69e5-49c4-bb3c-de423277cea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162535997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.162535997
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.377301842
Short name T660
Test name
Test status
Simulation time 30081634795 ps
CPU time 33.69 seconds
Started Aug 03 05:32:36 PM PDT 24
Finished Aug 03 05:33:10 PM PDT 24
Peak memory 201292 kb
Host smart-6b89ae08-75b4-467b-87cd-3d552c67e35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377301842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.377301842
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4181192386
Short name T523
Test name
Test status
Simulation time 5196585038 ps
CPU time 6.86 seconds
Started Aug 03 05:32:36 PM PDT 24
Finished Aug 03 05:32:43 PM PDT 24
Peak memory 201336 kb
Host smart-01e1dad8-64aa-41e9-b6d1-c0fbbf1643be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181192386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4181192386
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3011314226
Short name T692
Test name
Test status
Simulation time 5831094182 ps
CPU time 4.19 seconds
Started Aug 03 05:32:24 PM PDT 24
Finished Aug 03 05:32:28 PM PDT 24
Peak memory 201296 kb
Host smart-60b55538-7558-4b1b-becd-5668126fb3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011314226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3011314226
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.594734341
Short name T722
Test name
Test status
Simulation time 179740870855 ps
CPU time 172.54 seconds
Started Aug 03 05:32:35 PM PDT 24
Finished Aug 03 05:35:28 PM PDT 24
Peak memory 210156 kb
Host smart-d1558284-13e4-4a91-9f7c-cfb03b9e16f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594734341 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.594734341
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1403823680
Short name T452
Test name
Test status
Simulation time 378626933 ps
CPU time 0.97 seconds
Started Aug 03 05:32:48 PM PDT 24
Finished Aug 03 05:32:49 PM PDT 24
Peak memory 201248 kb
Host smart-df0a8115-0378-4a54-b4b3-21292b27eb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403823680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1403823680
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3047526939
Short name T710
Test name
Test status
Simulation time 582383298052 ps
CPU time 86.92 seconds
Started Aug 03 05:32:43 PM PDT 24
Finished Aug 03 05:34:10 PM PDT 24
Peak memory 201428 kb
Host smart-4d55148d-08b9-419f-8989-679abcf175b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047526939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3047526939
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2748963664
Short name T576
Test name
Test status
Simulation time 163996957933 ps
CPU time 241.38 seconds
Started Aug 03 05:32:44 PM PDT 24
Finished Aug 03 05:36:46 PM PDT 24
Peak memory 201440 kb
Host smart-16cc9198-c0f6-42ce-a8c7-1d21c2431cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748963664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2748963664
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.4132456512
Short name T490
Test name
Test status
Simulation time 166107029562 ps
CPU time 101.11 seconds
Started Aug 03 05:32:45 PM PDT 24
Finished Aug 03 05:34:26 PM PDT 24
Peak memory 201492 kb
Host smart-3e2f65af-0c9b-499a-b059-243ebd98204a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132456512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.4132456512
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1813617426
Short name T440
Test name
Test status
Simulation time 160293593142 ps
CPU time 254.96 seconds
Started Aug 03 05:32:43 PM PDT 24
Finished Aug 03 05:36:58 PM PDT 24
Peak memory 201356 kb
Host smart-68deb032-bc1b-4ad7-8933-213b161631fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813617426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1813617426
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4286552751
Short name T433
Test name
Test status
Simulation time 326121037314 ps
CPU time 206.17 seconds
Started Aug 03 05:32:43 PM PDT 24
Finished Aug 03 05:36:10 PM PDT 24
Peak memory 201404 kb
Host smart-38f1f1a8-dccd-4a40-b2cf-bba701e8638b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286552751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4286552751
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1129161835
Short name T304
Test name
Test status
Simulation time 552335073965 ps
CPU time 1235.12 seconds
Started Aug 03 05:32:42 PM PDT 24
Finished Aug 03 05:53:18 PM PDT 24
Peak memory 201432 kb
Host smart-8372f793-9032-443e-89d1-02b7a4c0270c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129161835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1129161835
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1656560199
Short name T661
Test name
Test status
Simulation time 590333638545 ps
CPU time 360.04 seconds
Started Aug 03 05:32:42 PM PDT 24
Finished Aug 03 05:38:42 PM PDT 24
Peak memory 201416 kb
Host smart-04907193-95e4-4309-82ad-f455d305d123
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656560199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1656560199
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3417718846
Short name T673
Test name
Test status
Simulation time 94951419235 ps
CPU time 385.57 seconds
Started Aug 03 05:32:52 PM PDT 24
Finished Aug 03 05:39:18 PM PDT 24
Peak memory 201756 kb
Host smart-e2ed7838-c30b-46ea-9cad-5841fbda753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417718846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3417718846
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2985757960
Short name T642
Test name
Test status
Simulation time 28917719491 ps
CPU time 67.84 seconds
Started Aug 03 05:32:50 PM PDT 24
Finished Aug 03 05:33:58 PM PDT 24
Peak memory 201264 kb
Host smart-734b858e-d772-4c94-a411-e758b6ce2af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985757960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2985757960
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1855903481
Short name T687
Test name
Test status
Simulation time 3481535972 ps
CPU time 1.75 seconds
Started Aug 03 05:32:41 PM PDT 24
Finished Aug 03 05:32:43 PM PDT 24
Peak memory 201368 kb
Host smart-3487562f-ab5a-4544-bf7c-e365c155fa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855903481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1855903481
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.4075373331
Short name T395
Test name
Test status
Simulation time 6023706693 ps
CPU time 4.46 seconds
Started Aug 03 05:32:43 PM PDT 24
Finished Aug 03 05:32:47 PM PDT 24
Peak memory 201376 kb
Host smart-e98296b4-804c-46f5-af99-39731e55bd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075373331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.4075373331
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2317908911
Short name T771
Test name
Test status
Simulation time 11598660493 ps
CPU time 7.64 seconds
Started Aug 03 05:32:49 PM PDT 24
Finished Aug 03 05:32:57 PM PDT 24
Peak memory 201324 kb
Host smart-100060e5-c614-4863-aa62-eda81399bbae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317908911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2317908911
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.50481621
Short name T308
Test name
Test status
Simulation time 175256458399 ps
CPU time 113.01 seconds
Started Aug 03 05:32:52 PM PDT 24
Finished Aug 03 05:34:45 PM PDT 24
Peak memory 210096 kb
Host smart-e0389e1b-e5ca-463e-af63-3903a39134cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50481621 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.50481621
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2412140586
Short name T611
Test name
Test status
Simulation time 392832873 ps
CPU time 0.83 seconds
Started Aug 03 05:32:58 PM PDT 24
Finished Aug 03 05:32:58 PM PDT 24
Peak memory 201160 kb
Host smart-7dac9e41-3600-490e-b9f7-590df2a83dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412140586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2412140586
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.72508739
Short name T697
Test name
Test status
Simulation time 180828174655 ps
CPU time 209.49 seconds
Started Aug 03 05:32:53 PM PDT 24
Finished Aug 03 05:36:23 PM PDT 24
Peak memory 201384 kb
Host smart-ab1458f7-caa9-4971-83c5-95a83274173e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72508739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gatin
g.72508739
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2895438786
Short name T85
Test name
Test status
Simulation time 164492378606 ps
CPU time 74.4 seconds
Started Aug 03 05:32:51 PM PDT 24
Finished Aug 03 05:34:06 PM PDT 24
Peak memory 201432 kb
Host smart-de8f700d-9f5f-4ea1-9a9e-5d3a90941494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895438786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2895438786
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3432172305
Short name T300
Test name
Test status
Simulation time 324795531053 ps
CPU time 284.61 seconds
Started Aug 03 05:32:49 PM PDT 24
Finished Aug 03 05:37:34 PM PDT 24
Peak memory 201436 kb
Host smart-3a75755d-031f-49b4-9956-dd5a24522d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432172305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3432172305
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2429005902
Short name T724
Test name
Test status
Simulation time 328925418466 ps
CPU time 749.11 seconds
Started Aug 03 05:32:47 PM PDT 24
Finished Aug 03 05:45:17 PM PDT 24
Peak memory 201472 kb
Host smart-fc8c2aa3-1dac-474a-91d1-3f38ab481f5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429005902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2429005902
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.591956557
Short name T191
Test name
Test status
Simulation time 327112664959 ps
CPU time 81.27 seconds
Started Aug 03 05:32:49 PM PDT 24
Finished Aug 03 05:34:11 PM PDT 24
Peak memory 201448 kb
Host smart-844c2fb5-38c1-4c3d-bf53-65f696355550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591956557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.591956557
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.427014938
Short name T790
Test name
Test status
Simulation time 324637769580 ps
CPU time 104.63 seconds
Started Aug 03 05:32:49 PM PDT 24
Finished Aug 03 05:34:34 PM PDT 24
Peak memory 201464 kb
Host smart-8d341af6-241f-433a-9684-82b9e9a9f6d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=427014938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.427014938
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3086759522
Short name T694
Test name
Test status
Simulation time 364507243392 ps
CPU time 185.25 seconds
Started Aug 03 05:32:52 PM PDT 24
Finished Aug 03 05:35:58 PM PDT 24
Peak memory 201488 kb
Host smart-415b3bfb-813b-4044-850c-03ce18a887bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086759522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3086759522
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1684354092
Short name T575
Test name
Test status
Simulation time 207373084902 ps
CPU time 114.23 seconds
Started Aug 03 05:32:52 PM PDT 24
Finished Aug 03 05:34:46 PM PDT 24
Peak memory 201356 kb
Host smart-fc129cd2-c86a-4737-ae48-511d35c81bb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684354092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1684354092
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3807032120
Short name T545
Test name
Test status
Simulation time 111146065099 ps
CPU time 567.68 seconds
Started Aug 03 05:32:56 PM PDT 24
Finished Aug 03 05:42:24 PM PDT 24
Peak memory 201768 kb
Host smart-ffd51447-78d6-4779-ae22-0fac907e03e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807032120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3807032120
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2239949894
Short name T473
Test name
Test status
Simulation time 37229902890 ps
CPU time 43.94 seconds
Started Aug 03 05:32:58 PM PDT 24
Finished Aug 03 05:33:42 PM PDT 24
Peak memory 201308 kb
Host smart-060e5da1-f592-4c73-b0a5-580611c3e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239949894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2239949894
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4235438456
Short name T400
Test name
Test status
Simulation time 5006359789 ps
CPU time 3.46 seconds
Started Aug 03 05:32:54 PM PDT 24
Finished Aug 03 05:32:57 PM PDT 24
Peak memory 201384 kb
Host smart-862536ba-f59c-41af-be2b-5823992e90d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235438456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4235438456
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2730384418
Short name T401
Test name
Test status
Simulation time 6014737078 ps
CPU time 15.03 seconds
Started Aug 03 05:32:52 PM PDT 24
Finished Aug 03 05:33:07 PM PDT 24
Peak memory 201296 kb
Host smart-7e75d9f9-33a1-4123-a021-4e362db887a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730384418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2730384418
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.801207877
Short name T203
Test name
Test status
Simulation time 297946765958 ps
CPU time 894.1 seconds
Started Aug 03 05:32:58 PM PDT 24
Finished Aug 03 05:47:53 PM PDT 24
Peak memory 209924 kb
Host smart-ba7f3528-a888-4034-8b06-6f3ccde17bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801207877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
801207877
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3875847707
Short name T797
Test name
Test status
Simulation time 27004282386 ps
CPU time 80.85 seconds
Started Aug 03 05:32:57 PM PDT 24
Finished Aug 03 05:34:18 PM PDT 24
Peak memory 210552 kb
Host smart-08a4009f-2bf1-4a76-ae76-b0d363459534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875847707 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3875847707
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.263415920
Short name T799
Test name
Test status
Simulation time 360434066 ps
CPU time 1.45 seconds
Started Aug 03 05:33:19 PM PDT 24
Finished Aug 03 05:33:20 PM PDT 24
Peak memory 201216 kb
Host smart-b71bb808-7033-4d30-a2c5-4d146ec26ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263415920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.263415920
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2993736134
Short name T275
Test name
Test status
Simulation time 520062049528 ps
CPU time 1044.59 seconds
Started Aug 03 05:34:59 PM PDT 24
Finished Aug 03 05:52:24 PM PDT 24
Peak memory 201456 kb
Host smart-0f6a79f6-781e-49a4-aa5b-62b3a4d1298a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993736134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2993736134
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2046908202
Short name T316
Test name
Test status
Simulation time 162325296789 ps
CPU time 197.25 seconds
Started Aug 03 05:34:59 PM PDT 24
Finished Aug 03 05:38:16 PM PDT 24
Peak memory 201472 kb
Host smart-5eeb515c-928f-48c9-8f07-60bc6d03e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046908202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2046908202
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1759926569
Short name T229
Test name
Test status
Simulation time 166892332539 ps
CPU time 360.17 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:40:58 PM PDT 24
Peak memory 201460 kb
Host smart-b1393695-e548-418b-9fe5-2ab47e447aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759926569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1759926569
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.789616361
Short name T555
Test name
Test status
Simulation time 499518759129 ps
CPU time 296 seconds
Started Aug 03 05:34:59 PM PDT 24
Finished Aug 03 05:39:55 PM PDT 24
Peak memory 201400 kb
Host smart-a2314f2b-3006-4a38-91a2-413859285c68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=789616361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.789616361
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.201514497
Short name T698
Test name
Test status
Simulation time 492450335434 ps
CPU time 1071.51 seconds
Started Aug 03 05:35:01 PM PDT 24
Finished Aug 03 05:52:53 PM PDT 24
Peak memory 201376 kb
Host smart-237f0dd0-00a2-4532-9d70-38584a28977a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=201514497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.201514497
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2000626588
Short name T652
Test name
Test status
Simulation time 437929220577 ps
CPU time 230.34 seconds
Started Aug 03 05:34:57 PM PDT 24
Finished Aug 03 05:38:48 PM PDT 24
Peak memory 201472 kb
Host smart-922f96e3-606e-4a5a-bc2b-a8fff3e10d2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000626588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2000626588
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1884716501
Short name T432
Test name
Test status
Simulation time 407531839829 ps
CPU time 547.03 seconds
Started Aug 03 05:34:57 PM PDT 24
Finished Aug 03 05:44:04 PM PDT 24
Peak memory 201428 kb
Host smart-512fb247-a553-46d9-be8d-2eb69e131afb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884716501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1884716501
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3567264932
Short name T351
Test name
Test status
Simulation time 90575360490 ps
CPU time 407.9 seconds
Started Aug 03 05:34:48 PM PDT 24
Finished Aug 03 05:41:36 PM PDT 24
Peak memory 201744 kb
Host smart-e9de74dd-70b0-41cc-a91c-576775491ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567264932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3567264932
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1511368063
Short name T418
Test name
Test status
Simulation time 35054011041 ps
CPU time 41 seconds
Started Aug 03 05:34:58 PM PDT 24
Finished Aug 03 05:35:39 PM PDT 24
Peak memory 201300 kb
Host smart-6cfb2ee2-82b6-405c-917e-afe2ee5c0342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511368063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1511368063
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1482062111
Short name T548
Test name
Test status
Simulation time 4948909444 ps
CPU time 3.61 seconds
Started Aug 03 05:34:59 PM PDT 24
Finished Aug 03 05:35:03 PM PDT 24
Peak memory 201360 kb
Host smart-e0a8762c-ebdd-422b-a4b1-d474b23c2e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482062111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1482062111
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2452735771
Short name T434
Test name
Test status
Simulation time 5956247178 ps
CPU time 8.89 seconds
Started Aug 03 05:34:59 PM PDT 24
Finished Aug 03 05:35:08 PM PDT 24
Peak memory 201384 kb
Host smart-461dbda4-96d9-4e89-a77c-2f1c924f10b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452735771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2452735771
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3654662083
Short name T242
Test name
Test status
Simulation time 164306074350 ps
CPU time 86.2 seconds
Started Aug 03 05:33:17 PM PDT 24
Finished Aug 03 05:34:43 PM PDT 24
Peak memory 201444 kb
Host smart-bf553206-d9de-42b4-9606-e9e7bf21b8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654662083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3654662083
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.4148031794
Short name T23
Test name
Test status
Simulation time 88766339687 ps
CPU time 44.4 seconds
Started Aug 03 05:33:16 PM PDT 24
Finished Aug 03 05:34:00 PM PDT 24
Peak memory 210120 kb
Host smart-b6e0a817-fd79-4f89-82c3-ba8f00e7bfe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148031794 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.4148031794
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3380763107
Short name T390
Test name
Test status
Simulation time 366610738 ps
CPU time 1.42 seconds
Started Aug 03 05:34:59 PM PDT 24
Finished Aug 03 05:35:00 PM PDT 24
Peak memory 201208 kb
Host smart-9188f694-3301-4bec-9812-f7ef0b536e81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380763107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3380763107
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1627769458
Short name T778
Test name
Test status
Simulation time 161882356468 ps
CPU time 89.6 seconds
Started Aug 03 05:33:25 PM PDT 24
Finished Aug 03 05:34:54 PM PDT 24
Peak memory 201360 kb
Host smart-ac5a45d9-19b8-4788-924b-564e85028057
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627769458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1627769458
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.67620100
Short name T189
Test name
Test status
Simulation time 550081088602 ps
CPU time 341.72 seconds
Started Aug 03 05:35:00 PM PDT 24
Finished Aug 03 05:40:41 PM PDT 24
Peak memory 201520 kb
Host smart-7184c131-be59-4824-abdd-63f964626ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67620100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.67620100
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2203607578
Short name T612
Test name
Test status
Simulation time 160628662158 ps
CPU time 109.01 seconds
Started Aug 03 05:33:24 PM PDT 24
Finished Aug 03 05:35:13 PM PDT 24
Peak memory 201456 kb
Host smart-475c5f7a-1c3d-44f7-8ff7-46a7fc89e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203607578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2203607578
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.454791192
Short name T577
Test name
Test status
Simulation time 164346048009 ps
CPU time 169.77 seconds
Started Aug 03 05:33:24 PM PDT 24
Finished Aug 03 05:36:13 PM PDT 24
Peak memory 201440 kb
Host smart-e140fb8d-4186-4a2f-b8c8-db7b55b1e634
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=454791192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.454791192
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3950957349
Short name T299
Test name
Test status
Simulation time 325162258239 ps
CPU time 195.76 seconds
Started Aug 03 05:33:24 PM PDT 24
Finished Aug 03 05:36:40 PM PDT 24
Peak memory 201360 kb
Host smart-04b0876a-7d14-4999-b604-d89ab09fffd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950957349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3950957349
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2839321390
Short name T753
Test name
Test status
Simulation time 487125227295 ps
CPU time 579.49 seconds
Started Aug 03 05:33:22 PM PDT 24
Finished Aug 03 05:43:01 PM PDT 24
Peak memory 201440 kb
Host smart-c093e914-9dc1-4208-8a64-97bc2f540d71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839321390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2839321390
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.964493732
Short name T266
Test name
Test status
Simulation time 508590026209 ps
CPU time 585.32 seconds
Started Aug 03 05:33:21 PM PDT 24
Finished Aug 03 05:43:07 PM PDT 24
Peak memory 201492 kb
Host smart-de67733c-e781-4d34-8968-9d470683ab0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964493732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.964493732
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2435887373
Short name T446
Test name
Test status
Simulation time 396906886326 ps
CPU time 214.07 seconds
Started Aug 03 05:33:23 PM PDT 24
Finished Aug 03 05:36:57 PM PDT 24
Peak memory 201380 kb
Host smart-af979f94-febf-41c3-9960-191657f69572
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435887373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2435887373
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.395595544
Short name T51
Test name
Test status
Simulation time 107147592919 ps
CPU time 441.38 seconds
Started Aug 03 05:35:01 PM PDT 24
Finished Aug 03 05:42:22 PM PDT 24
Peak memory 201820 kb
Host smart-9ba3d09a-36a7-4fce-a82d-974e7a3d1bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395595544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.395595544
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3080698987
Short name T593
Test name
Test status
Simulation time 24366784713 ps
CPU time 14.17 seconds
Started Aug 03 05:35:00 PM PDT 24
Finished Aug 03 05:35:15 PM PDT 24
Peak memory 201364 kb
Host smart-bc368ab8-24d6-4802-96b3-bb755c1639c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080698987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3080698987
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.328443935
Short name T414
Test name
Test status
Simulation time 4855782157 ps
CPU time 2.77 seconds
Started Aug 03 05:34:59 PM PDT 24
Finished Aug 03 05:35:02 PM PDT 24
Peak memory 201328 kb
Host smart-fa1c50ae-a182-4f92-afed-cc4526949bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328443935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.328443935
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2451778079
Short name T383
Test name
Test status
Simulation time 6076357687 ps
CPU time 2.98 seconds
Started Aug 03 05:33:22 PM PDT 24
Finished Aug 03 05:33:25 PM PDT 24
Peak memory 201384 kb
Host smart-1ceb8adb-e2ef-428d-be00-db6842d725dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451778079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2451778079
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1496413715
Short name T213
Test name
Test status
Simulation time 180319855077 ps
CPU time 219.36 seconds
Started Aug 03 05:35:00 PM PDT 24
Finished Aug 03 05:38:40 PM PDT 24
Peak memory 201436 kb
Host smart-a31464a0-19b5-4d34-a14b-b7a3a3467880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496413715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1496413715
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.4137076091
Short name T169
Test name
Test status
Simulation time 75534238554 ps
CPU time 38.11 seconds
Started Aug 03 05:33:55 PM PDT 24
Finished Aug 03 05:34:33 PM PDT 24
Peak memory 201660 kb
Host smart-3041bfa4-1de2-4995-a9e3-9cb71538980c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137076091 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.4137076091
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3922677039
Short name T457
Test name
Test status
Simulation time 411250678 ps
CPU time 1.57 seconds
Started Aug 03 05:34:02 PM PDT 24
Finished Aug 03 05:34:03 PM PDT 24
Peak memory 201208 kb
Host smart-16ec5e3a-0e18-4e5a-a9ae-7720c0fb0b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922677039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3922677039
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3632265918
Short name T329
Test name
Test status
Simulation time 502571249850 ps
CPU time 558.85 seconds
Started Aug 03 05:33:32 PM PDT 24
Finished Aug 03 05:42:51 PM PDT 24
Peak memory 201452 kb
Host smart-d94f94c6-0462-4b65-abc2-da575cc69b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632265918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3632265918
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3131076407
Short name T223
Test name
Test status
Simulation time 159391620733 ps
CPU time 294.12 seconds
Started Aug 03 05:33:32 PM PDT 24
Finished Aug 03 05:38:26 PM PDT 24
Peak memory 201456 kb
Host smart-04ce70fd-8c6d-4976-aa04-1f1527afadb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131076407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3131076407
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1860999497
Short name T538
Test name
Test status
Simulation time 490804840714 ps
CPU time 568.63 seconds
Started Aug 03 05:33:35 PM PDT 24
Finished Aug 03 05:43:03 PM PDT 24
Peak memory 201440 kb
Host smart-67025c3d-dc13-41a8-a7de-18bd603d12a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860999497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1860999497
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.552511486
Short name T622
Test name
Test status
Simulation time 327198649780 ps
CPU time 670.47 seconds
Started Aug 03 05:33:33 PM PDT 24
Finished Aug 03 05:44:43 PM PDT 24
Peak memory 201444 kb
Host smart-53950e09-e56d-41f3-98ce-4259bcfce034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552511486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.552511486
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2596430765
Short name T164
Test name
Test status
Simulation time 163245053927 ps
CPU time 46.87 seconds
Started Aug 03 05:33:32 PM PDT 24
Finished Aug 03 05:34:19 PM PDT 24
Peak memory 201464 kb
Host smart-d4841037-2333-417e-b1a9-ec3dfb1ee317
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596430765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2596430765
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2093736791
Short name T139
Test name
Test status
Simulation time 188724214629 ps
CPU time 417.82 seconds
Started Aug 03 05:33:33 PM PDT 24
Finished Aug 03 05:40:31 PM PDT 24
Peak memory 201416 kb
Host smart-9e54db1a-08ab-4e25-81cd-b41322f29f6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093736791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2093736791
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1348112213
Short name T800
Test name
Test status
Simulation time 386101975987 ps
CPU time 929.36 seconds
Started Aug 03 05:33:32 PM PDT 24
Finished Aug 03 05:49:02 PM PDT 24
Peak memory 201468 kb
Host smart-51121281-3805-4f05-97f4-117ef5cb5099
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348112213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1348112213
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1885269776
Short name T399
Test name
Test status
Simulation time 143654087423 ps
CPU time 758.73 seconds
Started Aug 03 05:33:33 PM PDT 24
Finished Aug 03 05:46:12 PM PDT 24
Peak memory 201844 kb
Host smart-0cb2d67f-5d1d-466f-8ab0-67640e89aef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885269776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1885269776
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1217774816
Short name T500
Test name
Test status
Simulation time 29615260336 ps
CPU time 67.26 seconds
Started Aug 03 05:33:32 PM PDT 24
Finished Aug 03 05:34:40 PM PDT 24
Peak memory 201336 kb
Host smart-7ecab3dd-1554-4e2c-8cce-48de3c8b2a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217774816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1217774816
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3990663643
Short name T454
Test name
Test status
Simulation time 5199278186 ps
CPU time 7.38 seconds
Started Aug 03 05:33:33 PM PDT 24
Finished Aug 03 05:33:41 PM PDT 24
Peak memory 201288 kb
Host smart-26899f5d-c919-4b68-84c2-1008827203b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990663643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3990663643
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1816187273
Short name T405
Test name
Test status
Simulation time 5863112399 ps
CPU time 3.17 seconds
Started Aug 03 05:33:31 PM PDT 24
Finished Aug 03 05:33:35 PM PDT 24
Peak memory 201360 kb
Host smart-d6f93379-3aaf-4fd9-83ff-b46f00fa5b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816187273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1816187273
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.883176523
Short name T272
Test name
Test status
Simulation time 513417148932 ps
CPU time 1120.68 seconds
Started Aug 03 05:33:34 PM PDT 24
Finished Aug 03 05:52:15 PM PDT 24
Peak memory 201448 kb
Host smart-d1b80698-aaa6-4c6e-8611-6763d0ec530f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883176523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
883176523
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2648900045
Short name T707
Test name
Test status
Simulation time 48551767067 ps
CPU time 108.3 seconds
Started Aug 03 05:33:35 PM PDT 24
Finished Aug 03 05:35:23 PM PDT 24
Peak memory 210152 kb
Host smart-d68ce98b-02ef-4b67-9ae5-1b3ded3c31d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648900045 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2648900045
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1236623469
Short name T572
Test name
Test status
Simulation time 498157770 ps
CPU time 1.05 seconds
Started Aug 03 05:33:55 PM PDT 24
Finished Aug 03 05:33:56 PM PDT 24
Peak memory 201232 kb
Host smart-0fe8af12-d1c9-44e2-86c6-02850fc80305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236623469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1236623469
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.4140632892
Short name T50
Test name
Test status
Simulation time 236955088451 ps
CPU time 43.32 seconds
Started Aug 03 05:33:43 PM PDT 24
Finished Aug 03 05:34:26 PM PDT 24
Peak memory 201444 kb
Host smart-28d3301a-559e-4abf-a8c1-736aa4cea8b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140632892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.4140632892
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2208041628
Short name T522
Test name
Test status
Simulation time 164689849011 ps
CPU time 202.37 seconds
Started Aug 03 05:33:46 PM PDT 24
Finished Aug 03 05:37:09 PM PDT 24
Peak memory 201460 kb
Host smart-75fd30f2-d59a-43b4-a183-8dd1b20f29e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208041628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2208041628
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1909939940
Short name T240
Test name
Test status
Simulation time 500064711003 ps
CPU time 567.8 seconds
Started Aug 03 05:35:02 PM PDT 24
Finished Aug 03 05:44:30 PM PDT 24
Peak memory 201520 kb
Host smart-9669ea5e-0e67-4044-b0f9-14e68a04983b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909939940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1909939940
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.877824572
Short name T504
Test name
Test status
Simulation time 326768064089 ps
CPU time 89.88 seconds
Started Aug 03 05:35:08 PM PDT 24
Finished Aug 03 05:36:38 PM PDT 24
Peak memory 201396 kb
Host smart-f172b1cb-82d8-4c53-9f4a-3755aaa0df21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=877824572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.877824572
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.4192264724
Short name T15
Test name
Test status
Simulation time 500507700762 ps
CPU time 539.19 seconds
Started Aug 03 05:34:44 PM PDT 24
Finished Aug 03 05:43:43 PM PDT 24
Peak memory 201420 kb
Host smart-7f79401d-231e-4da6-a997-dfc5b4dd1d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192264724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.4192264724
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2997550216
Short name T472
Test name
Test status
Simulation time 495269523365 ps
CPU time 1119.07 seconds
Started Aug 03 05:35:02 PM PDT 24
Finished Aug 03 05:53:41 PM PDT 24
Peak memory 201436 kb
Host smart-1fe0f52e-ba6e-475f-84f1-54d1c42c84dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997550216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2997550216
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2757117493
Short name T737
Test name
Test status
Simulation time 377364100568 ps
CPU time 227.16 seconds
Started Aug 03 05:35:05 PM PDT 24
Finished Aug 03 05:38:53 PM PDT 24
Peak memory 201596 kb
Host smart-e3ea4a2b-7e3f-4743-a6a0-575d9b153db5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757117493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2757117493
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3933402576
Short name T32
Test name
Test status
Simulation time 404936412390 ps
CPU time 865.69 seconds
Started Aug 03 05:33:45 PM PDT 24
Finished Aug 03 05:48:11 PM PDT 24
Peak memory 201380 kb
Host smart-83707715-1708-4992-998a-daa5c983233e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933402576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3933402576
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3182302790
Short name T701
Test name
Test status
Simulation time 74495898147 ps
CPU time 269.53 seconds
Started Aug 03 05:33:52 PM PDT 24
Finished Aug 03 05:38:22 PM PDT 24
Peak memory 201788 kb
Host smart-81bc9f2a-7278-4296-9995-29e4dbc6f749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182302790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3182302790
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2944595611
Short name T382
Test name
Test status
Simulation time 29718897338 ps
CPU time 25.23 seconds
Started Aug 03 05:33:50 PM PDT 24
Finished Aug 03 05:34:15 PM PDT 24
Peak memory 201384 kb
Host smart-23b4e4b9-1f25-4910-9e5e-3d2046a83f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944595611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2944595611
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3661685486
Short name T570
Test name
Test status
Simulation time 3575219445 ps
CPU time 8.61 seconds
Started Aug 03 05:33:45 PM PDT 24
Finished Aug 03 05:33:54 PM PDT 24
Peak memory 201324 kb
Host smart-76ac878e-a503-4bae-a9d7-1e11a5e46067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661685486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3661685486
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1265544860
Short name T738
Test name
Test status
Simulation time 5808359524 ps
CPU time 14.13 seconds
Started Aug 03 05:35:02 PM PDT 24
Finished Aug 03 05:35:16 PM PDT 24
Peak memory 201292 kb
Host smart-21509bb7-c067-4e1a-9249-d5ab2ec83502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265544860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1265544860
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1776465146
Short name T625
Test name
Test status
Simulation time 246805291016 ps
CPU time 264.82 seconds
Started Aug 03 05:33:50 PM PDT 24
Finished Aug 03 05:38:15 PM PDT 24
Peak memory 201464 kb
Host smart-f5a17256-628e-479e-8edc-014ba39d6bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776465146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1776465146
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3244681695
Short name T17
Test name
Test status
Simulation time 46648874989 ps
CPU time 108.26 seconds
Started Aug 03 05:33:51 PM PDT 24
Finished Aug 03 05:35:39 PM PDT 24
Peak memory 210136 kb
Host smart-c1313503-7001-41d9-84d6-9acf4f1b32ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244681695 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3244681695
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3063033486
Short name T574
Test name
Test status
Simulation time 397735893 ps
CPU time 0.69 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:28:40 PM PDT 24
Peak memory 201196 kb
Host smart-c7ef79b1-0ddb-4e9d-a8e2-7e8afca7b092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063033486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3063033486
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2860176742
Short name T743
Test name
Test status
Simulation time 165267337205 ps
CPU time 345.12 seconds
Started Aug 03 05:28:41 PM PDT 24
Finished Aug 03 05:34:27 PM PDT 24
Peak memory 201492 kb
Host smart-d2274920-5d2f-4dc5-9248-50246e6f03ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860176742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2860176742
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1071682654
Short name T286
Test name
Test status
Simulation time 161396206827 ps
CPU time 94.23 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:30:14 PM PDT 24
Peak memory 201392 kb
Host smart-916c2154-cf9b-4c6b-a925-845c1596eb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071682654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1071682654
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2912016574
Short name T437
Test name
Test status
Simulation time 162413082040 ps
CPU time 47.98 seconds
Started Aug 03 05:28:41 PM PDT 24
Finished Aug 03 05:29:29 PM PDT 24
Peak memory 200796 kb
Host smart-7c1f302b-c448-48ba-af0e-2dd2a3e58f5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912016574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2912016574
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.4118849926
Short name T702
Test name
Test status
Simulation time 165762264704 ps
CPU time 41.1 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:29:20 PM PDT 24
Peak memory 201376 kb
Host smart-bbc7e656-fd80-478e-bc8a-5b16feb55df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118849926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.4118849926
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1359104916
Short name T517
Test name
Test status
Simulation time 159363770341 ps
CPU time 347.42 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:34:27 PM PDT 24
Peak memory 201384 kb
Host smart-7acdf17a-8b4a-453e-b680-f67d4cb3a189
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359104916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1359104916
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3654787184
Short name T248
Test name
Test status
Simulation time 619707905468 ps
CPU time 1464.42 seconds
Started Aug 03 05:28:42 PM PDT 24
Finished Aug 03 05:53:06 PM PDT 24
Peak memory 200864 kb
Host smart-bcdfbd29-e0a1-4b22-898e-e4750ee00b1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654787184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3654787184
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2923025417
Short name T466
Test name
Test status
Simulation time 381781642063 ps
CPU time 124.35 seconds
Started Aug 03 05:28:49 PM PDT 24
Finished Aug 03 05:30:53 PM PDT 24
Peak memory 201460 kb
Host smart-e6405343-de50-4b1e-80f1-8cc07792cb58
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923025417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2923025417
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3536382755
Short name T696
Test name
Test status
Simulation time 95782279295 ps
CPU time 289.74 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:33:30 PM PDT 24
Peak memory 201916 kb
Host smart-13fb42d2-35e9-4d35-a532-e1252ff87c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536382755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3536382755
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1472934632
Short name T788
Test name
Test status
Simulation time 40629977040 ps
CPU time 17.58 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:28:58 PM PDT 24
Peak memory 201388 kb
Host smart-df2e5ce5-01ec-41e4-9b5f-1cac0d58287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472934632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1472934632
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.180856854
Short name T402
Test name
Test status
Simulation time 4294658680 ps
CPU time 8.94 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:28:48 PM PDT 24
Peak memory 201336 kb
Host smart-83e19fd2-3d7a-422c-b162-02f2f87a9509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180856854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.180856854
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.4265981737
Short name T636
Test name
Test status
Simulation time 6008568953 ps
CPU time 6.58 seconds
Started Aug 03 05:28:41 PM PDT 24
Finished Aug 03 05:28:48 PM PDT 24
Peak memory 200720 kb
Host smart-851b7163-5b60-4723-9362-a1079a7b6b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265981737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4265981737
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.163482681
Short name T138
Test name
Test status
Simulation time 492540190809 ps
CPU time 1095.56 seconds
Started Aug 03 05:28:44 PM PDT 24
Finished Aug 03 05:47:00 PM PDT 24
Peak memory 201404 kb
Host smart-2e6af31c-3127-4b58-9dbc-1f566f3bfd5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163482681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.163482681
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3003036592
Short name T56
Test name
Test status
Simulation time 213147687617 ps
CPU time 422.55 seconds
Started Aug 03 05:28:41 PM PDT 24
Finished Aug 03 05:35:44 PM PDT 24
Peak memory 210168 kb
Host smart-f3b1d63b-fc02-4636-924e-78498aab29c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003036592 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3003036592
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1180186130
Short name T108
Test name
Test status
Simulation time 465512772 ps
CPU time 0.87 seconds
Started Aug 03 05:28:44 PM PDT 24
Finished Aug 03 05:28:45 PM PDT 24
Peak memory 201248 kb
Host smart-5047d89a-c4fc-4a67-915d-1a22d81b9f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180186130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1180186130
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2331055910
Short name T784
Test name
Test status
Simulation time 394242846530 ps
CPU time 848.51 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:42:49 PM PDT 24
Peak memory 201508 kb
Host smart-dce1cbb1-02b2-43b2-90e1-9d4aeb42269e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331055910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2331055910
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1178598849
Short name T685
Test name
Test status
Simulation time 512945900195 ps
CPU time 578.47 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:38:18 PM PDT 24
Peak memory 201456 kb
Host smart-d88528b2-eca3-4208-90b1-872cf85f300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178598849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1178598849
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1835479021
Short name T212
Test name
Test status
Simulation time 498816828579 ps
CPU time 1155.92 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:47:55 PM PDT 24
Peak memory 201440 kb
Host smart-a63e540c-95fb-4ab7-9419-c01d98568674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835479021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1835479021
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1130933545
Short name T281
Test name
Test status
Simulation time 167350988849 ps
CPU time 204.33 seconds
Started Aug 03 05:28:40 PM PDT 24
Finished Aug 03 05:32:05 PM PDT 24
Peak memory 201404 kb
Host smart-9e0a317d-51ca-463a-b7c2-55293ffa18db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130933545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1130933545
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1980807448
Short name T606
Test name
Test status
Simulation time 160304067376 ps
CPU time 386.29 seconds
Started Aug 03 05:28:41 PM PDT 24
Finished Aug 03 05:35:08 PM PDT 24
Peak memory 201424 kb
Host smart-5ef848ae-8043-4320-8b61-4bb5a3e0a9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980807448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1980807448
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2980319453
Short name T693
Test name
Test status
Simulation time 164570797233 ps
CPU time 62.54 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:29:42 PM PDT 24
Peak memory 201428 kb
Host smart-a7674582-aa2e-40ab-a106-9124bd9f598e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980319453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2980319453
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.884681563
Short name T541
Test name
Test status
Simulation time 381647624516 ps
CPU time 930.26 seconds
Started Aug 03 05:28:38 PM PDT 24
Finished Aug 03 05:44:09 PM PDT 24
Peak memory 201488 kb
Host smart-fa34d063-da5c-444f-b0a5-87f0da7e538f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884681563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.884681563
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2576317289
Short name T483
Test name
Test status
Simulation time 396081327594 ps
CPU time 820.64 seconds
Started Aug 03 05:28:38 PM PDT 24
Finished Aug 03 05:42:19 PM PDT 24
Peak memory 201384 kb
Host smart-e98a3b2c-4b31-44d5-981a-9ed7e7ee7ad5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576317289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2576317289
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1569764463
Short name T349
Test name
Test status
Simulation time 132017634051 ps
CPU time 419.14 seconds
Started Aug 03 05:28:51 PM PDT 24
Finished Aug 03 05:35:50 PM PDT 24
Peak memory 201924 kb
Host smart-9937ec84-e3f6-4afe-b9aa-410d89e272a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569764463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1569764463
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1975744021
Short name T628
Test name
Test status
Simulation time 31699214413 ps
CPU time 6.16 seconds
Started Aug 03 05:28:43 PM PDT 24
Finished Aug 03 05:28:50 PM PDT 24
Peak memory 201364 kb
Host smart-cf8c9235-eeb0-4952-9722-7c95108ed2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975744021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1975744021
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1282464871
Short name T536
Test name
Test status
Simulation time 4109393495 ps
CPU time 1.73 seconds
Started Aug 03 05:28:44 PM PDT 24
Finished Aug 03 05:28:46 PM PDT 24
Peak memory 201360 kb
Host smart-40e3d23b-f594-4b45-b183-a5d98a4d0f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282464871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1282464871
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3549100888
Short name T369
Test name
Test status
Simulation time 5536168541 ps
CPU time 4.13 seconds
Started Aug 03 05:28:39 PM PDT 24
Finished Aug 03 05:28:43 PM PDT 24
Peak memory 201384 kb
Host smart-c6ae7506-c3e1-4931-96d1-6283e9f70c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549100888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3549100888
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3983545388
Short name T669
Test name
Test status
Simulation time 143088922905 ps
CPU time 574.26 seconds
Started Aug 03 05:28:45 PM PDT 24
Finished Aug 03 05:38:20 PM PDT 24
Peak memory 210020 kb
Host smart-cb7d84a8-0e45-4a68-87cb-92017925cd05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983545388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3983545388
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.818561413
Short name T48
Test name
Test status
Simulation time 64167678049 ps
CPU time 148.13 seconds
Started Aug 03 05:28:44 PM PDT 24
Finished Aug 03 05:31:13 PM PDT 24
Peak memory 209752 kb
Host smart-4123acc0-b40c-4d00-b988-6d652ddd2325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818561413 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.818561413
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.147980794
Short name T717
Test name
Test status
Simulation time 449188385 ps
CPU time 0.86 seconds
Started Aug 03 05:28:46 PM PDT 24
Finished Aug 03 05:28:47 PM PDT 24
Peak memory 201248 kb
Host smart-504ed32f-6303-4812-b93e-9777e82ef9c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147980794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.147980794
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.521078908
Short name T795
Test name
Test status
Simulation time 501304728657 ps
CPU time 315.3 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:34:05 PM PDT 24
Peak memory 201520 kb
Host smart-08d50560-3685-41de-904e-eaef8c2d8513
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521078908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.521078908
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.4036095615
Short name T241
Test name
Test status
Simulation time 547488674910 ps
CPU time 672.23 seconds
Started Aug 03 05:28:43 PM PDT 24
Finished Aug 03 05:39:56 PM PDT 24
Peak memory 201428 kb
Host smart-6bad2dd8-c51f-4647-830f-7d8dd0441f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036095615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.4036095615
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3915709771
Short name T274
Test name
Test status
Simulation time 162063774126 ps
CPU time 349.75 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:34:40 PM PDT 24
Peak memory 201468 kb
Host smart-bd5a6926-7564-4b2d-bb3a-7ea9113ae59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915709771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3915709771
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.161831033
Short name T417
Test name
Test status
Simulation time 492725678049 ps
CPU time 607.09 seconds
Started Aug 03 05:28:47 PM PDT 24
Finished Aug 03 05:38:54 PM PDT 24
Peak memory 201396 kb
Host smart-699fb0df-dc45-436b-b9f2-44828675d3c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=161831033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.161831033
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3277252802
Short name T315
Test name
Test status
Simulation time 482788957489 ps
CPU time 293.83 seconds
Started Aug 03 05:28:45 PM PDT 24
Finished Aug 03 05:33:39 PM PDT 24
Peak memory 201444 kb
Host smart-58053576-91f8-4254-809c-365b89ea96a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277252802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3277252802
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1259017820
Short name T514
Test name
Test status
Simulation time 323104990395 ps
CPU time 667.57 seconds
Started Aug 03 05:28:44 PM PDT 24
Finished Aug 03 05:39:52 PM PDT 24
Peak memory 201448 kb
Host smart-16f55e28-6faa-450a-ba7d-1b3f6d38257c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259017820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1259017820
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2246364917
Short name T180
Test name
Test status
Simulation time 534937381168 ps
CPU time 287.04 seconds
Started Aug 03 05:28:44 PM PDT 24
Finished Aug 03 05:33:32 PM PDT 24
Peak memory 201472 kb
Host smart-93b7dfbd-9b48-4def-9c17-aa71f2cd1c08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246364917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2246364917
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4252553328
Short name T9
Test name
Test status
Simulation time 587206251165 ps
CPU time 416.87 seconds
Started Aug 03 05:28:46 PM PDT 24
Finished Aug 03 05:35:43 PM PDT 24
Peak memory 201448 kb
Host smart-cd7a8f1d-d954-474c-864d-292ff71ad4c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252553328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4252553328
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.4042492061
Short name T745
Test name
Test status
Simulation time 73585064521 ps
CPU time 423.79 seconds
Started Aug 03 05:28:47 PM PDT 24
Finished Aug 03 05:35:51 PM PDT 24
Peak memory 201832 kb
Host smart-e2bc0b29-0bcf-4e32-81bb-c9bf97824aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042492061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.4042492061
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1489555031
Short name T742
Test name
Test status
Simulation time 27055219722 ps
CPU time 30.76 seconds
Started Aug 03 05:28:47 PM PDT 24
Finished Aug 03 05:29:18 PM PDT 24
Peak memory 201340 kb
Host smart-a82237d5-fbaf-49d3-8930-28c1a94b89eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489555031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1489555031
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2286353389
Short name T136
Test name
Test status
Simulation time 4462238187 ps
CPU time 3.29 seconds
Started Aug 03 05:28:47 PM PDT 24
Finished Aug 03 05:28:50 PM PDT 24
Peak memory 201340 kb
Host smart-a91c369c-7587-4c5d-8612-35e9eabba1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286353389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2286353389
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2577453413
Short name T731
Test name
Test status
Simulation time 5859372191 ps
CPU time 3.69 seconds
Started Aug 03 05:28:44 PM PDT 24
Finished Aug 03 05:28:48 PM PDT 24
Peak memory 201356 kb
Host smart-200c5e57-b6d8-4ecf-8f17-3b29345bffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577453413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2577453413
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2886686034
Short name T346
Test name
Test status
Simulation time 33637827736 ps
CPU time 102.44 seconds
Started Aug 03 05:28:48 PM PDT 24
Finished Aug 03 05:30:31 PM PDT 24
Peak memory 217764 kb
Host smart-95acb3ec-2201-41f4-8b2d-b867b72e3e1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886686034 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2886686034
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2277305441
Short name T376
Test name
Test status
Simulation time 345602983 ps
CPU time 0.75 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:28:51 PM PDT 24
Peak memory 201216 kb
Host smart-b5af409d-1317-4f65-8ce1-e6e3893fb5ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277305441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2277305441
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.518405932
Short name T153
Test name
Test status
Simulation time 365168375230 ps
CPU time 643.39 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:39:33 PM PDT 24
Peak memory 201444 kb
Host smart-cab191e7-c20b-4746-afdd-e176659fd559
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518405932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.518405932
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1249155029
Short name T587
Test name
Test status
Simulation time 481151197004 ps
CPU time 1075.12 seconds
Started Aug 03 05:28:51 PM PDT 24
Finished Aug 03 05:46:47 PM PDT 24
Peak memory 201472 kb
Host smart-17c68e27-0514-40c3-9298-e2e4c80d764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249155029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1249155029
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.237620395
Short name T290
Test name
Test status
Simulation time 170330779962 ps
CPU time 379.91 seconds
Started Aug 03 05:28:53 PM PDT 24
Finished Aug 03 05:35:13 PM PDT 24
Peak memory 201468 kb
Host smart-a971aefd-8ca7-434f-9a9d-db620fce4e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237620395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.237620395
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.443650513
Short name T436
Test name
Test status
Simulation time 499891441763 ps
CPU time 1233.8 seconds
Started Aug 03 05:28:51 PM PDT 24
Finished Aug 03 05:49:25 PM PDT 24
Peak memory 201424 kb
Host smart-c8e0a5b6-e68b-41ae-a6e2-f5efa0e705bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=443650513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.443650513
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.277601203
Short name T267
Test name
Test status
Simulation time 327592134632 ps
CPU time 500.49 seconds
Started Aug 03 05:28:47 PM PDT 24
Finished Aug 03 05:37:08 PM PDT 24
Peak memory 201452 kb
Host smart-8072a643-ab5a-43ee-bfae-5c7a49037ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277601203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.277601203
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3062574090
Short name T406
Test name
Test status
Simulation time 163248725193 ps
CPU time 116.43 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:30:47 PM PDT 24
Peak memory 201472 kb
Host smart-bea57df4-491d-4765-983a-48cac705a948
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062574090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3062574090
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1073010783
Short name T146
Test name
Test status
Simulation time 407524378610 ps
CPU time 405.75 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:35:36 PM PDT 24
Peak memory 201508 kb
Host smart-7eef7e91-251f-49a5-bb7a-3a42460dc3c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073010783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1073010783
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.960730365
Short name T106
Test name
Test status
Simulation time 100253836551 ps
CPU time 500.79 seconds
Started Aug 03 05:28:53 PM PDT 24
Finished Aug 03 05:37:14 PM PDT 24
Peak memory 201876 kb
Host smart-cae3ccd9-0777-4b4f-aabd-d43922c53ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960730365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.960730365
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.599711987
Short name T481
Test name
Test status
Simulation time 35004384228 ps
CPU time 39.62 seconds
Started Aug 03 05:28:53 PM PDT 24
Finished Aug 03 05:29:32 PM PDT 24
Peak memory 201304 kb
Host smart-cf0b6480-9d88-44f9-af1f-853a2a5bf527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599711987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.599711987
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3485659966
Short name T381
Test name
Test status
Simulation time 3462374674 ps
CPU time 4.62 seconds
Started Aug 03 05:28:51 PM PDT 24
Finished Aug 03 05:28:55 PM PDT 24
Peak memory 201336 kb
Host smart-2662b8c1-99cd-4791-829b-2e9f9942e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485659966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3485659966
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2442991496
Short name T740
Test name
Test status
Simulation time 5802790015 ps
CPU time 7.91 seconds
Started Aug 03 05:28:48 PM PDT 24
Finished Aug 03 05:28:56 PM PDT 24
Peak memory 201372 kb
Host smart-b8ad3265-1fd6-4523-93fe-a10a404c685e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442991496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2442991496
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1673370180
Short name T515
Test name
Test status
Simulation time 45683675400 ps
CPU time 125.23 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:30:56 PM PDT 24
Peak memory 210108 kb
Host smart-7e327e7b-06d3-48ea-90a1-b517a57ca664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673370180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1673370180
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.283739097
Short name T573
Test name
Test status
Simulation time 516829649 ps
CPU time 1.27 seconds
Started Aug 03 05:29:04 PM PDT 24
Finished Aug 03 05:29:05 PM PDT 24
Peak memory 201224 kb
Host smart-d01351ae-a0d6-4aa4-9203-7abd0952d49c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283739097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.283739097
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.596465149
Short name T239
Test name
Test status
Simulation time 368426536026 ps
CPU time 196.69 seconds
Started Aug 03 05:28:52 PM PDT 24
Finished Aug 03 05:32:09 PM PDT 24
Peak memory 201448 kb
Host smart-e5c67410-d3e3-4928-af54-45a3e1f51bb6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596465149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.596465149
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.156742842
Short name T501
Test name
Test status
Simulation time 337747811421 ps
CPU time 748.58 seconds
Started Aug 03 05:28:51 PM PDT 24
Finished Aug 03 05:41:19 PM PDT 24
Peak memory 201444 kb
Host smart-5c90d3af-2cf4-41f1-b49f-aaa4eaaca257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156742842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.156742842
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2877400950
Short name T317
Test name
Test status
Simulation time 165332671432 ps
CPU time 55.77 seconds
Started Aug 03 05:28:49 PM PDT 24
Finished Aug 03 05:29:44 PM PDT 24
Peak memory 201468 kb
Host smart-171e0a27-c0d4-4021-a6a9-9c48256fee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877400950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2877400950
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.349489998
Short name T479
Test name
Test status
Simulation time 161385223186 ps
CPU time 73.69 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:30:04 PM PDT 24
Peak memory 201388 kb
Host smart-177ee539-31f8-4b68-a092-935231533da8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=349489998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.349489998
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.509076563
Short name T170
Test name
Test status
Simulation time 493257646821 ps
CPU time 279.71 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:33:30 PM PDT 24
Peak memory 201492 kb
Host smart-542a3321-bbca-43d3-9c3e-e93e10f93438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509076563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.509076563
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.215625890
Short name T665
Test name
Test status
Simulation time 168973430866 ps
CPU time 370.56 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:35:01 PM PDT 24
Peak memory 201432 kb
Host smart-a97ad557-4134-4976-b9f4-5c38ec2ed5f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=215625890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.215625890
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1540037945
Short name T264
Test name
Test status
Simulation time 390907523689 ps
CPU time 836.6 seconds
Started Aug 03 05:28:53 PM PDT 24
Finished Aug 03 05:42:50 PM PDT 24
Peak memory 201436 kb
Host smart-69618bf5-195a-430a-aa45-e1bc6f765241
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540037945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1540037945
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4214196981
Short name T557
Test name
Test status
Simulation time 199858020172 ps
CPU time 471.7 seconds
Started Aug 03 05:28:52 PM PDT 24
Finished Aug 03 05:36:44 PM PDT 24
Peak memory 201460 kb
Host smart-ea1396ce-074b-4543-ba5a-1d81e575981c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214196981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.4214196981
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.609034625
Short name T409
Test name
Test status
Simulation time 96135484478 ps
CPU time 501.82 seconds
Started Aug 03 05:28:53 PM PDT 24
Finished Aug 03 05:37:15 PM PDT 24
Peak memory 201920 kb
Host smart-ccedfdc1-9db5-45cc-9e08-a0096f5f70ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609034625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.609034625
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1813225845
Short name T444
Test name
Test status
Simulation time 28089440600 ps
CPU time 60.43 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:29:51 PM PDT 24
Peak memory 201272 kb
Host smart-be6f4424-4a4b-45d4-b6af-2d2fada5502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813225845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1813225845
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2339837404
Short name T712
Test name
Test status
Simulation time 4888192351 ps
CPU time 6.74 seconds
Started Aug 03 05:28:53 PM PDT 24
Finished Aug 03 05:29:00 PM PDT 24
Peak memory 201304 kb
Host smart-71ff3d13-1e5e-47d3-9a54-ef806840bfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339837404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2339837404
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.4168403569
Short name T721
Test name
Test status
Simulation time 6015587533 ps
CPU time 14.84 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:29:04 PM PDT 24
Peak memory 201364 kb
Host smart-2555e43c-afbc-45fb-9fce-8b2389a56de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168403569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.4168403569
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4116244530
Short name T516
Test name
Test status
Simulation time 118728699078 ps
CPU time 331.5 seconds
Started Aug 03 05:29:05 PM PDT 24
Finished Aug 03 05:34:37 PM PDT 24
Peak memory 210004 kb
Host smart-8876b0ed-7472-4db2-a18b-d8651ee7d67b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116244530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4116244530
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.581619045
Short name T781
Test name
Test status
Simulation time 237795307050 ps
CPU time 156.26 seconds
Started Aug 03 05:28:50 PM PDT 24
Finished Aug 03 05:31:27 PM PDT 24
Peak memory 210164 kb
Host smart-8314fe18-fe78-44e6-8424-544b6c41f16a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581619045 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.581619045
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest