Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6433	1			T4	5		T8	26		T50	44
testmodes[AdcCtrlTestmodeNormal]	5319	1			T1	1		T4	5		T7	1
testmodes[AdcCtrlTestmodeLowpower]	5336	1			T2	2		T3	1		T5	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3461	1			T4	1		T8	20		T50	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1634	1			T4	3		T8	5		T50	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1224	1			T50	11		T45	12		T33	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1661	1			T4	4		T8	6		T50	9
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2016	1			T4	1		T8	8		T9	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1309	1			T8	1		T50	14		T32	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1203	1			T50	15		T45	12		T33	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1318	1			T8	1		T10	1		T50	10
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2565	1			T2	1		T6	2		T47	1