Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21672

1

T1

1

T2

15

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

4304

1

T2

28

T3

20

T6

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19553

1

T4

10

T6

18

T8

55

auto[1]

6423

1

T1

1

T2

43

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T195	19		T196	8		-	-
values[0]	61	1			T197	34		T198	10		T153	7
values[1]	855	1			T38	1		T43	8		T59	8
values[2]	3022	1			T1	1		T5	13		T6	19
values[3]	727	1			T2	28		T11	5		T39	4
values[4]	748	1			T6	10		T8	3		T32	5
values[5]	791	1			T8	15		T47	2		T136	22
values[6]	853	1			T10	5		T11	1		T48	13
values[7]	749	1			T2	15		T3	20		T48	22
values[8]	879	1			T8	1		T10	25		T199	19
values[9]	1137	1			T47	16		T48	14		T42	14
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1119	1			T43	8		T46	1		T59	9
values[1]	2989	1			T1	1		T5	13		T6	19
values[2]	736	1			T2	28		T40	4		T46	1
values[3]	763	1			T6	10		T8	3		T32	5
values[4]	813	1			T8	15		T47	2		T39	9
values[5]	809	1			T10	5		T11	1		T48	35
values[6]	736	1			T2	15		T8	1		T38	1
values[7]	868	1			T3	20		T47	16		T199	19
values[8]	862	1			T10	25		T48	14		T42	14
values[9]	152	1			T15	14		T200	13		T195	19
minimum	16129	1			T4	10		T8	39		T50	110

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T59	1		T136	8		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T43	8		T46	1		T59	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T1	1		T5	13		T6	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	11		T11	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	2		T46	1		T199	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	14		T152	9		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	10		T8	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T32	4		T60	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T136	10		T98	1		T201	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T8	11		T47	2		T39	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	2		T46	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T11	1		T48	19		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	8		T38	1		T96	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	1		T132	1		T97	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T137	1		T202	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T3	11		T47	16		T199	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	12		T48	4		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T42	10		T130	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T203	8		T204	6		T205	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T15	4		T200	13		T195	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15991	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T136	10		T25	8		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T59	4		T134	9		T25	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T7	10		T60	8		T135	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	4		T202	1		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T40	2		T36	4		T206	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	14		T152	11		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	2		T133	14		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T32	1		T152	13		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T136	12		T16	3		T208	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	4		T44	11		T209	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	3		T177	12		T178	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T48	16		T40	13		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	7		T210	21		T211	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T97	18		T12	8		T24	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T137	4		T202	1		T212	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	9		T152	10		T197	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T10	13		T48	10		T136	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T42	4		T13	1		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T204	8		T205	2		T213	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T15	10		T195	8		T20	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T195	11		T196	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T197	20		T198	10		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T214	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T38	1		T136	8		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T43	8		T59	4		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T1	1		T5	13		T6	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	11		T46	1		T28	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T40	2		T199	15		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	14		T11	1		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	10		T8	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T32	4		T152	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	10		T98	1		T30	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T8	11		T47	2		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	2		T46	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T11	1		T48	7		T39	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	8		T38	1		T210	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	11		T48	12		T97	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	12		T137	1		T96	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T8	1		T199	19		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T48	4		T136	11		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T47	16		T42	10		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T195	8		T196	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T197	14		T153	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T136	10		T28	1		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T59	4		T134	9		T25	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1136	1			T7	10		T60	8		T99	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T28	1		T30	3		T202	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	2		T135	14		T36	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	14		T11	4		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	2		T133	14		T33	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T32	1		T152	13		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	12		T30	3		T84	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	4		T209	8		T207	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T10	3		T215	7		T216	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T48	6		T40	13		T44	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	7		T210	10		T177	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	9		T48	10		T97	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	13		T137	4		T210	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T152	10		T207	8		T177	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T48	10		T136	3		T173	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T42	4		T197	11		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T59	1		T136	11		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T43	1		T46	1		T59	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T1	1		T5	1		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	1		T11	5		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T40	3		T46	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	15		T152	12		T173	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	1		T8	3		T133	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T32	5		T60	1		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T136	13		T98	1		T201	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	5		T47	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	4		T46	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T11	1		T48	18		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	8		T38	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	1		T132	1		T97	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	5		T202	2		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	10		T47	1		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	14		T48	11		T136	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T42	5		T130	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T203	1		T204	9		T205	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T15	13		T200	1		T195	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T136	7		T197	18		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T43	7		T59	3		T28	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T5	12		T6	7		T49	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T6	10		T39	3		T139	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T40	1		T199	14		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	13		T152	8		T217	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	9		T33	2		T30	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T131	14		T14	2		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T136	9		T201	5		T218	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T8	10		T47	1		T39	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	1		T177	9		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T48	17		T39	8		T40	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	7		T96	18		T210	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T97	11		T12	2		T24	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T212	10		T219	10		T220	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	10		T47	15		T199	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	11		T48	3		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T42	9		T201	14		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T203	7		T204	5		T205	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T15	1		T200	12		T195	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T195	9		T196	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T197	16		T198	1		T153	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T214	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	1		T136	11		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T43	1		T59	5		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T1	1		T5	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T46	1		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T40	3		T199	1		T135	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	15		T11	5		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	1		T8	3		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T32	5		T152	14		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	13		T98	1		T30	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T8	5		T47	1		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T10	4		T46	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T11	1		T48	7		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	8		T38	1		T210	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	10		T48	11		T97	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	14		T137	5		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T8	1		T199	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T48	11		T136	4		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T47	1		T42	5		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T195	10		T196	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T197	18		T198	9		T221	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	7		T13	1		T222	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T43	7		T59	3		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T5	12		T6	7		T49	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	10		T28	8		T30	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	1		T199	14		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	13		T39	3		T152	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	9		T33	2		T223	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	1		T212	10		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T136	9		T30	5		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T8	10		T47	1		T131	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T10	1		T201	5		T224	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T48	6		T39	16		T40	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	7		T210	4		T177	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	10		T48	11		T97	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	11		T96	18		T210	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T199	18		T152	13		T177	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T48	3		T136	10		T164	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T47	15		T42	9		T197	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22218

1

T1

1

T2

28

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3758

1

T2

15

T6

18

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19489

1

T2

43

T3

20

T4

10

auto[1]

6487

1

T1

1

T5

13

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T38	1		T218	9		T225	6
values[0]	47	1			T134	10		T98	1		T15	14
values[1]	769	1			T46	1		T133	15		T130	1
values[2]	631	1			T8	3		T10	5		T11	1
values[3]	868	1			T11	5		T48	13		T32	5
values[4]	827	1			T2	28		T6	10		T38	1
values[5]	3091	1			T1	1		T5	13		T7	11
values[6]	683	1			T10	25		T39	4		T46	1
values[7]	850	1			T2	15		T3	20		T47	2
values[8]	782	1			T6	11		T39	9		T40	21
values[9]	1285	1			T6	8		T8	16		T40	4
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1167	1			T11	1		T38	1		T43	8
values[1]	554	1			T8	3		T10	5		T48	35
values[2]	784	1			T2	28		T6	10		T11	5
values[3]	3080	1			T1	1		T5	13		T7	11
values[4]	828	1			T47	16		T48	14		T39	4
values[5]	729	1			T2	15		T3	20		T10	25
values[6]	795	1			T47	2		T39	9		T44	24
values[7]	707	1			T6	19		T40	25		T42	14
values[8]	1039	1			T8	16		T136	18		T130	1
values[9]	166	1			T38	1		T129	10		T143	2
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T43	8		T134	1		T152	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T11	1		T38	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T46	1		T137	1		T28	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	1		T10	2		T48	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	14		T11	1		T32	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	10		T39	9		T152	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T1	1		T5	13		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T38	1		T135	11		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	4		T39	4		T96	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T47	16		T139	14		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	11		T10	12		T59	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	8		T46	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T44	13		T98	1		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T47	2		T39	9		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	11		T42	10		T199	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	8		T40	10		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T8	11		T136	8		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	1		T60	1		T33	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T226	1		T227	14		T228	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T38	1		T129	10		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T134	9		T152	11		T24	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T133	14		T139	25		T15	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T137	4		T28	1		T206	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T8	2		T10	3		T48	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	14		T11	4		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T152	10		T97	18		T29	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T7	10		T136	12		T209	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T135	14		T144	17		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	10		T14	1		T211	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T139	12		T230	9		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	9		T10	13		T59	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	7		T60	8		T219	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T44	11		T25	9		T212	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T138	10		T207	8		T140	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T42	4		T30	3		T197	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	15		T136	3		T210	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T8	4		T136	10		T152	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	3		T197	14		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T227	12		T228	15		T232	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T143	1		T192	7		T233	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T218	9		T225	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T38	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T134	1		T234	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T98	1		T15	4		T168	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T152	9		T131	16		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T46	1		T133	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T43	8		T24	14		T28	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	1		T10	2		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T11	1		T32	4		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	7		T39	9		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	14		T59	1		T199	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	10		T38	1		T135	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T1	1		T5	13		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T47	16		T155	2		T235	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	12		T39	4		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T46	1		T132	1		T60	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	11		T44	13		T59	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T2	8		T47	2		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	11		T42	10		T199	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T39	9		T40	8		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	410	1			T8	11		T136	8		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T6	8		T8	1		T40	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T134	9		T234	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T15	10		T168	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T152	11		T25	8		T30	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T133	14		T139	13		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T24	4		T28	1		T173	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T8	2		T10	3		T48	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	4		T32	1		T137	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	6		T152	10		T97	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	14		T136	12		T209	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T135	14		T236	10		T144	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T7	10		T48	10		T99	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T237	10		T230	9		T149	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	13		T25	13		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T60	8		T139	12		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	9		T44	11		T59	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	7		T207	8		T140	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T42	4		T25	9		T30	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T40	13		T136	3		T210	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T8	4		T136	10		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	2		T33	3		T197	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2