Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22161

1

T1

1

T2

15

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

3815

1

T2

28

T3

20

T6

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19616

1

T2

28

T4

10

T6

11

auto[1]

6360

1

T1

1

T2

15

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	346	1			T48	22		T197	21		T138	13
values[0]	20	1			T98	1		T255	1		T306	1
values[1]	647	1			T11	1		T32	5		T39	4
values[2]	929	1			T46	1		T59	1		T152	38
values[3]	776	1			T8	3		T11	5		T38	1
values[4]	672	1			T6	10		T10	5		T38	1
values[5]	3043	1			T1	1		T3	20		T5	13
values[6]	834	1			T6	11		T8	1		T46	1
values[7]	698	1			T2	15		T6	8		T43	8
values[8]	644	1			T8	15		T48	27		T39	9
values[9]	1240	1			T2	28		T10	25		T47	18
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	668	1			T11	1		T32	5		T42	14
values[1]	895	1			T59	1		T152	14		T96	15
values[2]	772	1			T6	10		T8	3		T11	5
values[3]	2984	1			T1	1		T3	20		T5	13
values[4]	779	1			T199	19		T136	18		T135	25
values[5]	788	1			T2	15		T6	11		T8	1
values[6]	820	1			T6	8		T48	14		T43	8
values[7]	587	1			T8	15		T10	25		T48	13
values[8]	1156	1			T2	28		T47	18		T48	22
values[9]	190	1			T136	14		T138	13		T14	4
minimum	16337	1			T4	10		T8	39		T50	110

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T136	10		T130	1		T152	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	1		T32	4		T42	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T59	1		T152	1		T96	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T15	4		T36	4		T248	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	1		T11	1		T59	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	10		T38	1		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T1	1		T5	13		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	11		T38	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T199	19		T135	11		T131	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T136	8		T137	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	8		T6	11		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T46	1		T98	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T6	8		T48	4		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T43	8		T44	13		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	11		T60	6		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	12		T48	7		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T47	16		T129	10		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T2	14		T47	2		T48	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T136	11		T138	3		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T243	15		T307	1		T301	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16044	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T197	8		T283	1		T166	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T136	12		T152	10		T34	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T32	1		T42	4		T152	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T152	13		T12	8		T29	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T15	10		T36	4		T248	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	2		T11	4		T28	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T40	2		T133	14		T173	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T7	10		T10	3		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	9		T59	4		T212	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T135	14		T209	8		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T136	10		T137	4		T202	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	7		T25	8		T202	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T153	9		T212	10		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T48	10		T24	4		T25	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T44	11		T30	3		T84	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	4		T60	8		T25	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	13		T48	6		T164	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T134	9		T197	11		T138	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T2	14		T48	10		T40	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T136	3		T138	10		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T243	10		T301	7		T278	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T59	1		T60	3		T29	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T215	12		T308	7		T253	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T197	10		T138	3		T263	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T48	12		T223	13		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T98	1		T306	1		T309	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T255	1		T310	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	4		T136	10		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T32	4		T42	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T59	1		T152	15		T96	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T46	1		T15	4		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T8	1		T11	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T38	1		T40	2		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	2		T59	1		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	10		T38	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T1	1		T5	13		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	11		T59	4		T136	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	11		T8	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T46	1		T98	1		T198	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T2	8		T6	8		T199	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T43	8		T44	13		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	11		T48	4		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	7		T39	9		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T47	16		T129	10		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	411	1			T2	14		T10	12		T47	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T197	11		T138	10		T263	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T48	10		T223	10		T241	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T309	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T136	12		T34	1		T30	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T32	1		T42	4		T152	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T152	23		T12	8		T28	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	10		T177	4		T36	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	2		T11	4		T28	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T40	2		T173	12		T138	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	3		T33	3		T223	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T133	14		T212	11		T35	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T7	10		T135	14		T99	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	9		T59	4		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T209	8		T25	8		T202	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	1		T212	10		T143	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	7		T24	4		T25	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T44	11		T153	9		T84	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	4		T48	10		T25	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T48	6		T30	3		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T136	3		T60	8		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T2	14		T10	13		T40	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T136	13		T130	1		T152	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	1		T32	5		T42	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T59	1		T152	14		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	13		T36	6		T248	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	3		T11	5		T59	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T38	1		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T1	1		T5	1		T7	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	10		T38	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T199	1		T135	15		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	11		T137	5		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	8		T6	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T46	1		T98	1		T153	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	1		T48	11		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T43	1		T44	12		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	5		T60	9		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	14		T48	7		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T47	1		T129	1		T134	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	431	1			T2	15		T47	1		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T136	4		T138	11		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T243	11		T307	1		T301	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16170	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T197	1		T283	1		T166	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	9		T152	13		T34	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T42	9		T152	8		T143	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T96	14		T12	2		T210	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	1		T36	2		T248	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T96	18		T28	8		T178	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	9		T40	1		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T5	12		T10	1		T49	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	10		T59	3		T212	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T199	18		T135	10		T131	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T136	7		T217	14		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	7		T6	10		T199	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T212	10		T235	10		T143	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	7		T48	3		T96	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	7		T44	12		T30	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	10		T60	5		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T10	11		T48	6		T39	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T47	15		T129	9		T197	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T2	13		T47	1		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T136	10		T138	2		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T243	14		T301	5		T278	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T39	3		T311	12		T312	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T197	7		T308	10		T313	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T197	12		T138	11		T263	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T48	11		T223	11		T241	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T98	1		T306	1		T309	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T255	1		T310	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T39	1		T136	13		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T32	5		T42	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T59	1		T152	25		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T46	1		T15	13		T177	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	3		T11	5		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T38	1		T40	3		T173	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	4		T59	1		T33	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	1		T38	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1473	1			T1	1		T5	1		T7	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	10		T59	5		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	1		T8	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T46	1		T98	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	8		T6	1		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T43	1		T44	12		T153	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	5		T48	11		T25	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T48	7		T39	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T47	1		T129	1		T136	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T2	15		T10	14		T47	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T197	9		T138	2		T263	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T48	11		T223	12		T243	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T309	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	3		T136	9		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T42	9		T152	8		T197	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T152	13		T96	14		T12	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	1		T36	2		T248	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T96	18		T28	8		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	1		T138	13		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T10	1		T33	2		T222	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	9		T212	10		T218	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T5	12		T49	7		T39	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	10		T59	3		T136	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	10		T209	8		T139	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T198	9		T14	1		T212	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	7		T6	7		T199	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T43	7		T44	12		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	10		T48	3		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T48	6		T39	8		T30	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T47	15		T129	9		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T2	13		T10	11		T47	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12