Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22058

1

T1

1

T2

15

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

3918

1

T2

28

T3

20

T6

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19527

1

T4

10

T6

11

T8

39

auto[1]

6449

1

T1

1

T2

43

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	45	1			T48	22		T307	1		T293	13
values[0]	63	1			T42	14		T98	1		T255	1
values[1]	573	1			T11	1		T32	5		T39	4
values[2]	907	1			T46	1		T59	1		T152	38
values[3]	852	1			T6	10		T8	3		T11	5
values[4]	695	1			T10	5		T38	1		T46	1
values[5]	3020	1			T1	1		T3	20		T5	13
values[6]	782	1			T6	11		T8	1		T132	1
values[7]	723	1			T2	15		T43	8		T44	24
values[8]	637	1			T6	8		T8	15		T48	27
values[9]	1552	1			T2	28		T10	25		T47	18
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	895	1			T11	1		T32	5		T39	4
values[1]	832	1			T59	1		T152	14		T96	15
values[2]	832	1			T8	3		T11	5		T38	1
values[3]	3004	1			T1	1		T3	20		T5	13
values[4]	757	1			T46	1		T199	19		T136	18
values[5]	735	1			T2	15		T6	11		T8	1
values[6]	847	1			T6	8		T48	14		T43	8
values[7]	653	1			T8	15		T10	25		T48	13
values[8]	1033	1			T2	28		T47	18		T48	22
values[9]	252	1			T136	14		T13	4		T14	4
minimum	16136	1			T4	10		T8	39		T50	110

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T39	4		T130	1		T152	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	1		T32	4		T42	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T59	1		T152	1		T96	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	5		T139	14		T15	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T38	1		T59	1		T60	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	1		T11	1		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T1	1		T5	13		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	11		T6	10		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T199	19		T135	11		T131	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T46	1		T136	8		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	8		T8	1		T199	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T6	11		T98	1		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T6	8		T48	4		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	8		T44	13		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	11		T60	6		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	12		T48	7		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T47	16		T38	1		T129	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T2	14		T47	2		T48	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T136	11		T13	3		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T243	15		T215	1		T301	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T197	8		T310	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T152	10		T34	1		T30	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T32	1		T42	4		T136	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T152	13		T28	1		T29	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	8		T139	12		T15	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T28	1		T138	11		T178	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	2		T11	4		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T7	10		T10	3		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	9		T59	4		T173	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T135	14		T137	4		T209	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T136	10		T140	4		T14	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	7		T25	8		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T202	1		T212	10		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	10		T24	4		T25	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T44	11		T30	3		T207	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	4		T60	8		T25	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	13		T48	6		T164	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T134	9		T177	22		T241	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T2	14		T48	10		T40	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T136	3		T13	1		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T243	10		T215	15		T301	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T293	13		T232	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T48	12		T307	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T306	1		T309	7		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T42	10		T98	1		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T39	4		T130	1		T34	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	1		T32	4		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T59	1		T152	15		T96	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T46	1		T12	5		T139	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T38	1		T60	1		T96	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	10		T8	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	2		T59	1		T135	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	1		T46	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T1	1		T5	13		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	11		T46	1		T59	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	1		T132	1		T209	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T6	11		T98	1		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	8		T199	15		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T43	8		T44	13		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	8		T8	11		T48	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	7		T39	9		T30	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T47	16		T38	1		T129	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	450	1			T2	14		T10	12		T47	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T232	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T48	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T309	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T42	4		T143	11		T314	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	1		T30	3		T197	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T32	1		T136	12		T152	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T152	23		T28	1		T210	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	8		T139	12		T15	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T28	1		T29	12		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	2		T11	4		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	3		T135	14		T33	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T133	14		T35	2		T144	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1123	1			T7	10		T137	4		T99	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	9		T59	4		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T209	8		T25	8		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T202	1		T207	8		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	7		T24	4		T25	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	11		T153	9		T84	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	4		T48	10		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T48	6		T30	3		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T136	3		T60	8		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	473	1			T2	14		T10	13		T40	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T39	1		T130	1		T152	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	1		T32	5		T42	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T59	1		T152	14		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	11		T139	13		T15	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	1		T59	1		T60	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	3		T11	5		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T1	1		T5	1		T7	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	10		T6	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T199	1		T135	15		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	1		T136	11		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	8		T8	1		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	1		T98	1		T202	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T6	1		T48	11		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T43	1		T44	12		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	5		T60	9		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	14		T48	7		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T47	1		T38	1		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T2	15		T47	1		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T136	4		T13	3		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T243	11		T215	16		T301	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T197	1		T310	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T39	3		T152	13		T34	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T42	9		T136	9		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T96	14		T210	3		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	2		T139	13		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T96	18		T28	8		T138	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T40	1		T13	1		T217	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T5	12		T10	1		T49	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	10		T6	9		T59	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T199	18		T135	10		T131	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T136	7		T217	14		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T2	7		T199	14		T139	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	10		T212	10		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	7		T48	3		T96	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T43	7		T44	12		T30	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	10		T60	5		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	11		T48	6		T39	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T47	15		T129	9		T201	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	13		T47	1		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T136	10		T13	1		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T243	14		T301	5		T278	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T197	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T293	1		T232	7		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T48	11		T307	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T306	1		T309	9		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T42	5		T98	1		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	1		T130	1		T34	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	1		T32	5		T136	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T59	1		T152	25		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T46	1		T12	11		T139	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T38	1		T60	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	1		T8	3		T11	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T10	4		T59	1		T135	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T38	1		T46	1		T133	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1480	1			T1	1		T5	1		T7	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	10		T46	1		T59	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	1		T132	1		T209	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	1		T98	1		T202	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	8		T199	1		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T43	1		T44	12		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T8	5		T48	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T48	7		T39	1		T30	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T47	1		T38	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	552	1			T2	15		T10	14		T47	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T293	12		T232	2		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T48	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T309	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T42	9		T143	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T39	3		T34	1		T30	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T136	9		T152	8		T197	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T152	13		T96	14		T210	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	2		T139	13		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T96	18		T28	8		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	9		T40	1		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	1		T135	10		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T218	8		T144	9		T229	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T5	12		T49	7		T39	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T3	10		T59	3		T136	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T209	8		T139	16		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	10		T198	9		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	7		T199	14		T96	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T43	7		T44	12		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	7		T8	10		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	6		T39	8		T30	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T47	15		T129	9		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T2	13		T10	11		T47	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12