Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22095

1

T1

1

T2

28

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

3881

1

T2

15

T3

20

T6

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19302

1

T2

43

T3

20

T4

10

auto[1]

6674

1

T1

1

T5

13

T6

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	516	1			T50	2		T45	1		T130	1
values[0]	40	1			T275	10		T233	30		-	-
values[1]	821	1			T10	5		T47	16		T39	13
values[2]	3178	1			T1	1		T5	13		T6	11
values[3]	692	1			T48	22		T199	19		T136	18
values[4]	875	1			T2	15		T8	4		T32	5
values[5]	579	1			T3	20		T47	2		T134	10
values[6]	687	1			T11	1		T46	1		T133	15
values[7]	931	1			T38	2		T39	9		T40	21
values[8]	820	1			T6	18		T48	14		T42	14
values[9]	1110	1			T2	28		T48	13		T43	8
minimum	15727	1			T4	10		T8	39		T50	108

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	695	1			T47	16		T39	13		T197	26
values[1]	3250	1			T1	1		T5	13		T6	11
values[2]	656	1			T46	1		T59	1		T199	19
values[3]	854	1			T2	15		T8	4		T32	5
values[4]	622	1			T3	20		T47	2		T134	10
values[5]	773	1			T11	1		T38	1		T46	1
values[6]	824	1			T48	14		T38	1		T39	9
values[7]	786	1			T6	18		T42	14		T59	1
values[8]	959	1			T2	28		T48	13		T129	10
values[9]	124	1			T43	8		T167	20		T226	1
minimum	16433	1			T4	10		T8	39		T10	5

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T39	4		T197	12		T201	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T47	16		T39	9		T138	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T1	1		T5	13		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T6	11		T8	11		T10	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	1		T59	1		T199	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T98	1		T34	7		T25	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	1		T131	1		T96	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	8		T8	1		T32	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T47	2		T137	1		T209	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	11		T134	1		T135	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T38	1		T46	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	1		T29	2		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T48	4		T39	9		T40	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T38	1		T199	15		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T6	18		T97	12		T30	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T42	10		T59	1		T96	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T2	14		T59	4		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T48	7		T129	10		T210	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T167	10		T226	1		T315	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T43	8		T278	13		T205	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16128	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T10	2		T46	1		T30	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T197	14		T250	4		T180	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T138	11		T36	1		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T7	10		T48	10		T40	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	4		T10	13		T11	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T177	4		T248	7		T229	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T34	1		T25	21		T13	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	2		T138	13		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	7		T32	1		T44	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T137	4		T209	8		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	9		T134	9		T135	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T133	14		T30	3		T210	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	12		T173	12		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	10		T40	13		T12	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T28	1		T197	11		T207	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T97	18		T30	3		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	4		T263	1		T270	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	14		T59	4		T202	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T48	6		T210	10		T139	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T167	10		T316	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T278	10		T205	1		T317	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T59	1		T60	3		T152	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T10	3		T241	8		T275	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	445	1			T50	2		T45	1		T130	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T178	1		T142	1		T318	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T233	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T39	4		T152	1		T28	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	2		T47	16		T39	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T1	1		T5	13		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T6	11		T8	11		T10	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T48	12		T199	19		T136	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T98	1		T34	7		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	1		T59	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	8		T8	1		T32	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T47	2		T96	15		T143	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	11		T134	1		T135	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T46	1		T133	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	1		T29	2		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T38	1		T39	9		T40	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T38	1		T199	15		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	18		T48	4		T97	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T42	10		T59	1		T96	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T2	14		T59	4		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T48	7		T43	8		T129	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15589	1			T4	10		T8	39		T50	108
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T167	10		T234	11		T93	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T318	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T233	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T275	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	13		T28	1		T250	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	3		T138	11		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T7	10		T40	2		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	4		T10	13		T11	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T48	10		T136	10		T60	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T34	1		T25	13		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	2		T138	13		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T2	7		T32	1		T44	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T143	9		T211	12		T269	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	9		T134	9		T135	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T133	14		T137	4		T209	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	12		T173	12		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T40	13		T12	8		T173	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T207	11		T177	12		T248	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	10		T97	18		T30	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T42	4		T28	1		T197	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	14		T59	4		T202	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T48	6		T210	10		T139	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T39	1		T197	15		T201	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	1		T39	1		T138	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T1	1		T5	1		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	1		T8	5		T10	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T46	1		T59	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T98	1		T34	7		T25	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T8	3		T131	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T2	8		T8	1		T32	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	1		T137	5		T209	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	10		T134	10		T135	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T38	1		T46	1		T133	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	1		T29	14		T173	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T48	11		T39	1		T40	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	1		T199	1		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	2		T97	19		T30	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T42	5		T59	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T2	15		T59	5		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T48	7		T129	1		T210	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T167	11		T226	1		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T43	1		T278	11		T205	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16258	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T10	4		T46	1		T30	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	3		T197	11		T201	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T47	15		T39	8		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T5	12		T48	11		T49	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	10		T8	10		T10	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T199	18		T248	6		T229	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T34	1		T13	1		T217	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T96	14		T138	11		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	7		T44	12		T152	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T47	1		T209	8		T143	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T3	10		T135	10		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T30	5		T210	3		T201	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	1		T198	14		T178	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	3		T39	8		T40	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T199	14		T197	9		T222	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	16		T97	11		T30	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T42	9		T96	8		T218	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	13		T59	3		T96	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	6		T129	9		T210	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T167	9		T315	12		T319	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T43	7		T278	12		T205	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T28	8		T245	7		T299	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T10	1		T320	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	460	1			T50	2		T45	1		T130	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T178	1		T142	1		T318	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T233	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T275	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	1		T152	14		T28	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	4		T47	1		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T1	1		T5	1		T7	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	1		T8	5		T10	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	11		T199	1		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T98	1		T34	7		T25	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	3		T59	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T2	8		T8	1		T32	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	1		T96	1		T143	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	10		T134	10		T135	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T46	1		T133	15		T137	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	1		T29	14		T173	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T38	1		T39	1		T40	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T38	1		T199	1		T207	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	2		T48	11		T97	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T42	5		T59	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T2	15		T59	5		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T48	7		T43	1		T129	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15727	1			T4	10		T8	39		T50	108
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T167	9		T315	12		T93	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T321	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T233	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T39	3		T28	8		T202	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	1		T47	15		T39	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T5	12		T49	7		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	10		T8	10		T10	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	11		T199	18		T136	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	1		T217	14		T229	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T138	11		T14	1		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	7		T44	12		T152	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T47	1		T96	14		T143	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	10		T135	10		T131	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T209	8		T30	5		T210	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T13	1		T178	10		T308	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	8		T40	7		T12	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T199	14		T222	5		T198	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	16		T48	3		T97	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T42	9		T96	8		T197	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	13		T59	3		T96	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T48	6		T43	7		T129	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12