Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22217

1

T1

1

T2

28

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3759

1

T2

15

T6

18

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19502

1

T2

43

T3

20

T4

10

auto[1]

6474

1

T1

1

T5

13

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	421	1			T8	15		T38	1		T152	14
values[0]	50	1			T98	1		T173	13		T15	14
values[1]	734	1			T11	1		T46	1		T133	15
values[2]	686	1			T8	3		T10	5		T48	22
values[3]	813	1			T6	10		T11	5		T48	13
values[4]	792	1			T2	28		T38	1		T59	1
values[5]	3176	1			T1	1		T5	13		T7	11
values[6]	677	1			T2	15		T3	20		T10	25
values[7]	882	1			T47	2		T39	9		T44	24
values[8]	741	1			T6	19		T40	25		T42	14
values[9]	877	1			T8	1		T129	10		T136	18
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	913	1			T11	1		T43	8		T46	1
values[1]	565	1			T8	3		T10	5		T48	35
values[2]	810	1			T2	28		T6	10		T11	5
values[3]	3063	1			T1	1		T5	13		T7	11
values[4]	833	1			T47	16		T48	14		T39	4
values[5]	696	1			T2	15		T3	20		T10	25
values[6]	876	1			T47	2		T39	9		T40	21
values[7]	666	1			T6	19		T40	4		T199	15
values[8]	1098	1			T8	16		T38	1		T129	10
values[9]	103	1			T143	2		T192	13		T227	26
minimum	16353	1			T4	10		T8	39		T50	110

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T43	8		T152	9		T131	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	1		T46	1		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T46	1		T137	1		T28	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	1		T10	2		T48	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	14		T11	1		T32	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	10		T38	1		T39	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T1	1		T5	13		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T135	11		T144	13		T229	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T48	4		T39	4		T96	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T47	16		T139	14		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	11		T10	12		T59	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	8		T46	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T42	10		T44	13		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T47	2		T39	9		T40	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	11		T199	15		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	8		T40	2		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T8	11		T136	8		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T8	1		T38	1		T129	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T227	14		T232	16		T225	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T143	1		T192	6		T293	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16045	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T98	1		T144	10		T143	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T152	11		T24	4		T210	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T133	14		T139	25		T15	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T137	4		T28	1		T173	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T8	2		T10	3		T48	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	14		T11	4		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T152	10		T97	18		T29	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T7	10		T136	12		T209	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T135	14		T144	17		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	10		T14	1		T211	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T139	12		T149	9		T308	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	9		T10	13		T59	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	7		T60	8		T219	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T42	4		T44	11		T25	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	13		T138	10		T207	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T30	3		T197	11		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	2		T136	3		T210	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T8	4		T136	10		T152	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T33	3		T197	14		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T227	12		T232	19		T322	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T143	1		T192	7		T323	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T59	1		T60	3		T134	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T144	10		T143	9		T176	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T8	11		T152	1		T153	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	1		T33	7		T197	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T173	1		T234	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T98	1		T15	4		T168	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T134	1		T152	9		T131	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T46	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T43	8		T24	14		T28	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	1		T10	2		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T11	1		T32	4		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	10		T48	7		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	14		T59	1		T199	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T38	1		T135	11		T198	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T1	1		T5	13		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T47	16		T165	1		T155	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	11		T10	12		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	8		T46	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T44	13		T59	4		T96	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T47	2		T39	9		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	11		T42	10		T199	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	8		T40	10		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T136	8		T130	1		T96	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T129	10		T60	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T8	4		T152	13		T153	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T33	3		T197	14		T270	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T173	12		T234	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T15	10		T168	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T134	9		T152	11		T25	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T133	14		T139	13		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T24	4		T28	1		T173	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	2		T10	3		T48	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	4		T32	1		T137	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	6		T152	10		T97	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	14		T136	12		T209	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T135	14		T236	10		T144	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T7	10		T48	10		T99	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T237	10		T230	9		T149	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	9		T10	13		T25	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	7		T60	8		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T44	11		T59	4		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T138	10		T207	8		T140	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T42	4		T25	9		T30	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	15		T136	3		T210	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T136	10		T34	1		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T143	1		T231	10		T324	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T43	1		T152	12		T131	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T11	1		T46	1		T133	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	1		T137	5		T28	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	3		T10	4		T48	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	15		T11	5		T32	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T38	1		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T1	1		T5	1		T7	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T135	15		T144	18		T229	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T48	11		T39	1		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T47	1		T139	13		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	10		T10	14		T59	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	8		T46	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T42	5		T44	12		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T47	1		T39	1		T40	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T199	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T40	3		T136	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T8	5		T136	11		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	1		T38	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T227	13		T232	23		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T143	2		T192	8		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16234	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T98	1		T144	11		T143	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T43	7		T152	8		T131	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T197	7		T201	5		T139	31
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	8		T217	15		T238	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T10	1		T48	17		T164	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	13		T13	1		T198	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	9		T39	8		T152	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T5	12		T49	7		T239	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T135	10		T144	12		T229	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	3		T39	3		T96	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T47	15		T139	13		T235	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	10		T10	11		T59	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	7		T60	5		T219	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T42	9		T44	12		T212	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T47	1		T39	8		T40	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	10		T199	14		T96	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T6	7		T40	1		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T8	10		T136	7		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T129	9		T33	2		T197	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T227	13		T232	12		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T192	5		T293	12		T323	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T30	3		T177	7		T272	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T144	9		T143	8		T168	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T8	5		T152	14		T153	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T38	1		T33	8		T197	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T173	13		T234	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T98	1		T15	13		T168	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T134	10		T152	12		T131	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	1		T46	1		T133	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T43	1		T24	5		T28	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	3		T10	4		T48	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	5		T32	5		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T48	7		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	15		T59	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T38	1		T135	15		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T1	1		T5	1		T7	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T47	1		T165	1		T155	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	10		T10	14		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	8		T46	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T44	12		T59	5		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T47	1		T39	1		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T42	5		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	1		T40	17		T136	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T136	11		T130	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	1		T129	1		T60	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T8	10		T218	8		T269	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T33	2		T197	11		T174	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T15	1		T168	1		T240	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T152	8		T131	14		T30	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T201	5		T139	16		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T43	7		T24	13		T28	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	1		T48	11		T197	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T198	14		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	9		T48	6		T39	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	13		T199	18		T136	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T135	10		T198	9		T236	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T5	12		T48	3		T49	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T47	15		T235	10		T145	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	10		T10	11		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	7		T60	5		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T44	12		T59	3		T96	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T47	1		T39	8		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	10		T42	9		T199	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	7		T40	8		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T136	7		T96	8		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	9		T201	14		T224	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12