Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22106

1

T1

1

T2

28

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3870

1

T2

15

T6

11

T8

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19598

1

T2

15

T3

20

T4

10

auto[1]

6378

1

T1

1

T2

28

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	280	1			T48	14		T59	1		T197	8
values[0]	40	1			T229	20		T282	20		-	-
values[1]	893	1			T2	28		T6	11		T46	1
values[2]	704	1			T3	20		T6	8		T8	15
values[3]	837	1			T6	10		T11	1		T39	9
values[4]	747	1			T8	3		T10	5		T11	5
values[5]	637	1			T46	1		T152	14		T25	9
values[6]	832	1			T48	13		T39	4		T43	8
values[7]	869	1			T131	15		T12	13		T173	13
values[8]	412	1			T136	18		T130	1		T30	1
values[9]	3598	1			T1	1		T2	15		T5	13
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	896	1			T6	19		T199	19		T136	36
values[1]	583	1			T3	20		T8	15		T48	22
values[2]	820	1			T6	10		T11	1		T39	9
values[3]	830	1			T8	3		T10	5		T11	5
values[4]	777	1			T46	1		T60	1		T152	38
values[5]	688	1			T48	13		T39	4		T43	8
values[6]	3106	1			T1	1		T5	13		T7	11
values[7]	505	1			T46	1		T136	18		T130	1
values[8]	1131	1			T2	15		T10	25		T38	1
values[9]	214	1			T8	1		T48	14		T59	1
minimum	16426	1			T2	28		T4	10		T8	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T6	8		T199	19		T136	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	11		T136	10		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	11		T32	4		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	11		T48	12		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	10		T39	9		T152	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T11	1		T40	8		T42	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	1		T47	18		T39	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T8	1		T10	2		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T46	1		T60	1		T97	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T152	15		T209	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T39	4		T43	8		T12	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T48	7		T199	15		T24	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T1	1		T5	13		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T131	15		T202	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T136	8		T130	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T46	1		T98	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T40	2		T59	1		T96	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	8		T10	12		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T48	4		T98	1		T197	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T8	1		T59	1		T34	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16085	1			T2	14		T4	10		T8	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T46	1		T137	1		T98	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T136	3		T25	13		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T136	12		T133	14		T25	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	9		T32	1		T139	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	4		T48	10		T209	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	11		T135	14		T30	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T40	13		T42	4		T44	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T11	4		T60	8		T153	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T8	2		T10	3		T29	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T97	18		T202	1		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T152	23		T25	8		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	8		T173	16		T211	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T48	6		T24	4		T173	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T7	10		T99	27		T26	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T202	1		T153	6		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T136	10		T28	1		T207	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T14	1		T263	1		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T40	2		T177	4		T248	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T2	7		T10	13		T59	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T48	10		T211	12		T243	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T34	1		T212	10		T278	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	14		T59	1		T60	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T137	4		T257	1		T325	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T48	4		T197	8		T177	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T59	1		T201	6		T15	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T229	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T282	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	14		T25	1		T28	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	11		T46	1		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	11		T6	8		T32	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	11		T48	12		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	10		T39	9		T152	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T11	1		T40	8		T42	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T47	18		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T8	1		T10	2		T129	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T46	1		T202	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T152	1		T25	1		T29	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T39	4		T43	8		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T48	7		T199	15		T152	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	5		T173	1		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T131	15		T201	15		T202	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T136	8		T130	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T30	1		T171	1		T145	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1787	1			T1	1		T5	13		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T2	8		T8	1		T10	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T48	10		T177	4		T144	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T212	10		T326	18		T327	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T229	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T282	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	14		T25	13		T28	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T136	12		T133	14		T137	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	9		T32	1		T136	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	4		T48	10		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T152	11		T30	3		T197	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T40	13		T42	4		T44	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	4		T60	8		T135	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	2		T10	3		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T202	1		T140	4		T272	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T152	13		T25	8		T29	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T97	18		T173	4		T139	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	6		T152	10		T24	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	8		T173	12		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T202	1		T153	6		T15	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T136	10		T215	15		T257	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T145	13		T147	10		T270	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T7	10		T40	2		T99	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	7		T10	13		T59	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T6	1		T199	1		T136	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	1		T136	13		T133	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	10		T32	5		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	5		T48	11		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T39	1		T152	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T11	1		T40	14		T42	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	5		T47	2		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T8	3		T10	4		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T46	1		T60	1		T97	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T152	25		T209	1		T25	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T39	1		T43	1		T12	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	7		T199	1		T24	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1418	1			T1	1		T5	1		T7	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T131	1		T202	2		T153	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T136	11		T130	1		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T46	1		T98	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T40	3		T59	1		T96	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T2	8		T10	14		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T48	11		T98	1		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T8	1		T59	1		T34	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16240	1			T2	15		T4	10		T8	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T46	1		T137	5		T98	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T6	7		T199	18		T136	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	10		T136	9		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	10		T217	15		T139	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	10		T48	11		T209	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T6	9		T39	8		T152	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T40	7		T42	9		T44	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T47	16		T39	8		T60	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T10	1		T197	9		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T97	11		T139	15		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T152	13		T139	16		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T39	3		T43	7		T12	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T48	6		T199	14		T24	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T5	12		T49	7		T239	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T131	14		T223	9		T235	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T136	7		T249	22		T180	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T14	1		T174	12		T147	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T40	1		T96	22		T248	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	7		T10	11		T59	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T48	3		T197	7		T224	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T34	1		T212	10		T284	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T2	13		T30	3		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T158	16		T221	7		T328	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T48	11		T197	1		T177	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T59	1		T201	1		T15	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T229	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T282	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T2	15		T25	14		T28	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	1		T46	1		T136	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	10		T6	1		T32	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	5		T48	11		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	1		T39	1		T152	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T11	1		T40	14		T42	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	5		T47	2		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T8	3		T10	4		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T46	1		T202	2		T140	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T152	14		T25	9		T29	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T39	1		T43	1		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T48	7		T199	1		T152	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	11		T173	13		T138	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T131	1		T201	1		T202	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T136	11		T130	1		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	1		T171	1		T145	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T1	1		T5	1		T7	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T2	8		T8	1		T10	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T48	3		T197	7		T144	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T201	5		T212	10		T327	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T229	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T282	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	13		T28	8		T30	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	10		T136	9		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	10		T6	7		T199	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	10		T48	11		T96	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	9		T39	8		T152	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T40	7		T42	9		T44	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T47	16		T39	8		T60	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	1		T129	9		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T272	16		T237	13		T243	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T197	9		T139	16		T219	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T39	3		T43	7		T97	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	6		T199	14		T152	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	2		T138	13		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T131	14		T201	14		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T136	7		T257	18		T221	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T145	10		T147	12		T245	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T5	12		T49	7		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	7		T10	11		T59	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12