Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T43	1		T134	10		T152	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T11	1		T38	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T46	1		T137	5		T28	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	3		T10	4		T48	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	15		T11	5		T32	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	1		T39	1		T152	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T1	1		T5	1		T7	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T38	1		T135	15		T144	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	11		T39	1		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T47	1		T139	13		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	10		T10	14		T59	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	8		T46	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T44	12		T98	1		T25	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T47	1		T39	1		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	1		T42	5		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	1		T40	17		T136	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T8	5		T136	11		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	1		T60	1		T33	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T226	1		T227	13		T228	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T38	1		T129	1		T143	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T43	7		T152	8		T131	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T197	7		T201	5		T139	31
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T28	8		T217	15		T238	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T10	1		T48	17		T164	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	13		T198	14		T224	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	9		T39	8		T152	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T5	12		T49	7		T239	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T135	10		T144	12		T229	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	3		T39	3		T96	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T47	15		T139	13		T235	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	10		T10	11		T59	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	7		T60	5		T174	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T44	12		T212	20		T223	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T47	1		T39	8		T138	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	10		T42	9		T199	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	7		T40	8		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T8	10		T136	7		T96	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T33	2		T197	11		T201	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T227	13		T228	16		T232	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T129	9		T192	5		T233	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T218	1		T225	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T38	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T134	10		T234	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T98	1		T15	13		T168	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T152	12		T131	2		T25	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T46	1		T133	15		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T43	1		T24	5		T28	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	3		T10	4		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T11	5		T32	5		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T48	7		T39	1		T152	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	15		T59	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	1		T38	1		T135	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T1	1		T5	1		T7	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T47	1		T155	2		T235	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T10	14		T39	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	1		T132	1		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	10		T44	12		T59	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	8		T47	1		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T42	5		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T39	1		T40	14		T136	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	423	1			T8	5		T136	11		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	1		T8	1		T40	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T218	8		T225	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T15	1		T168	1		T240	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T152	8		T131	14		T30	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T201	5		T139	16		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	7		T24	13		T28	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	1		T48	11		T197	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	1		T198	14		T177	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T48	6		T39	8		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	13		T199	18		T136	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	9		T135	10		T236	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T5	12		T48	3		T49	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T47	15		T235	10		T145	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T10	11		T39	3		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T60	5		T139	13		T174	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	10		T44	12		T59	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	7		T47	1		T178	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	10		T42	9		T199	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	8		T40	7		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T8	10		T136	7		T96	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	7		T40	1		T129	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12