Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19697

1

T2

28

T3

20

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

6279

1

T1

1

T2

15

T5

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19438

1

T4

10

T6

19

T8

43

auto[1]

6538

1

T1

1

T2

43

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	353	1			T48	13		T38	1		T209	1
values[0]	1	1			T166	1		-	-		-	-
values[1]	853	1			T11	1		T48	22		T39	4
values[2]	672	1			T6	8		T10	25		T11	5
values[3]	639	1			T48	14		T130	1		T152	44
values[4]	805	1			T2	43		T10	5		T44	24
values[5]	739	1			T3	20		T6	11		T42	14
values[6]	803	1			T8	3		T40	25		T43	8
values[7]	838	1			T8	15		T46	1		T129	10
values[8]	745	1			T6	10		T8	1		T47	2
values[9]	3401	1			T1	1		T5	13		T7	11
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	712	1			T11	1		T39	4		T131	1
values[1]	3078	1			T1	1		T5	13		T6	8
values[2]	567	1			T48	14		T130	1		T152	20
values[3]	764	1			T2	43		T3	20		T6	11
values[4]	808	1			T40	21		T42	14		T43	8
values[5]	743	1			T8	3		T40	4		T46	1
values[6]	840	1			T129	10		T136	18		T132	1
values[7]	770	1			T6	10		T8	16		T47	2
values[8]	1082	1			T48	13		T32	5		T38	1
values[9]	166	1			T46	1		T24	18		T25	14
minimum	16446	1			T4	10		T8	39		T48	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T11	1		T96	34		T34	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	4		T131	1		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	8		T10	12		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1576	1			T1	1		T5	13		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T130	1		T152	9		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T48	4		T173	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	14		T3	11		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	8		T6	11		T10	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T40	8		T43	8		T28	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T42	10		T134	1		T12	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T136	11		T137	1		T201	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T8	1		T40	2		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T129	10		T136	8		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T152	1		T96	9		T197	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	10		T8	12		T47	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T38	1		T39	9		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	7		T32	4		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T46	1		T209	10		T197	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T24	14		T25	1		T198	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T46	1		T219	10		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16063	1			T4	10		T8	39		T48	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T136	10		T15	1		T242	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	1		T243	14		T230	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T173	12		T138	10		T212	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	13		T11	4		T33	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1097	1			T7	10		T60	8		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T152	11		T173	4		T139	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	10		T173	4		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	14		T3	9		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	7		T10	3		T44	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T40	13		T28	1		T211	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T42	4		T134	9		T12	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T136	3		T137	4		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	2		T40	2		T97	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T136	10		T135	14		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T152	13		T197	11		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	4		T59	4		T202	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T25	9		T28	1		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	6		T32	1		T30	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T209	8		T197	14		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T24	4		T25	13		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T219	10		T241	8		T245	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T48	10		T59	1		T60	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T136	12		T237	10		T246	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T48	7		T38	1		T25	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T209	1		T36	2		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T166	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	1		T48	12		T96	34
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T39	4		T136	10		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T6	8		T10	12		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T47	16		T38	1		T59	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T130	1		T152	9		T30	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	4		T152	14		T197	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	14		T60	1		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	8		T10	2		T44	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	11		T130	1		T28	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	11		T42	10		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T40	8		T43	8		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	1		T40	2		T131	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T8	11		T129	10		T136	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T46	1		T60	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	10		T8	1		T47	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T39	9		T25	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T32	4		T199	19		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1738	1			T1	1		T5	13		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T48	6		T25	13		T139	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T36	1		T241	8		T245	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	10		T34	1		T29	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T136	12		T173	12		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	13		T11	4		T33	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T60	8		T143	12		T145	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T152	11		T30	3		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	10		T152	10		T173	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	14		T139	12		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	7		T10	3		T44	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	9		T28	1		T211	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T42	4		T134	9		T210	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	13		T136	3		T137	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	2		T40	2		T97	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	4		T136	10		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T152	13		T197	11		T247	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T59	4		T202	1		T177	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T25	9		T28	1		T139	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T32	1		T24	4		T30	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1296	1			T7	10		T209	8		T99	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T96	2		T34	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T39	1		T131	1		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	1		T10	14		T11	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1445	1			T1	1		T5	1		T7	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T130	1		T152	12		T173	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	11		T173	5		T140	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	15		T3	10		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	8		T6	1		T10	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T40	14		T43	1		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T42	5		T134	10		T12	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T136	4		T137	5		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	3		T40	3		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T129	1		T136	11		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T152	14		T96	1		T197	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	1		T8	6		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T38	1		T39	1		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T48	7		T32	5		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T46	1		T209	10		T197	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T24	5		T25	14		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T46	1		T219	11		T241	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16207	1			T4	10		T8	39		T48	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T136	13		T15	1		T242	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T96	32		T34	1		T174	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T39	3		T138	2		T212	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	7		T10	11		T39	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1228	1			T5	12		T47	15		T49	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T152	8		T139	15		T218	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T48	3		T248	9		T174	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	13		T3	10		T217	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	7		T6	10		T10	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	7		T43	7		T28	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T42	9		T12	2		T210	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T136	10		T201	14		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T40	1		T131	14		T97	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T129	9		T136	7		T135	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T96	8		T197	9		T139	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	9		T8	10		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T39	8		T14	1		T249	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T48	6		T30	3		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T209	8		T197	11		T138	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T24	13		T198	14		T235	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T219	9		T245	8		T203	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T48	11		T217	10		T250	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T136	9		T237	13		T251	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T48	7		T38	1		T25	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T209	1		T36	2		T241	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T166	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	1		T48	11		T96	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T39	1		T136	13		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	1		T10	14		T11	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T47	1		T38	1		T59	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T130	1		T152	12		T30	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T48	11		T152	11		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	15		T60	1		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T2	8		T10	4		T44	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	10		T130	1		T28	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T42	5		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	14		T43	1		T136	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	3		T40	3		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T8	5		T129	1		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T46	1		T60	1		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T8	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	1		T25	10		T28	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T32	5		T199	1		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1672	1			T1	1		T5	1		T7	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T48	6		T139	13		T198	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T36	1		T245	8		T192	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T48	11		T96	32		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T39	3		T136	9		T138	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	7		T10	11		T39	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T47	15		T60	5		T143	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T152	8		T30	5		T201	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T48	3		T152	13		T197	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	13		T139	15		T229	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	7		T10	1		T44	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	10		T28	8		T217	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	10		T42	9		T210	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T40	7		T43	7		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	1		T131	14		T97	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	10		T129	9		T136	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T96	8		T197	9		T247	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	9		T47	1		T59	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T39	8		T139	16		T238	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T199	18		T24	13		T30	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1362	1			T5	12		T49	7		T239	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12