Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22340

1

T1

1

T2

15

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3636

1

T2

28

T6

19

T8

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19310

1

T2

28

T3

20

T4

10

auto[1]

6666

1

T1

1

T2

15

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T210	15		T252	9		-	-
values[0]	56	1			T36	3		T238	17		T253	5
values[1]	779	1			T11	5		T48	13		T39	4
values[2]	838	1			T2	15		T6	11		T48	22
values[3]	903	1			T47	2		T39	9		T40	21
values[4]	792	1			T40	4		T60	1		T98	1
values[5]	746	1			T38	1		T60	15		T131	15
values[6]	691	1			T130	1		T152	14		T197	21
values[7]	729	1			T10	25		T129	10		T136	36
values[8]	3050	1			T1	1		T2	28		T3	20
values[9]	1241	1			T6	10		T8	3		T47	16
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1031	1			T11	5		T48	35		T38	1
values[1]	986	1			T2	15		T6	11		T46	1
values[2]	720	1			T47	2		T39	9		T40	25
values[3]	1015	1			T60	15		T25	14		T29	14
values[4]	477	1			T38	1		T60	1		T131	15
values[5]	792	1			T10	25		T136	14		T132	1
values[6]	2958	1			T1	1		T2	28		T5	13
values[7]	777	1			T3	20		T6	18		T8	16
values[8]	930	1			T47	16		T38	1		T39	9
values[9]	162	1			T8	3		T199	19		T209	1
minimum	16128	1			T4	10		T8	39		T50	110

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T11	1		T46	1		T59	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T48	19		T38	1		T39	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	8		T136	8		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T6	11		T46	1		T199	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	2		T39	9		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	2		T59	1		T12	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T60	6		T25	1		T201	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T60	1		T29	2		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T38	1		T13	3		T217	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T60	1		T131	15		T96	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T136	11		T132	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	12		T98	1		T254	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T1	1		T5	13		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	14		T10	2		T136	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	11		T6	10		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	8		T8	11		T32	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T47	16		T39	9		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T38	1		T44	13		T152	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T8	1		T255	1		T149	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T199	19		T209	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15990	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	4		T209	8		T33	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T48	16		T134	9		T24	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	7		T136	10		T97	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T133	14		T13	1		T139	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	13		T28	1		T173	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	2		T12	8		T177	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T60	8		T25	13		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T29	12		T202	1		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T13	1		T139	12		T256	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T210	11		T212	10		T257	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T136	3		T152	13		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	13		T236	10		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1133	1			T7	10		T48	10		T99	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T2	14		T10	3		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	9		T59	4		T15	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	4		T32	1		T42	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T210	10		T138	10		T206	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T44	11		T152	21		T28	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T8	2		T149	9		T175	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T258	4		T259	12		T260	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T210	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T252	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T36	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T238	17		T253	1		T261	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	1		T46	2		T209	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T48	7		T39	4		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	8		T59	1		T136	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	11		T48	12		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T47	2		T39	9		T40	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T46	1		T59	1		T199	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T98	1		T25	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T40	2		T60	1		T212	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T38	1		T60	6		T201	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T60	1		T131	15		T96	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T130	1		T152	1		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T197	10		T154	1		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T129	10		T136	11		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	12		T136	10		T135	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1552	1			T1	1		T3	11		T5	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	14		T6	8		T8	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	391	1			T6	10		T8	1		T47	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T38	1		T44	13		T199	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T210	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T252	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T36	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T253	4		T261	1		T262	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	4		T209	8		T25	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	6		T134	9		T24	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	7		T136	10		T33	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	10		T13	1		T139	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T40	13		T36	4		T219	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T133	14		T12	8		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T25	13		T28	1		T173	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	2		T212	21		T263	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T60	8		T139	12		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	12		T210	11		T202	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	13		T13	1		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T197	11		T176	9		T167	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T136	3		T34	1		T30	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	13		T136	12		T135	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T3	9		T7	10		T48	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	14		T8	4		T10	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T8	2		T59	4		T138	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T44	11		T152	21		T137	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T11	5		T46	1		T59	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T48	18		T38	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	8		T136	11		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T6	1		T46	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T47	1		T39	1		T40	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T40	3		T59	1		T12	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T60	9		T25	14		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T60	1		T29	14		T202	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T38	1		T13	3		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T60	1		T131	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T136	4		T132	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	14		T98	1		T254	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T1	1		T5	1		T7	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	15		T10	4		T136	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	10		T6	1		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	1		T8	5		T32	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T47	1		T39	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T38	1		T44	12		T152	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T8	3		T255	1		T149	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T199	1		T209	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16128	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T209	8		T33	2		T96	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T48	17		T39	3		T24	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	7		T136	7		T97	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	10		T199	14		T13	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T47	1		T39	8		T40	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	1		T12	2		T217	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T60	5		T201	5		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	1		T164	15		T212	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T13	1		T217	15		T139	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T131	14		T96	18		T210	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T136	10		T34	1		T201	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	11		T236	11		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T5	12		T48	3		T49	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T2	13		T10	1		T136	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	10		T6	9		T59	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	7		T8	10		T42	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T47	15		T39	8		T210	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T44	12		T152	21		T28	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T149	11		T264	2		T265	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T199	18		T258	2		T259	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T210	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T252	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T36	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T238	1		T253	5		T261	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	5		T46	2		T209	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T48	7		T39	1		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	8		T59	1		T136	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	1		T48	11		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T47	1		T39	1		T40	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T46	1		T59	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T98	1		T25	14		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T40	3		T60	1		T212	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T38	1		T60	9		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T60	1		T131	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T130	1		T152	14		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T197	12		T154	1		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T129	1		T136	4		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	14		T136	13		T135	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T1	1		T3	10		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	15		T6	1		T8	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	448	1			T6	1		T8	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T38	1		T44	12		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T210	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T36	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T238	16		T261	1		T262	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T209	8		T96	8		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T48	6		T39	3		T24	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	7		T136	7		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	10		T48	11		T13	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T47	1		T39	8		T40	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T199	14		T12	2		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T201	5		T138	11		T143	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	1		T212	20		T263	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T60	5		T201	14		T139	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T131	14		T96	18		T210	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	1		T217	15		T139	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T197	9		T167	9		T266	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T129	9		T136	10		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	11		T136	9		T135	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T3	10		T5	12		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	13		T6	7		T8	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T6	9		T47	15		T39	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T44	12		T199	18		T152	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12