Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22097

1

T1

1

T2

15

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

3879

1

T2

28

T3

20

T6

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19583

1

T2

15

T3

20

T4

10

auto[1]

6393

1

T1

1

T2

28

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	46	1			T144	20		T253	11		T214	15
values[0]	90	1			T39	9		T60	14		T222	1
values[1]	691	1			T8	3		T59	1		T152	14
values[2]	1071	1			T2	15		T48	22		T59	9
values[3]	542	1			T136	14		T131	16		T96	9
values[4]	3321	1			T1	1		T5	13		T7	11
values[5]	584	1			T11	5		T48	14		T199	19
values[6]	768	1			T2	28		T6	11		T8	15
values[7]	806	1			T3	20		T10	5		T47	16
values[8]	773	1			T6	8		T11	1		T38	1
values[9]	1157	1			T6	10		T8	1		T10	25
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1185	1			T2	15		T8	3		T48	22
values[1]	787	1			T59	2		T152	20		T135	25
values[2]	676	1			T47	2		T39	9		T59	8
values[3]	3068	1			T1	1		T5	13		T7	11
values[4]	848	1			T2	28		T6	11		T40	21
values[5]	751	1			T3	20		T48	14		T38	1
values[6]	733	1			T8	15		T10	5		T11	1
values[7]	661	1			T6	18		T8	1		T32	5
values[8]	1032	1			T10	25		T42	14		T129	10
values[9]	108	1			T138	25		T207	9		T211	13
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T2	8		T8	1		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T48	12		T39	9		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T59	1		T152	9		T135	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T59	1		T173	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	2		T39	9		T59	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T131	1		T98	1		T30	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T1	1		T5	13		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T199	19		T136	10		T217	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T136	8		T60	1		T24	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	14		T6	11		T40	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T38	1		T43	8		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	11		T48	4		T44	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	11		T10	2		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	1		T46	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	18		T32	4		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	1		T199	15		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T33	7		T35	2		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	438	1			T10	12		T42	10		T129	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T267	1		T216	1		T268	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T138	14		T207	1		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T2	7		T8	2		T60	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T48	10		T134	9		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T152	11		T135	14		T139	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T173	4		T177	4		T269	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T59	4		T173	4		T263	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T30	3		T173	12		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T7	10		T11	4		T48	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T136	12		T145	13		T269	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	10		T24	4		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	14		T40	13		T30	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T97	18		T13	1		T248	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	9		T48	10		T44	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	4		T10	3		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T137	4		T25	9		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T32	1		T40	2		T247	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T133	14		T210	11		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T33	3		T144	10		T16	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T10	13		T42	4		T12	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T267	14		T216	12		T268	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T138	11		T207	8		T211	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T144	10		T214	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T253	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T60	6		T222	1		T270	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T39	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	1		T59	1		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T152	1		T96	19		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T2	8		T59	4		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T48	12		T59	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T136	11		T131	15		T96	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T131	1		T98	1		T30	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1666	1			T1	1		T5	13		T7	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T217	27		T223	10		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	1		T24	14		T13	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	4		T199	19		T136	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	11		T38	1		T43	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	14		T6	11		T40	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T10	2		T47	16		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	11		T38	1		T44	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	8		T11	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T199	15		T29	2		T210	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	10		T32	4		T40	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	464	1			T8	1		T10	12		T42	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T144	10		T214	14		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T253	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T60	8		T270	9		T271	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	2		T210	10		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T152	13		T28	1		T143	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T2	7		T59	4		T152	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	10		T134	9		T143	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T136	3		T173	4		T211	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T30	3		T173	16		T177	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T7	10		T48	6		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T223	12		T256	10		T145	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T11	4		T24	4		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	10		T136	12		T202	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	4		T13	1		T212	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	14		T40	13		T137	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	3		T97	18		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	9		T44	11		T28	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T247	8		T272	13		T250	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	12		T210	11		T211	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T32	1		T40	2		T33	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	405	1			T10	13		T42	4		T133	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T2	8		T8	3		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T48	11		T39	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T59	1		T152	12		T135	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T59	1		T173	5		T177	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	1		T39	1		T59	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T131	1		T98	1		T30	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T1	1		T5	1		T7	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T199	1		T136	13		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T136	11		T60	1		T24	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	15		T6	1		T40	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T38	1		T43	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	10		T48	11		T44	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	5		T10	4		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T38	1		T46	1		T137	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	2		T32	5		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	1		T199	1		T133	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T33	8		T35	2		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	431	1			T10	14		T42	5		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T267	15		T216	13		T268	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T138	12		T207	9		T211	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	7		T60	5		T209	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T48	11		T39	8		T96	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T152	8		T135	10		T131	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T224	5		T269	1		T273	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T47	1		T39	8		T59	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T30	5		T201	14		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T5	12		T48	6		T49	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T199	18		T136	9		T217	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T136	7		T24	13		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	13		T6	10		T40	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T43	7		T97	11		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	10		T48	3		T44	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	10		T10	1		T47	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T222	5		T235	10		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	16		T40	1		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T199	14		T210	3		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T33	2		T144	9		T16	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T10	11		T42	9		T129	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T268	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T138	13		T158	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T144	11		T214	15		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T253	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T60	9		T222	1		T270	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T39	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	3		T59	1		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T152	14		T96	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T2	8		T59	5		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	11		T59	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T136	4		T131	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T131	1		T98	1		T30	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T1	1		T5	1		T7	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T217	2		T223	13		T256	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	5		T24	5		T13	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	11		T199	1		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	5		T38	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	15		T6	1		T40	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	4		T47	1		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	10		T38	1		T44	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	1		T11	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T199	1		T29	14		T210	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	1		T32	5		T40	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	492	1			T8	1		T10	14		T42	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T144	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T253	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T60	5		T271	14		T274	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T39	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T210	4		T14	1		T36	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T96	18		T28	8		T202	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T2	7		T59	3		T152	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	11		T96	14		T141	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T136	10		T131	14		T96	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T30	5		T201	14		T248	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T5	12		T47	1		T48	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T217	25		T223	9		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T24	13		T13	1		T198	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	3		T199	18		T136	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	10		T43	7		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	13		T6	10		T40	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	1		T47	15		T97	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	10		T44	12		T197	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	7		T39	3		T247	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T199	14		T210	3		T222	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T6	9		T40	1		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T10	11		T42	9		T129	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12