Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22230

1

T1

1

T2

28

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

3746

1

T2

15

T3

20

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19489

1

T2

43

T3

20

T4

10

auto[1]

6487

1

T1

1

T5

13

T6

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	449	1			T50	2		T45	1		T33	3
values[0]	42	1			T46	1		T30	1		T275	10
values[1]	865	1			T6	11		T10	5		T47	16
values[2]	3119	1			T1	1		T5	13		T7	11
values[3]	710	1			T48	22		T199	19		T136	18
values[4]	871	1			T2	15		T8	4		T47	2
values[5]	592	1			T3	20		T134	10		T135	25
values[6]	664	1			T46	1		T133	15		T137	5
values[7]	973	1			T6	8		T11	1		T38	2
values[8]	790	1			T6	10		T48	14		T42	14
values[9]	1174	1			T2	28		T48	13		T43	8
minimum	15727	1			T4	10		T8	39		T50	108

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	945	1			T10	5		T47	16		T39	13
values[1]	3298	1			T1	1		T5	13		T6	11
values[2]	675	1			T46	1		T59	1		T199	19
values[3]	830	1			T2	15		T8	4		T32	5
values[4]	592	1			T3	20		T47	2		T134	10
values[5]	802	1			T11	1		T38	1		T46	1
values[6]	726	1			T48	14		T38	1		T39	9
values[7]	863	1			T6	18		T40	21		T42	14
values[8]	864	1			T48	13		T129	10		T59	8
values[9]	231	1			T2	28		T43	8		T177	1
minimum	16150	1			T4	10		T8	39		T50	110

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T10	2		T152	1		T28	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T47	16		T39	13		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1621	1			T1	1		T5	13		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T6	11		T8	11		T10	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T59	1		T199	19		T25	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	1		T98	1		T34	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	2		T32	4		T96	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	8		T44	13		T152	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	2		T134	1		T135	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	11		T209	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	1		T38	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T133	1		T29	2		T30	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	4		T38	1		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T199	15		T28	1		T197	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T6	10		T40	8		T42	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	8		T59	1		T96	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T59	4		T132	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T48	7		T129	10		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T2	14		T177	1		T167	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T43	8		T276	8		T277	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16002	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	3		T152	13		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	3		T223	10		T143	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T7	10		T136	10		T60	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	4		T10	13		T11	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T25	21		T177	4		T248	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T34	1		T13	1		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	2		T32	1		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	7		T44	11		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T134	9		T135	14		T137	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	9		T25	9		T36	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T209	8		T210	11		T173	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T133	14		T29	12		T30	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	10		T12	8		T173	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T28	1		T197	11		T153	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T40	13		T42	4		T97	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T263	1		T270	4		T215	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T59	4		T210	10		T202	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	6		T139	12		T212	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T2	14		T167	10		T21	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T276	1		T277	9		T278	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T59	1		T60	3		T29	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	405	1			T50	2		T45	1		T33	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T278	13		T240	5		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T30	1		T233	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T46	1		T275	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T10	2		T130	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	11		T47	16		T39	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1564	1			T1	1		T5	13		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T8	11		T10	12		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T199	19		T136	8		T60	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	12		T98	1		T34	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	2		T47	2		T32	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	8		T44	13		T152	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T134	1		T135	11		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	11		T131	1		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	1		T137	1		T209	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T133	1		T29	2		T30	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	1		T38	2		T39	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T6	8		T199	15		T201	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	10		T48	4		T42	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T59	1		T96	28		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T2	14		T59	4		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T48	7		T43	8		T129	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15589	1			T4	10		T8	39		T50	108
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T205	1		T279	14		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T278	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T233	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T275	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	3		T152	13		T28	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T136	12		T212	11		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T7	10		T152	10		T33	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	4		T10	13		T11	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	10		T60	8		T25	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T48	10		T34	1		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	2		T32	1		T25	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	7		T44	11		T152	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T134	9		T135	14		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	9		T25	9		T202	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	4		T209	8		T210	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T133	14		T29	12		T30	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T40	13		T12	8		T173	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T207	11		T177	12		T248	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	10		T42	4		T97	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T28	1		T197	11		T153	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T2	14		T59	4		T210	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T48	6		T139	12		T212	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T10	4		T152	14		T28	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T47	1		T39	2		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T1	1		T5	1		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T6	1		T8	5		T10	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T59	1		T199	1		T25	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T46	1		T98	1		T34	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	4		T32	5		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	8		T44	12		T152	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T47	1		T134	10		T135	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	10		T209	1		T25	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	1		T38	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T133	15		T29	14		T30	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T48	11		T38	1		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T199	1		T28	2		T197	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T6	1		T40	14		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T59	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T59	5		T132	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T48	7		T129	1		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T2	15		T177	1		T167	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T43	1		T276	7		T277	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16139	1			T4	10		T8	39		T50	110
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T10	1		T28	8		T197	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T47	15		T39	11		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T5	12		T49	7		T239	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	10		T8	10		T10	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T199	18		T248	6		T229	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T34	1		T13	1		T217	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T96	14		T138	11		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	7		T44	12		T152	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T47	1		T135	10		T143	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T3	10		T36	2		T235	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T209	8		T210	3		T198	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	5		T201	14		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	3		T39	8		T12	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T199	14		T197	9		T222	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T6	9		T40	7		T42	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	7		T96	8		T218	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T59	3		T210	4		T198	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T48	6		T129	9		T96	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T2	13		T167	9		T21	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T43	7		T276	2		T277	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T36	1		T280	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T50	2		T45	1		T33	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T278	11		T240	1		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T30	1		T233	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T46	1		T275	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	4		T130	1		T152	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	1		T47	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T1	1		T5	1		T7	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T8	5		T10	14		T11	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T199	1		T136	11		T60	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	11		T98	1		T34	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T8	4		T47	1		T32	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T2	8		T44	12		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T134	10		T135	15		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	10		T131	1		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	1		T137	5		T209	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T133	15		T29	14		T30	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	1		T38	2		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	1		T199	1		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	1		T48	11		T42	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T59	1		T96	2		T28	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T2	15		T59	5		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T48	7		T43	1		T129	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15727	1			T4	10		T8	39		T50	108
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T205	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T278	12		T240	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T233	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	1		T28	8		T197	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	10		T47	15		T39	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T5	12		T49	7		T239	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	10		T10	11		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T199	18		T136	7		T60	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T48	11		T34	1		T217	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T47	1		T96	14		T138	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	7		T44	12		T152	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T135	10		T143	8		T90	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T3	10		T235	10		T269	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T209	8		T210	3		T164	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T30	5		T13	1		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T39	8		T40	7		T12	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	7		T199	14		T201	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	9		T48	3		T42	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T96	26		T197	9		T218	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T2	13		T59	3		T210	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T48	6		T43	7		T129	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12