Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22062

1

T1

1

T2

28

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3914

1

T2

15

T6

21

T8

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19777

1

T2

15

T3

20

T4

10

auto[1]

6199

1

T1

1

T2

28

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T34	8		-	-		-	-
values[0]	83	1			T137	5		T229	20		T281	1
values[1]	835	1			T2	28		T6	8		T46	1
values[2]	725	1			T3	20		T6	11		T8	15
values[3]	913	1			T6	10		T11	1		T47	2
values[4]	637	1			T8	3		T10	5		T47	16
values[5]	697	1			T11	5		T46	1		T152	14
values[6]	823	1			T39	4		T43	8		T199	15
values[7]	824	1			T48	13		T131	15		T12	13
values[8]	446	1			T136	18		T130	1		T30	1
values[9]	3858	1			T1	1		T2	15		T5	13
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1078	1			T6	19		T46	1		T199	19
values[1]	682	1			T3	20		T8	15		T48	22
values[2]	782	1			T6	10		T11	1		T39	9
values[3]	833	1			T8	3		T10	5		T11	5
values[4]	740	1			T39	4		T46	1		T60	1
values[5]	755	1			T48	13		T43	8		T199	15
values[6]	3061	1			T1	1		T5	13		T7	11
values[7]	489	1			T136	18		T130	1		T28	2
values[8]	1052	1			T2	15		T38	1		T40	4
values[9]	309	1			T8	1		T10	25		T48	14
minimum	16195	1			T2	28		T4	10		T8	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T6	8		T136	11		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T6	11		T46	1		T199	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	11		T32	4		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	11		T48	12		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	9		T152	9		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T6	10		T11	1		T40	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	1		T47	2		T39	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T8	1		T10	2		T47	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T39	4		T46	1		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T152	14		T209	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T43	8		T97	12		T12	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T48	7		T199	15		T24	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T1	1		T5	13		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T131	15		T202	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T136	8		T130	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T30	1		T254	1		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T40	2		T59	1		T96	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	8		T38	1		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T48	4		T98	1		T197	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T8	1		T10	12		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16017	1			T2	14		T4	10		T8	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T98	1		T282	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T136	3		T25	13		T210	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T136	12		T133	14		T137	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	9		T32	1		T139	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	4		T48	10		T209	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T152	11		T135	14		T30	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	13		T42	4		T44	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	4		T60	8		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	2		T10	3		T29	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T152	13		T202	1		T219	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T152	10		T25	8		T138	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T97	18		T12	8		T173	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	6		T24	4		T173	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T7	10		T99	27		T26	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T202	1		T153	6		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T136	10		T28	1		T207	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T263	1		T147	10		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T40	2		T34	1		T177	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T2	7		T59	4		T33	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T48	10		T143	9		T211	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T10	13		T212	10		T54	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	14		T59	1		T60	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T282	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T34	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T229	10		T271	15		T233	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T137	1		T281	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T2	14		T6	8		T210	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T46	1		T136	10		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	11		T32	4		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	11		T8	11		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T47	2		T39	9		T152	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T6	10		T11	1		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	9		T130	1		T60	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	1		T10	2		T47	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	1		T46	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T25	1		T29	2		T197	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	4		T43	8		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T199	15		T152	14		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	5		T173	1		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T48	7		T131	15		T201	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T136	8		T130	1		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T30	1		T202	1		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1837	1			T1	1		T5	13		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T2	8		T8	1		T10	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T34	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T229	10		T271	12		T233	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T137	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	14		T210	11		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T136	12		T133	14		T25	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	9		T32	1		T136	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T8	4		T28	1		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T152	11		T135	14		T30	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T48	10		T40	13		T42	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T60	8		T153	9		T143	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	2		T10	3		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	4		T152	13		T202	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T25	8		T29	12		T197	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T97	18		T173	4		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T152	10		T24	4		T173	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	8		T173	12		T269	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	6		T153	6		T15	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T136	10		T13	1		T215	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T202	1		T263	1		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T7	10		T48	10		T40	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T2	7		T10	13		T59	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T6	1		T136	4		T25	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	1		T46	1		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	10		T32	5		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	5		T48	11		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	1		T152	12		T135	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	1		T11	1		T40	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	5		T47	1		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T8	3		T10	4		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T39	1		T46	1		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T152	11		T209	1		T25	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T43	1		T97	19		T12	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T48	7		T199	1		T24	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T1	1		T5	1		T7	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T131	1		T202	2		T153	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T136	11		T130	1		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T30	1		T254	1		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T40	3		T59	1		T96	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T2	8		T38	1		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T48	11		T98	1		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T8	1		T10	14		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16150	1			T2	15		T4	10		T8	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T98	1		T282	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	7		T136	10		T210	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	10		T199	18		T136	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	10		T217	15		T139	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	10		T48	11		T209	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T39	8		T152	8		T135	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	9		T40	7		T42	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T47	1		T39	8		T60	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	1		T47	15		T197	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T39	3		T219	9		T243	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T152	13		T138	2		T139	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T43	7		T97	11		T12	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	6		T199	14		T24	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T5	12		T49	7		T239	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T131	14		T223	9		T235	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T136	7		T249	22		T16	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T174	12		T147	12		T245	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T40	1		T96	22		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	7		T59	3		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T48	3		T197	7		T143	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T10	11		T212	10		T284	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T2	13		T285	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T282	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T34	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T229	11		T271	13		T233	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T137	5		T281	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	15		T6	1		T210	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T46	1		T136	13		T133	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	10		T32	5		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	1		T8	5		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T47	1		T39	1		T152	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T6	1		T11	1		T48	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	1		T130	1		T60	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	3		T10	4		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	5		T46	1		T152	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T25	9		T29	14		T197	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T39	1		T43	1		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T199	1		T152	11		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	11		T173	13		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T48	7		T131	1		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T136	11		T130	1		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	1		T202	2		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1705	1			T1	1		T5	1		T7	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T2	8		T8	1		T10	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T34	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T229	9		T271	14		T233	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	13		T6	7		T210	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T136	9		T30	3		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	10		T136	10		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	10		T8	10		T199	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	1		T39	8		T152	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T6	9		T48	11		T40	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T39	8		T60	5		T286	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	1		T47	15		T129	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T219	9		T272	16		T237	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T197	9		T139	16		T178	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	3		T43	7		T97	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T199	14		T152	13		T24	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	2		T269	1		T158	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	6		T131	14		T201	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T136	7		T13	1		T257	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T145	10		T147	12		T245	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T5	12		T48	3		T49	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	7		T10	11		T59	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12