Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22355

1

T1

1

T2

15

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3621

1

T2

28

T6

19

T8

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19288

1

T2

28

T3

20

T4

10

auto[1]

6688

1

T1

1

T2

15

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	132	1			T30	1		T210	15		T255	1
values[0]	50	1			T24	18		T287	25		T253	5
values[1]	738	1			T11	5		T48	13		T39	4
values[2]	786	1			T2	15		T6	11		T48	22
values[3]	1057	1			T47	2		T39	9		T40	21
values[4]	787	1			T40	4		T60	1		T98	1
values[5]	699	1			T38	1		T60	15		T131	15
values[6]	643	1			T130	1		T152	14		T201	15
values[7]	762	1			T10	25		T129	10		T136	36
values[8]	3051	1			T1	1		T2	28		T3	20
values[9]	1144	1			T6	10		T8	3		T47	16
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	779	1			T48	35		T38	1		T46	2
values[1]	962	1			T2	15		T6	11		T46	1
values[2]	813	1			T47	2		T39	9		T40	25
values[3]	943	1			T60	15		T25	14		T29	14
values[4]	502	1			T38	1		T60	1		T131	15
values[5]	761	1			T136	14		T132	1		T130	1
values[6]	2951	1			T1	1		T5	13		T7	11
values[7]	940	1			T2	28		T3	20		T6	18
values[8]	898	1			T47	16		T38	1		T39	9
values[9]	79	1			T8	3		T30	1		T255	1
minimum	16348	1			T4	10		T8	39		T11	5

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T48	7		T46	2		T59	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T48	12		T38	1		T30	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	8		T136	8		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T6	11		T46	1		T199	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T47	2		T39	9		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T40	2		T59	1		T12	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T60	6		T25	1		T201	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T60	1		T29	2		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T38	1		T13	3		T139	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T60	1		T131	15		T96	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T136	11		T132	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T254	1		T154	1		T236	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T1	1		T5	13		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T10	14		T136	10		T135	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	11		T6	10		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	14		T6	8		T8	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T47	16		T39	9		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T38	1		T44	13		T199	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T8	1		T255	1		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T30	1		T166	1		T288	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16039	1			T4	10		T8	39		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T39	4		T134	1		T24	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T48	6		T33	3		T25	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	10		T30	3		T269	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	7		T136	10		T97	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T133	14		T13	1		T139	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T40	13		T28	1		T173	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T40	2		T12	8		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T60	8		T25	13		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	12		T202	1		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T13	1		T139	12		T212	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T210	11		T257	11		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T136	3		T152	13		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T236	10		T143	11		T180	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T7	10		T48	10		T99	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T10	16		T136	12		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	9		T59	4		T197	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	14		T8	4		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T210	10		T138	10		T206	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T44	11		T152	21		T28	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T8	2		T149	9		T264	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T288	2		T258	4		T259	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	4		T59	1		T60	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T134	9		T24	4		T287	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T210	5		T255	1		T35	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T30	1		T166	1		T258	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T24	14		T287	12		T253	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	1		T48	7		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	4		T134	1		T30	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	8		T59	1		T136	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	11		T48	12		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T47	2		T39	9		T40	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T46	1		T59	1		T199	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T98	1		T25	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T40	2		T60	1		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T38	1		T60	6		T13	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T60	1		T131	15		T96	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T130	1		T152	1		T201	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T154	1		T289	1		T290	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T129	10		T136	11		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	12		T136	10		T135	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T1	1		T3	11		T5	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	14		T6	8		T8	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T6	10		T8	1		T47	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T38	1		T44	13		T199	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T210	10		T291	2		T292	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T258	4		T168	2		T101	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T24	4		T287	13		T253	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	4		T48	6		T209	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	9		T30	3		T269	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	7		T136	10		T33	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	10		T13	1		T139	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T40	13		T97	18		T173	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T133	14		T12	8		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T25	13		T28	1		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T40	2		T14	1		T212	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T60	8		T13	1		T139	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	12		T210	11		T202	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T152	13		T139	13		T223	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T176	9		T167	7		T275	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T136	3		T34	1		T30	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	13		T136	12		T135	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1120	1			T3	9		T7	10		T48	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	14		T8	4		T10	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T8	2		T59	4		T138	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T44	11		T152	21		T137	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	7		T46	2		T59	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T48	11		T38	1		T30	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	8		T136	11		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	1		T46	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T47	1		T39	1		T40	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T40	3		T59	1		T12	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T60	9		T25	14		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T60	1		T29	14		T202	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T38	1		T13	3		T139	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T60	1		T131	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T136	4		T132	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T254	1		T154	1		T236	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T1	1		T5	1		T7	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	18		T136	13		T135	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T3	10		T6	1		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	15		T6	1		T8	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T47	1		T39	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T38	1		T44	12		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T8	3		T255	1		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T30	1		T166	1		T288	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16177	1			T4	10		T8	39		T11	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T39	1		T134	10		T24	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T48	6		T33	2		T96	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	11		T30	3		T198	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	7		T136	7		T97	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	10		T199	14		T13	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	1		T39	8		T40	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T40	1		T12	2		T217	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T60	5		T201	5		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	1		T212	10		T263	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T13	1		T139	15		T212	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T131	14		T96	18		T210	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T136	10		T34	1		T201	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T236	11		T143	10		T180	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T5	12		T48	3		T49	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T10	12		T136	9		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	10		T6	9		T59	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	13		T6	7		T8	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	15		T39	8		T210	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T44	12		T199	18		T152	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T149	11		T264	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T258	2		T259	18		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T209	8		T138	13		T144	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	3		T24	13		T174	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T210	11		T255	1		T35	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T30	1		T166	1		T258	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T24	5		T287	14		T253	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	5		T48	7		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T39	1		T134	10		T30	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	8		T59	1		T136	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T48	11		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T47	1		T39	1		T40	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T46	1		T59	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T98	1		T25	14		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T40	3		T60	1		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T38	1		T60	9		T13	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T60	1		T131	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T130	1		T152	14		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T154	1		T289	1		T290	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T129	1		T136	4		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	14		T136	13		T135	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1464	1			T1	1		T3	10		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	15		T6	1		T8	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T6	1		T8	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T38	1		T44	12		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T210	4		T260	12		T293	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T258	2		T168	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T24	13		T287	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	6		T209	8		T96	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T39	3		T30	3		T198	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	7		T136	7		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	10		T48	11		T13	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T47	1		T39	8		T40	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T199	14		T12	2		T217	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T201	5		T138	11		T145	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T40	1		T14	1		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T60	5		T13	1		T139	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T131	14		T96	18		T210	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T201	14		T217	15		T139	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T167	9		T266	11		T294	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T129	9		T136	10		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	11		T136	9		T135	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T3	10		T5	12		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	13		T6	7		T8	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T6	9		T47	15		T39	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T44	12		T199	18		T152	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12