Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25976

1

T1

1

T2

43

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21623

1

T1

1

T2

15

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

4353

1

T2

28

T3

20

T6

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19549

1

T4

10

T6

18

T8

55

auto[1]

6427

1

T1

1

T2

43

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21509

1

T1

1

T2

22

T3

11

auto[1]

4467

1

T2

21

T3

9

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	150	1			T13	3		T15	15		T36	3
values[0]	43	1			T197	34		T221	8		T295	1
values[1]	861	1			T38	1		T43	8		T46	1
values[2]	3035	1			T1	1		T5	13		T6	19
values[3]	696	1			T2	28		T11	5		T39	4
values[4]	754	1			T6	10		T8	3		T32	5
values[5]	838	1			T8	15		T47	2		T136	22
values[6]	940	1			T10	5		T11	1		T48	13
values[7]	579	1			T2	15		T48	22		T38	1
values[8]	913	1			T3	20		T8	1		T199	19
values[9]	1040	1			T10	25		T47	16		T48	14
minimum	16127	1			T4	10		T8	39		T50	110

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	899	1			T38	1		T43	8		T46	1
values[1]	2948	1			T1	1		T5	13		T6	19
values[2]	736	1			T2	28		T40	4		T46	1
values[3]	740	1			T6	10		T8	3		T32	5
values[4]	870	1			T8	15		T47	2		T39	9
values[5]	815	1			T10	5		T11	1		T48	35
values[6]	764	1			T2	15		T8	1		T38	1
values[7]	797	1			T3	20		T47	16		T199	19
values[8]	903	1			T10	25		T48	14		T42	14
values[9]	125	1			T15	14		T200	13		T195	19
minimum	16379	1			T4	10		T8	39		T50	110

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

4421

1

T2

20

T3

10

T5

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T38	1		T59	1		T136	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T43	8		T46	1		T59	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1565	1			T1	1		T5	13		T6	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	11		T11	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T40	2		T46	1		T199	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	14		T152	9		T96	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	10		T8	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T32	4		T60	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T136	10		T98	1		T30	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T8	11		T47	2		T39	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	2		T46	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T11	1		T48	19		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	8		T38	1		T96	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	1		T132	1		T97	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T137	1		T210	4		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T3	11		T47	16		T199	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	12		T48	4		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T42	10		T130	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T204	6		T205	11		T296	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T15	4		T200	13		T195	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16063	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T25	1		T222	1		T245	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T136	10		T25	8		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T59	4		T134	9		T28	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T7	10		T60	8		T135	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T11	4		T202	1		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T40	2		T36	4		T206	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	14		T152	11		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	2		T133	14		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T32	1		T152	13		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T136	12		T30	3		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T8	4		T44	11		T209	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	3		T177	12		T178	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T48	16		T40	13		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	7		T210	10		T211	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T97	18		T24	4		T236	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T137	4		T210	11		T202	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	9		T152	10		T197	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	13		T48	10		T136	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T42	4		T13	1		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T204	8		T205	2		T213	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T15	10		T195	8		T20	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T59	1		T60	3		T29	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T25	13		T245	9		T297	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T15	1		T203	8		T226	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T13	2		T15	4		T36	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T197	20		T221	8		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	1		T136	8		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T43	8		T46	1		T59	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T1	1		T5	13		T6	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	11		T28	9		T30	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T40	2		T199	15		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	14		T11	1		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	10		T8	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T32	4		T152	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T136	10		T98	1		T30	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T8	11		T47	2		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	2		T46	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T11	1		T48	7		T39	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	8		T38	1		T210	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T48	12		T97	12		T24	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T137	1		T96	19		T210	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T3	11		T8	1		T199	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T10	12		T48	4		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T47	16		T42	10		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15989	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T298	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T13	1		T15	10		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T197	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	10		T28	1		T13	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T59	4		T134	9		T25	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T7	10		T60	8		T99	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T28	1		T30	3		T202	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	2		T135	14		T36	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	14		T11	4		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T8	2		T133	14		T33	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T32	1		T152	13		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T136	12		T30	3		T84	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	4		T209	8		T207	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	3		T177	12		T243	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T48	6		T40	13		T44	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T2	7		T210	10		T178	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	10		T97	18		T24	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T137	4		T210	11		T202	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	9		T152	10		T207	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T10	13		T48	10		T136	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T42	4		T197	11		T223	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T60	3		T29	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	1		T59	1		T136	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T43	1		T46	1		T59	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T1	1		T5	1		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	1		T11	5		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T40	3		T46	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	15		T152	12		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T8	3		T133	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T32	5		T60	1		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T136	13		T98	1		T30	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T8	5		T47	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	4		T46	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T11	1		T48	18		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	8		T38	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	1		T132	1		T97	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T137	5		T210	12		T202	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	10		T47	1		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	14		T48	11		T136	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T42	5		T130	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T204	9		T205	3		T296	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T15	13		T200	1		T195	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16197	1			T4	10		T8	39		T50	110
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T25	14		T222	1		T245	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T136	7		T197	7		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T43	7		T59	3		T28	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T5	12		T6	7		T49	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T6	10		T39	3		T139	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	1		T199	14		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	13		T152	8		T96	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	9		T33	2		T141	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T131	14		T14	2		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T136	9		T30	5		T201	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T8	10		T47	1		T39	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	1		T177	9		T178	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	17		T39	8		T40	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	7		T96	18		T210	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T97	11		T24	13		T174	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T210	3		T212	10		T219	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	10		T47	15		T199	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	11		T48	3		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T42	9		T201	14		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T204	5		T205	10		T296	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T15	1		T200	12		T195	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T197	11		T84	14		T299	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T245	7		T300	6		T274	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T15	1		T203	1		T226	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T13	2		T15	13		T36	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T197	16		T221	1		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T38	1		T136	11		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T43	1		T46	1		T59	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T1	1		T5	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T28	2		T30	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	3		T199	1		T135	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	15		T11	5		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	1		T8	3		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T32	5		T152	14		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T136	13		T98	1		T30	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T8	5		T47	1		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	4		T46	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T11	1		T48	7		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	8		T38	1		T210	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T48	11		T97	19		T24	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T137	5		T96	1		T210	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T3	10		T8	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T10	14		T48	11		T136	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T47	1		T42	5		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16127	1			T4	10		T8	39		T50	110
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T203	7		T296	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	1		T15	1		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T197	18		T221	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T136	7		T13	1		T222	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T43	7		T59	3		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T5	12		T6	7		T49	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	10		T28	8		T30	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	1		T199	14		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	13		T39	3		T152	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	9		T33	2		T223	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	2		T212	10		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T136	9		T30	5		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T8	10		T47	1		T131	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	1		T201	5		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T48	6		T39	16		T40	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	7		T210	4		T178	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T48	11		T97	11		T24	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T96	18		T210	3		T212	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	10		T199	18		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T10	11		T48	3		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T47	15		T42	9		T197	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21555

1

T1

1

T2

23

T3

10

auto[1]

auto[0]

4421

1

T2

20

T3

10

T5

12