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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.22


Total test records in report: 918
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T797 /workspace/coverage/default/0.adc_ctrl_clock_gating.2596577206 Aug 04 04:57:39 PM PDT 24 Aug 04 05:04:44 PM PDT 24 487422973087 ps
T798 /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3277257710 Aug 04 04:57:55 PM PDT 24 Aug 04 04:58:15 PM PDT 24 33707690806 ps
T799 /workspace/coverage/default/12.adc_ctrl_alert_test.3087890958 Aug 04 04:58:46 PM PDT 24 Aug 04 04:58:47 PM PDT 24 470834013 ps
T112 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3336150205 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:31 PM PDT 24 399949720 ps
T800 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1081072724 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:34 PM PDT 24 348653858 ps
T110 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3203572485 Aug 04 05:30:34 PM PDT 24 Aug 04 05:30:36 PM PDT 24 517823305 ps
T801 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2290504320 Aug 04 05:31:00 PM PDT 24 Aug 04 05:31:01 PM PDT 24 420794380 ps
T94 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2850835699 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:33 PM PDT 24 483247705 ps
T55 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4191393210 Aug 04 05:30:19 PM PDT 24 Aug 04 05:30:27 PM PDT 24 2890143009 ps
T61 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1338588642 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:41 PM PDT 24 4385921944 ps
T62 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1690714967 Aug 04 05:30:28 PM PDT 24 Aug 04 05:30:40 PM PDT 24 4615580131 ps
T64 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.963784863 Aug 04 05:30:20 PM PDT 24 Aug 04 05:30:23 PM PDT 24 403130198 ps
T802 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.158296222 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:32 PM PDT 24 392002904 ps
T95 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.217067660 Aug 04 05:30:26 PM PDT 24 Aug 04 05:30:27 PM PDT 24 368531435 ps
T803 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1884213881 Aug 04 05:30:17 PM PDT 24 Aug 04 05:30:18 PM PDT 24 319836622 ps
T113 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.233319633 Aug 04 05:30:36 PM PDT 24 Aug 04 05:30:38 PM PDT 24 566110238 ps
T58 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3515717553 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:33 PM PDT 24 568748304 ps
T69 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2510074185 Aug 04 05:30:30 PM PDT 24 Aug 04 05:30:31 PM PDT 24 377309956 ps
T804 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3479517666 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:31 PM PDT 24 550190922 ps
T805 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.666014608 Aug 04 05:30:43 PM PDT 24 Aug 04 05:30:44 PM PDT 24 429971352 ps
T70 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3827625453 Aug 04 05:30:28 PM PDT 24 Aug 04 05:30:30 PM PDT 24 498517406 ps
T56 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3873566075 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:31 PM PDT 24 5408426838 ps
T806 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1659509562 Aug 04 05:30:28 PM PDT 24 Aug 04 05:30:29 PM PDT 24 453577184 ps
T807 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2642374304 Aug 04 05:30:25 PM PDT 24 Aug 04 05:30:26 PM PDT 24 411170294 ps
T122 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.121457149 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:31 PM PDT 24 535226327 ps
T808 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3457086182 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:36 PM PDT 24 523595067 ps
T77 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2882613291 Aug 04 05:30:35 PM PDT 24 Aug 04 05:30:37 PM PDT 24 671092113 ps
T809 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2674063641 Aug 04 05:30:46 PM PDT 24 Aug 04 05:30:53 PM PDT 24 493086163 ps
T123 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2078282677 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:35 PM PDT 24 438288752 ps
T63 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2995510703 Aug 04 05:30:28 PM PDT 24 Aug 04 05:30:40 PM PDT 24 4376944552 ps
T57 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2004474105 Aug 04 05:30:21 PM PDT 24 Aug 04 05:30:38 PM PDT 24 26482981404 ps
T810 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2266012195 Aug 04 05:30:59 PM PDT 24 Aug 04 05:31:00 PM PDT 24 456365226 ps
T811 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4029341248 Aug 04 05:30:56 PM PDT 24 Aug 04 05:30:57 PM PDT 24 334871012 ps
T78 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2865715607 Aug 04 05:30:27 PM PDT 24 Aug 04 05:30:30 PM PDT 24 396151878 ps
T124 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2263234377 Aug 04 05:30:21 PM PDT 24 Aug 04 05:30:25 PM PDT 24 3046129395 ps
T80 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3418835917 Aug 04 05:30:40 PM PDT 24 Aug 04 05:30:51 PM PDT 24 4390263649 ps
T812 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2680507063 Aug 04 05:30:40 PM PDT 24 Aug 04 05:30:42 PM PDT 24 503801366 ps
T813 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3823524620 Aug 04 05:30:44 PM PDT 24 Aug 04 05:30:45 PM PDT 24 330170181 ps
T814 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2552435309 Aug 04 05:30:41 PM PDT 24 Aug 04 05:30:42 PM PDT 24 403953767 ps
T125 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2744861562 Aug 04 05:30:46 PM PDT 24 Aug 04 05:30:50 PM PDT 24 2256908406 ps
T815 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1498202218 Aug 04 05:30:44 PM PDT 24 Aug 04 05:30:45 PM PDT 24 306320897 ps
T111 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3686653264 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:32 PM PDT 24 478325344 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.749451014 Aug 04 05:30:22 PM PDT 24 Aug 04 05:30:29 PM PDT 24 5698378375 ps
T71 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2081923661 Aug 04 05:30:40 PM PDT 24 Aug 04 05:30:41 PM PDT 24 559418080 ps
T65 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.87056047 Aug 04 05:30:28 PM PDT 24 Aug 04 05:30:35 PM PDT 24 4456940584 ps
T816 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3625336276 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:33 PM PDT 24 447436719 ps
T72 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1466590722 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:31 PM PDT 24 688693845 ps
T127 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2973868004 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:32 PM PDT 24 317656714 ps
T73 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1738473094 Aug 04 05:30:35 PM PDT 24 Aug 04 05:30:39 PM PDT 24 618987206 ps
T817 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.4019238446 Aug 04 05:30:42 PM PDT 24 Aug 04 05:30:43 PM PDT 24 294838634 ps
T818 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2841578004 Aug 04 05:30:58 PM PDT 24 Aug 04 05:30:59 PM PDT 24 519753176 ps
T114 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.598806480 Aug 04 05:30:20 PM PDT 24 Aug 04 05:30:23 PM PDT 24 943535199 ps
T115 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2500586788 Aug 04 05:30:24 PM PDT 24 Aug 04 05:30:25 PM PDT 24 411532200 ps
T819 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3632899019 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:30 PM PDT 24 412635356 ps
T74 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2297655134 Aug 04 05:30:19 PM PDT 24 Aug 04 05:30:23 PM PDT 24 385963576 ps
T81 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1676330760 Aug 04 05:30:25 PM PDT 24 Aug 04 05:30:35 PM PDT 24 4152766707 ps
T820 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.886656554 Aug 04 05:30:35 PM PDT 24 Aug 04 05:30:36 PM PDT 24 307055756 ps
T821 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2877566082 Aug 04 05:30:35 PM PDT 24 Aug 04 05:30:37 PM PDT 24 507441506 ps
T822 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3494044350 Aug 04 05:30:24 PM PDT 24 Aug 04 05:30:29 PM PDT 24 3983899789 ps
T116 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1752963014 Aug 04 05:30:18 PM PDT 24 Aug 04 05:30:22 PM PDT 24 793983021 ps
T823 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.317438212 Aug 04 05:30:45 PM PDT 24 Aug 04 05:30:50 PM PDT 24 2210735446 ps
T824 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1039962922 Aug 04 05:30:21 PM PDT 24 Aug 04 05:30:23 PM PDT 24 873105849 ps
T825 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2989044848 Aug 04 05:30:30 PM PDT 24 Aug 04 05:31:36 PM PDT 24 26014606101 ps
T826 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2102429521 Aug 04 05:30:28 PM PDT 24 Aug 04 05:30:33 PM PDT 24 1090343673 ps
T827 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.827998437 Aug 04 05:30:35 PM PDT 24 Aug 04 05:30:57 PM PDT 24 7998445824 ps
T828 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3320475540 Aug 04 05:30:30 PM PDT 24 Aug 04 05:30:41 PM PDT 24 4378769462 ps
T329 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3694450694 Aug 04 05:30:22 PM PDT 24 Aug 04 05:30:37 PM PDT 24 8084580411 ps
T829 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2735851911 Aug 04 05:30:39 PM PDT 24 Aug 04 05:30:41 PM PDT 24 335270033 ps
T830 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3635147518 Aug 04 05:30:57 PM PDT 24 Aug 04 05:30:59 PM PDT 24 495653997 ps
T75 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2787078181 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:31 PM PDT 24 534438494 ps
T831 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.315833281 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:31 PM PDT 24 667293151 ps
T832 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3480656199 Aug 04 05:30:22 PM PDT 24 Aug 04 05:30:23 PM PDT 24 541874514 ps
T332 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2166890924 Aug 04 05:30:30 PM PDT 24 Aug 04 05:30:34 PM PDT 24 4201101609 ps
T833 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3634673830 Aug 04 05:30:48 PM PDT 24 Aug 04 05:30:49 PM PDT 24 414318518 ps
T117 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1182243482 Aug 04 05:30:20 PM PDT 24 Aug 04 05:30:25 PM PDT 24 1089901264 ps
T834 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1034925517 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:36 PM PDT 24 364100928 ps
T835 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3161323103 Aug 04 05:30:40 PM PDT 24 Aug 04 05:30:41 PM PDT 24 419482062 ps
T836 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2870925597 Aug 04 05:30:34 PM PDT 24 Aug 04 05:30:38 PM PDT 24 4311130922 ps
T837 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1587593609 Aug 04 05:30:38 PM PDT 24 Aug 04 05:30:39 PM PDT 24 287549521 ps
T838 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2051977045 Aug 04 05:30:44 PM PDT 24 Aug 04 05:30:46 PM PDT 24 470018112 ps
T839 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2032551896 Aug 04 05:30:26 PM PDT 24 Aug 04 05:30:28 PM PDT 24 527687973 ps
T840 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2973245473 Aug 04 05:30:34 PM PDT 24 Aug 04 05:30:37 PM PDT 24 4374974202 ps
T841 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3803213014 Aug 04 05:30:40 PM PDT 24 Aug 04 05:30:42 PM PDT 24 510920339 ps
T842 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1915182820 Aug 04 05:30:17 PM PDT 24 Aug 04 05:30:19 PM PDT 24 501539870 ps
T843 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.99492061 Aug 04 05:30:26 PM PDT 24 Aug 04 05:30:27 PM PDT 24 562706844 ps
T844 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.423653482 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:45 PM PDT 24 4346174911 ps
T845 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2259290889 Aug 04 05:30:21 PM PDT 24 Aug 04 05:30:22 PM PDT 24 349239181 ps
T846 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1176141155 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:34 PM PDT 24 760243689 ps
T847 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1875899875 Aug 04 05:30:30 PM PDT 24 Aug 04 05:30:31 PM PDT 24 416206814 ps
T848 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3529822106 Aug 04 05:30:23 PM PDT 24 Aug 04 05:30:25 PM PDT 24 483518686 ps
T849 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.30632692 Aug 04 05:30:32 PM PDT 24 Aug 04 05:30:35 PM PDT 24 432134733 ps
T850 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.643246654 Aug 04 05:30:52 PM PDT 24 Aug 04 05:31:12 PM PDT 24 7900061102 ps
T851 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3755962850 Aug 04 05:30:26 PM PDT 24 Aug 04 05:30:27 PM PDT 24 347965469 ps
T852 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2791546710 Aug 04 05:30:23 PM PDT 24 Aug 04 05:30:25 PM PDT 24 607803902 ps
T853 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3397195827 Aug 04 05:30:21 PM PDT 24 Aug 04 05:30:22 PM PDT 24 502679243 ps
T854 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1292170498 Aug 04 05:30:34 PM PDT 24 Aug 04 05:30:36 PM PDT 24 2082965819 ps
T855 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1526367787 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:35 PM PDT 24 476072537 ps
T856 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.983050713 Aug 04 05:30:28 PM PDT 24 Aug 04 05:30:30 PM PDT 24 488828412 ps
T857 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.521857215 Aug 04 05:31:06 PM PDT 24 Aug 04 05:31:07 PM PDT 24 325645621 ps
T858 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.634364724 Aug 04 05:30:43 PM PDT 24 Aug 04 05:30:44 PM PDT 24 400442494 ps
T859 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3819065892 Aug 04 05:30:38 PM PDT 24 Aug 04 05:30:39 PM PDT 24 425646144 ps
T860 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2336124884 Aug 04 05:30:22 PM PDT 24 Aug 04 05:30:25 PM PDT 24 393450517 ps
T861 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.877511276 Aug 04 05:30:23 PM PDT 24 Aug 04 05:30:35 PM PDT 24 7936348521 ps
T862 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2420014715 Aug 04 05:30:36 PM PDT 24 Aug 04 05:30:37 PM PDT 24 359476524 ps
T863 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1924098908 Aug 04 05:30:24 PM PDT 24 Aug 04 05:30:27 PM PDT 24 4410981298 ps
T864 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.976443809 Aug 04 05:30:25 PM PDT 24 Aug 04 05:30:27 PM PDT 24 385665983 ps
T865 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4228053204 Aug 04 05:30:18 PM PDT 24 Aug 04 05:30:20 PM PDT 24 2443477976 ps
T866 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1278910843 Aug 04 05:30:44 PM PDT 24 Aug 04 05:30:49 PM PDT 24 4796440028 ps
T867 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2899130439 Aug 04 05:30:42 PM PDT 24 Aug 04 05:30:44 PM PDT 24 324855295 ps
T868 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3928990173 Aug 04 05:30:27 PM PDT 24 Aug 04 05:30:30 PM PDT 24 2299803394 ps
T330 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1371874430 Aug 04 05:30:36 PM PDT 24 Aug 04 05:30:43 PM PDT 24 8382825886 ps
T869 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.579990384 Aug 04 05:30:41 PM PDT 24 Aug 04 05:30:43 PM PDT 24 515540200 ps
T79 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1487706662 Aug 04 05:30:30 PM PDT 24 Aug 04 05:30:33 PM PDT 24 426190139 ps
T118 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.801305978 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:35 PM PDT 24 577612258 ps
T870 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3076813004 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:35 PM PDT 24 478776044 ps
T871 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1169043230 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:36 PM PDT 24 453003007 ps
T872 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3504572378 Aug 04 05:30:39 PM PDT 24 Aug 04 05:30:42 PM PDT 24 735992090 ps
T873 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1515055036 Aug 04 05:30:24 PM PDT 24 Aug 04 05:30:25 PM PDT 24 397412999 ps
T874 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2322383639 Aug 04 05:30:54 PM PDT 24 Aug 04 05:31:04 PM PDT 24 3939265995 ps
T119 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.748621787 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:33 PM PDT 24 447111787 ps
T875 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2470396459 Aug 04 05:30:39 PM PDT 24 Aug 04 05:30:40 PM PDT 24 351402157 ps
T876 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.522182120 Aug 04 05:30:57 PM PDT 24 Aug 04 05:31:00 PM PDT 24 720674147 ps
T333 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.676286040 Aug 04 05:30:24 PM PDT 24 Aug 04 05:30:29 PM PDT 24 8281336040 ps
T877 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1002330845 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:32 PM PDT 24 2108556251 ps
T878 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.222466808 Aug 04 05:30:46 PM PDT 24 Aug 04 05:30:52 PM PDT 24 395790294 ps
T879 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2848351667 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:36 PM PDT 24 8482737818 ps
T880 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1101804036 Aug 04 05:30:32 PM PDT 24 Aug 04 05:30:34 PM PDT 24 492273319 ps
T881 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2151989877 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:32 PM PDT 24 654891551 ps
T882 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1262339843 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:34 PM PDT 24 1036591361 ps
T883 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1386619598 Aug 04 05:30:43 PM PDT 24 Aug 04 05:31:05 PM PDT 24 4329866058 ps
T884 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.133569452 Aug 04 05:30:39 PM PDT 24 Aug 04 05:30:44 PM PDT 24 5527420577 ps
T885 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.788490681 Aug 04 05:30:21 PM PDT 24 Aug 04 05:30:23 PM PDT 24 748779767 ps
T886 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2568803321 Aug 04 05:30:22 PM PDT 24 Aug 04 05:30:23 PM PDT 24 474563352 ps
T331 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.715181801 Aug 04 05:30:23 PM PDT 24 Aug 04 05:30:25 PM PDT 24 5498742716 ps
T887 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.640245646 Aug 04 05:30:59 PM PDT 24 Aug 04 05:31:01 PM PDT 24 414917106 ps
T888 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.740740507 Aug 04 05:30:21 PM PDT 24 Aug 04 05:30:23 PM PDT 24 4943416400 ps
T889 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1443766598 Aug 04 05:30:24 PM PDT 24 Aug 04 05:30:34 PM PDT 24 5514240894 ps
T890 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2038097200 Aug 04 05:30:33 PM PDT 24 Aug 04 05:30:35 PM PDT 24 648801637 ps
T891 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.600354888 Aug 04 05:30:20 PM PDT 24 Aug 04 05:30:22 PM PDT 24 467769725 ps
T892 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2428901138 Aug 04 05:30:22 PM PDT 24 Aug 04 05:30:26 PM PDT 24 582260626 ps
T893 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.508934827 Aug 04 05:30:32 PM PDT 24 Aug 04 05:30:55 PM PDT 24 8483351991 ps
T894 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1009811502 Aug 04 05:30:43 PM PDT 24 Aug 04 05:30:44 PM PDT 24 398992162 ps
T895 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2100530842 Aug 04 05:30:38 PM PDT 24 Aug 04 05:30:40 PM PDT 24 463097887 ps
T896 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4258391053 Aug 04 05:30:24 PM PDT 24 Aug 04 05:30:33 PM PDT 24 26016467886 ps
T120 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2061144686 Aug 04 05:30:30 PM PDT 24 Aug 04 05:30:31 PM PDT 24 491278287 ps
T897 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3208263900 Aug 04 05:30:30 PM PDT 24 Aug 04 05:30:32 PM PDT 24 471630485 ps
T898 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.412198420 Aug 04 05:30:37 PM PDT 24 Aug 04 05:30:39 PM PDT 24 530795823 ps
T899 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.586838953 Aug 04 05:30:35 PM PDT 24 Aug 04 05:30:36 PM PDT 24 489636974 ps
T900 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4072945546 Aug 04 05:30:21 PM PDT 24 Aug 04 05:30:23 PM PDT 24 410651550 ps
T901 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.140669377 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:35 PM PDT 24 4896282130 ps
T902 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3777010438 Aug 04 05:30:30 PM PDT 24 Aug 04 05:30:31 PM PDT 24 620282449 ps
T903 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3671426818 Aug 04 05:30:36 PM PDT 24 Aug 04 05:30:37 PM PDT 24 432762642 ps
T904 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2052865411 Aug 04 05:30:27 PM PDT 24 Aug 04 05:30:30 PM PDT 24 4203016688 ps
T905 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1171994379 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:33 PM PDT 24 590036684 ps
T906 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2592869358 Aug 04 05:30:27 PM PDT 24 Aug 04 05:30:29 PM PDT 24 378315118 ps
T907 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3456685552 Aug 04 05:30:29 PM PDT 24 Aug 04 05:30:31 PM PDT 24 404411343 ps
T908 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1948593373 Aug 04 05:30:45 PM PDT 24 Aug 04 05:30:47 PM PDT 24 313712554 ps
T909 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2264844667 Aug 04 05:30:53 PM PDT 24 Aug 04 05:30:54 PM PDT 24 479069782 ps
T910 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.656420817 Aug 04 05:31:00 PM PDT 24 Aug 04 05:31:01 PM PDT 24 311690524 ps
T911 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3939114880 Aug 04 05:30:22 PM PDT 24 Aug 04 05:30:25 PM PDT 24 957343758 ps
T912 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3015349755 Aug 04 05:30:26 PM PDT 24 Aug 04 05:30:27 PM PDT 24 403829579 ps
T913 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4039126309 Aug 04 05:30:27 PM PDT 24 Aug 04 05:30:31 PM PDT 24 647445909 ps
T914 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3831789076 Aug 04 05:30:30 PM PDT 24 Aug 04 05:30:31 PM PDT 24 414752748 ps
T121 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4222546748 Aug 04 05:30:42 PM PDT 24 Aug 04 05:30:44 PM PDT 24 524647778 ps
T915 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3126520844 Aug 04 05:30:31 PM PDT 24 Aug 04 05:30:34 PM PDT 24 1323419009 ps
T916 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2564960919 Aug 04 05:30:28 PM PDT 24 Aug 04 05:30:35 PM PDT 24 2533575804 ps
T917 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4004430125 Aug 04 05:30:21 PM PDT 24 Aug 04 05:30:55 PM PDT 24 25360585157 ps
T918 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1677219904 Aug 04 05:30:41 PM PDT 24 Aug 04 05:30:42 PM PDT 24 290611712 ps

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1449731034
Short name T8
Test name
Test status
Simulation time 546426927011 ps
CPU time 320.67 seconds
Started Aug 04 05:03:04 PM PDT 24
Finished Aug 04 05:08:25 PM PDT 24
Peak memory 201380 kb
Host smart-b1700ca4-3319-4cca-b70a-dd6e8970742d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449731034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1449731034
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3906065383
Short name T13
Test name
Test status
Simulation time 169842488392 ps
CPU time 393.09 seconds
Started Aug 04 04:58:21 PM PDT 24
Finished Aug 04 05:04:54 PM PDT 24
Peak memory 210080 kb
Host smart-9fee08fd-399a-4811-9b61-f4d34ef27af4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906065383 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3906065383
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.829883415
Short name T48
Test name
Test status
Simulation time 492263258426 ps
CPU time 231.06 seconds
Started Aug 04 05:04:41 PM PDT 24
Finished Aug 04 05:08:32 PM PDT 24
Peak memory 201408 kb
Host smart-3ffa5dfc-cb39-44d2-ae0d-1f5c3b1fb402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829883415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.829883415
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.239205402
Short name T152
Test name
Test status
Simulation time 551294762846 ps
CPU time 466.39 seconds
Started Aug 04 04:58:59 PM PDT 24
Finished Aug 04 05:06:46 PM PDT 24
Peak memory 201380 kb
Host smart-92be6212-0254-43c3-8a7f-f1ec39624064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239205402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
239205402
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3924413201
Short name T33
Test name
Test status
Simulation time 47369118671 ps
CPU time 120.9 seconds
Started Aug 04 04:58:07 PM PDT 24
Finished Aug 04 05:00:08 PM PDT 24
Peak memory 210192 kb
Host smart-4f7ade11-ab9f-4539-8a10-12b7b0afd5d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924413201 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3924413201
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3899807604
Short name T136
Test name
Test status
Simulation time 497284386866 ps
CPU time 142.51 seconds
Started Aug 04 04:57:52 PM PDT 24
Finished Aug 04 05:00:14 PM PDT 24
Peak memory 201296 kb
Host smart-17513b1f-bf11-493c-bfa6-0fb4ccf9f0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899807604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3899807604
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.325080910
Short name T144
Test name
Test status
Simulation time 540569930288 ps
CPU time 946.73 seconds
Started Aug 04 04:58:11 PM PDT 24
Finished Aug 04 05:13:58 PM PDT 24
Peak memory 201388 kb
Host smart-07e96539-44a4-4c47-b3e7-c8c6913ad434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325080910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.325080910
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3171265220
Short name T39
Test name
Test status
Simulation time 527137733618 ps
CPU time 616.15 seconds
Started Aug 04 04:57:59 PM PDT 24
Finished Aug 04 05:08:15 PM PDT 24
Peak memory 201400 kb
Host smart-c83f3b57-940c-405e-947b-e1d04fb1a7d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171265220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3171265220
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3287844635
Short name T18
Test name
Test status
Simulation time 130465718649 ps
CPU time 265.47 seconds
Started Aug 04 04:58:39 PM PDT 24
Finished Aug 04 05:03:04 PM PDT 24
Peak memory 217756 kb
Host smart-8540bd20-9211-4a96-a146-aa81f58d346b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287844635 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3287844635
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.786319535
Short name T177
Test name
Test status
Simulation time 783943330835 ps
CPU time 2197.14 seconds
Started Aug 04 05:01:04 PM PDT 24
Finished Aug 04 05:37:42 PM PDT 24
Peak memory 209916 kb
Host smart-16e89160-2d84-4ca2-81d5-14aec01a211f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786319535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
786319535
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.323788944
Short name T145
Test name
Test status
Simulation time 492340279385 ps
CPU time 202.16 seconds
Started Aug 04 04:58:08 PM PDT 24
Finished Aug 04 05:01:30 PM PDT 24
Peak memory 201296 kb
Host smart-1e8e1fd1-f0e3-4961-8205-a9c278580421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323788944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.323788944
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.39546228
Short name T66
Test name
Test status
Simulation time 4488251415 ps
CPU time 4.15 seconds
Started Aug 04 04:57:52 PM PDT 24
Finished Aug 04 04:57:57 PM PDT 24
Peak memory 217008 kb
Host smart-a9b0ca0f-33fc-4f73-aabd-f55b7dbac730
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39546228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.39546228
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2520652233
Short name T197
Test name
Test status
Simulation time 487316869583 ps
CPU time 525.66 seconds
Started Aug 04 05:04:41 PM PDT 24
Finished Aug 04 05:13:27 PM PDT 24
Peak memory 201344 kb
Host smart-c4d24d20-219a-4bbf-8131-dbb1723dc9ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520652233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2520652233
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3827625453
Short name T70
Test name
Test status
Simulation time 498517406 ps
CPU time 2.67 seconds
Started Aug 04 05:30:28 PM PDT 24
Finished Aug 04 05:30:30 PM PDT 24
Peak memory 201688 kb
Host smart-196eac10-099c-40c5-bdc3-f68e426f85f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827625453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3827625453
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1403397021
Short name T210
Test name
Test status
Simulation time 375882798895 ps
CPU time 400.68 seconds
Started Aug 04 04:58:04 PM PDT 24
Finished Aug 04 05:04:45 PM PDT 24
Peak memory 201304 kb
Host smart-bb92a008-76ea-48f1-85c9-667830931521
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403397021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1403397021
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1190738166
Short name T98
Test name
Test status
Simulation time 496460448795 ps
CPU time 1217.09 seconds
Started Aug 04 04:57:57 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201384 kb
Host smart-b93f7ade-15ca-43b2-a5eb-4a8da7d17238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190738166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1190738166
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4191393210
Short name T55
Test name
Test status
Simulation time 2890143009 ps
CPU time 7.17 seconds
Started Aug 04 05:30:19 PM PDT 24
Finished Aug 04 05:30:27 PM PDT 24
Peak memory 201552 kb
Host smart-0633172e-e66d-48da-abec-e0545738f048
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191393210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4191393210
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.155722258
Short name T36
Test name
Test status
Simulation time 94302341042 ps
CPU time 149.55 seconds
Started Aug 04 04:59:29 PM PDT 24
Finished Aug 04 05:01:58 PM PDT 24
Peak memory 217612 kb
Host smart-16fc54bd-fce9-478e-ad9f-c75d42943fb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155722258 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.155722258
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3530826967
Short name T28
Test name
Test status
Simulation time 374517008008 ps
CPU time 414.11 seconds
Started Aug 04 04:58:36 PM PDT 24
Finished Aug 04 05:05:31 PM PDT 24
Peak memory 201304 kb
Host smart-b31ffa4d-a48e-45cf-a2cd-a51de617519d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530826967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3530826967
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2411072704
Short name T59
Test name
Test status
Simulation time 587196127186 ps
CPU time 1033.61 seconds
Started Aug 04 05:02:20 PM PDT 24
Finished Aug 04 05:19:33 PM PDT 24
Peak memory 201436 kb
Host smart-e191b2c8-8b18-4d85-9e98-36c5c0651873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411072704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2411072704
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1604007647
Short name T143
Test name
Test status
Simulation time 503423854520 ps
CPU time 101.04 seconds
Started Aug 04 04:59:54 PM PDT 24
Finished Aug 04 05:01:35 PM PDT 24
Peak memory 201396 kb
Host smart-aec7b6fc-2636-4cfb-b1fa-88a04c115d3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604007647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1604007647
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2951128044
Short name T245
Test name
Test status
Simulation time 508029225159 ps
CPU time 962.91 seconds
Started Aug 04 05:04:03 PM PDT 24
Finished Aug 04 05:20:06 PM PDT 24
Peak memory 201284 kb
Host smart-ebc78f09-260a-4dfa-9077-853e6f43ee2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951128044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2951128044
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1419827847
Short name T278
Test name
Test status
Simulation time 511807833696 ps
CPU time 606.15 seconds
Started Aug 04 05:05:04 PM PDT 24
Finished Aug 04 05:15:10 PM PDT 24
Peak memory 201364 kb
Host smart-57020b4f-8340-407f-8a95-4623880967a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419827847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1419827847
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.928290092
Short name T60
Test name
Test status
Simulation time 538196431817 ps
CPU time 111.63 seconds
Started Aug 04 04:59:30 PM PDT 24
Finished Aug 04 05:01:22 PM PDT 24
Peak memory 201384 kb
Host smart-e0c88e2a-f050-4a4e-99ec-b1216d75ad38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928290092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
928290092
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.907061466
Short name T40
Test name
Test status
Simulation time 336910490449 ps
CPU time 362.59 seconds
Started Aug 04 04:59:53 PM PDT 24
Finished Aug 04 05:05:56 PM PDT 24
Peak memory 201372 kb
Host smart-a595dac4-1182-41f0-be4b-f2183b7fad9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907061466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
907061466
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.487212845
Short name T202
Test name
Test status
Simulation time 501249474473 ps
CPU time 147.85 seconds
Started Aug 04 05:01:28 PM PDT 24
Finished Aug 04 05:03:56 PM PDT 24
Peak memory 201448 kb
Host smart-a6252237-fc99-40e0-b878-1c155ab69856
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487212845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.487212845
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2383442084
Short name T359
Test name
Test status
Simulation time 470678350 ps
CPU time 0.92 seconds
Started Aug 04 04:57:50 PM PDT 24
Finished Aug 04 04:57:51 PM PDT 24
Peak memory 201184 kb
Host smart-4f037bbe-cd5b-417b-abe6-550c47ae5ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383442084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2383442084
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2137202215
Short name T30
Test name
Test status
Simulation time 579592582732 ps
CPU time 103.18 seconds
Started Aug 04 05:04:23 PM PDT 24
Finished Aug 04 05:06:07 PM PDT 24
Peak memory 201376 kb
Host smart-ba98dd2a-3d42-4927-b8b3-45b1f10933c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137202215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2137202215
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3824502292
Short name T229
Test name
Test status
Simulation time 325653539205 ps
CPU time 204.88 seconds
Started Aug 04 04:58:57 PM PDT 24
Finished Aug 04 05:02:22 PM PDT 24
Peak memory 201408 kb
Host smart-b98834a0-7e50-432a-8522-d08ae463b5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824502292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3824502292
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3458507829
Short name T15
Test name
Test status
Simulation time 362300152720 ps
CPU time 335.19 seconds
Started Aug 04 05:03:02 PM PDT 24
Finished Aug 04 05:08:37 PM PDT 24
Peak memory 210000 kb
Host smart-576a2d28-0094-41f1-901e-353235852258
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458507829 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3458507829
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2613280998
Short name T275
Test name
Test status
Simulation time 492916982531 ps
CPU time 1081.16 seconds
Started Aug 04 05:01:23 PM PDT 24
Finished Aug 04 05:19:25 PM PDT 24
Peak memory 201404 kb
Host smart-6d3a60f4-0e5a-444a-9839-07b2a5b92f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613280998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2613280998
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3612203027
Short name T34
Test name
Test status
Simulation time 117113033538 ps
CPU time 275.92 seconds
Started Aug 04 05:02:30 PM PDT 24
Finished Aug 04 05:07:06 PM PDT 24
Peak memory 211092 kb
Host smart-3b032ad0-dec4-4b34-9dae-e708ec7b4326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612203027 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3612203027
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.87056047
Short name T65
Test name
Test status
Simulation time 4456940584 ps
CPU time 6.54 seconds
Started Aug 04 05:30:28 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201676 kb
Host smart-f9039ab7-390b-468c-9708-cd62186ea69f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87056047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg
_err.87056047
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2995920804
Short name T225
Test name
Test status
Simulation time 630647416913 ps
CPU time 387.1 seconds
Started Aug 04 04:57:49 PM PDT 24
Finished Aug 04 05:04:17 PM PDT 24
Peak memory 201344 kb
Host smart-596e6a3e-6115-4e82-927f-1a2185ab4209
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995920804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2995920804
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1070839588
Short name T253
Test name
Test status
Simulation time 505545843734 ps
CPU time 256.33 seconds
Started Aug 04 05:02:33 PM PDT 24
Finished Aug 04 05:06:49 PM PDT 24
Peak memory 201464 kb
Host smart-e6c8111a-2f3e-4675-bc05-f8ab8025d258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070839588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1070839588
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1716708164
Short name T205
Test name
Test status
Simulation time 521641878471 ps
CPU time 1101.1 seconds
Started Aug 04 05:03:10 PM PDT 24
Finished Aug 04 05:21:31 PM PDT 24
Peak memory 201376 kb
Host smart-d77eedd0-b9ed-46da-8235-579c57d623cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716708164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1716708164
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.469627247
Short name T178
Test name
Test status
Simulation time 645648020047 ps
CPU time 798.74 seconds
Started Aug 04 05:03:51 PM PDT 24
Finished Aug 04 05:17:10 PM PDT 24
Peak memory 201764 kb
Host smart-c5d696a2-c8c8-46a6-8045-70d0ee72e1a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469627247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
469627247
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.329293704
Short name T139
Test name
Test status
Simulation time 492938872139 ps
CPU time 267.02 seconds
Started Aug 04 04:58:07 PM PDT 24
Finished Aug 04 05:02:34 PM PDT 24
Peak memory 201304 kb
Host smart-1fcfb6bb-d842-4da3-abe9-ad484fc3e868
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329293704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.329293704
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2059476400
Short name T244
Test name
Test status
Simulation time 164838595430 ps
CPU time 187 seconds
Started Aug 04 04:58:10 PM PDT 24
Finished Aug 04 05:01:17 PM PDT 24
Peak memory 201384 kb
Host smart-43be4767-6d6f-4efd-aaba-daf6edd29626
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059476400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2059476400
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.260023744
Short name T7
Test name
Test status
Simulation time 164428189267 ps
CPU time 31.71 seconds
Started Aug 04 05:03:25 PM PDT 24
Finished Aug 04 05:03:56 PM PDT 24
Peak memory 201376 kb
Host smart-4dd6e6d6-ee21-4775-97ed-e0b325c9d5df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=260023744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.260023744
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3351333031
Short name T258
Test name
Test status
Simulation time 241831372389 ps
CPU time 379.74 seconds
Started Aug 04 05:04:40 PM PDT 24
Finished Aug 04 05:11:00 PM PDT 24
Peak memory 210072 kb
Host smart-246a5cd0-eb8a-498e-a612-fc2ad440eec3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351333031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3351333031
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3600072427
Short name T234
Test name
Test status
Simulation time 490329255731 ps
CPU time 218.12 seconds
Started Aug 04 05:01:12 PM PDT 24
Finished Aug 04 05:04:50 PM PDT 24
Peak memory 201408 kb
Host smart-c7017a9b-c917-4459-a2b7-368e276c9a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600072427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3600072427
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.562494945
Short name T267
Test name
Test status
Simulation time 529379065700 ps
CPU time 694.68 seconds
Started Aug 04 05:03:34 PM PDT 24
Finished Aug 04 05:15:09 PM PDT 24
Peak memory 201792 kb
Host smart-8a8f8b98-ea3d-41e9-a1b2-82543e08b855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562494945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
562494945
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2834674313
Short name T282
Test name
Test status
Simulation time 504899667293 ps
CPU time 1085.6 seconds
Started Aug 04 04:58:17 PM PDT 24
Finished Aug 04 05:16:23 PM PDT 24
Peak memory 201360 kb
Host smart-a451a8af-03f5-45fe-b942-b97062e3b755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834674313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2834674313
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2714170618
Short name T233
Test name
Test status
Simulation time 192014821569 ps
CPU time 390.6 seconds
Started Aug 04 05:00:24 PM PDT 24
Finished Aug 04 05:06:54 PM PDT 24
Peak memory 201336 kb
Host smart-ef10cc47-95c9-4576-997c-eca66dc786d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714170618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2714170618
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2875547201
Short name T195
Test name
Test status
Simulation time 562623037648 ps
CPU time 1449.86 seconds
Started Aug 04 05:04:37 PM PDT 24
Finished Aug 04 05:28:47 PM PDT 24
Peak memory 210044 kb
Host smart-bd1e852b-2cb9-40cc-aa9d-05af0362d3f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875547201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2875547201
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3800077795
Short name T211
Test name
Test status
Simulation time 489549244988 ps
CPU time 1211.84 seconds
Started Aug 04 04:58:20 PM PDT 24
Finished Aug 04 05:18:33 PM PDT 24
Peak memory 201388 kb
Host smart-46c673b8-1f0e-476c-85bf-0d4c3d99cbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800077795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3800077795
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3873566075
Short name T56
Test name
Test status
Simulation time 5408426838 ps
CPU time 2.6 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201560 kb
Host smart-299a541a-7b45-460f-9242-6142de99933d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873566075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3873566075
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2798052102
Short name T232
Test name
Test status
Simulation time 558631214134 ps
CPU time 347.23 seconds
Started Aug 04 05:03:33 PM PDT 24
Finished Aug 04 05:09:20 PM PDT 24
Peak memory 210108 kb
Host smart-7878a2f7-b20f-4ab0-98fd-df8d51816d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798052102 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2798052102
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1294217658
Short name T16
Test name
Test status
Simulation time 651916576981 ps
CPU time 791.69 seconds
Started Aug 04 05:04:46 PM PDT 24
Finished Aug 04 05:17:58 PM PDT 24
Peak memory 210120 kb
Host smart-7859ca6f-6d77-4714-84a6-deae01617d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294217658 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1294217658
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.522182120
Short name T876
Test name
Test status
Simulation time 720674147 ps
CPU time 2.56 seconds
Started Aug 04 05:30:57 PM PDT 24
Finished Aug 04 05:31:00 PM PDT 24
Peak memory 201632 kb
Host smart-c9743a2f-0a16-4da7-ad42-e860b2a9b821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522182120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.522182120
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2399066493
Short name T309
Test name
Test status
Simulation time 524567647253 ps
CPU time 348.22 seconds
Started Aug 04 04:59:11 PM PDT 24
Finished Aug 04 05:04:59 PM PDT 24
Peak memory 201412 kb
Host smart-3ae70aed-0ca5-4d2b-9f37-cf0c7bd0a7b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399066493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2399066493
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.136551181
Short name T224
Test name
Test status
Simulation time 515546409037 ps
CPU time 1087.73 seconds
Started Aug 04 05:00:42 PM PDT 24
Finished Aug 04 05:18:50 PM PDT 24
Peak memory 201376 kb
Host smart-2f542ab6-1e2c-4d12-8dc6-6c2f1977a6aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136551181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.136551181
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4138428479
Short name T167
Test name
Test status
Simulation time 334087168773 ps
CPU time 155.85 seconds
Started Aug 04 05:04:17 PM PDT 24
Finished Aug 04 05:06:53 PM PDT 24
Peak memory 201436 kb
Host smart-8a876204-8e6b-4011-8742-3ad178a8412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138428479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4138428479
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1478937092
Short name T162
Test name
Test status
Simulation time 349137173401 ps
CPU time 60.81 seconds
Started Aug 04 04:57:38 PM PDT 24
Finished Aug 04 04:58:39 PM PDT 24
Peak memory 201292 kb
Host smart-90ab5f6e-172b-4eca-87c2-0cccc029c2bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478937092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1478937092
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3697514823
Short name T137
Test name
Test status
Simulation time 167323215216 ps
CPU time 114.25 seconds
Started Aug 04 04:58:39 PM PDT 24
Finished Aug 04 05:00:34 PM PDT 24
Peak memory 201444 kb
Host smart-986b11c3-dfe2-437e-a78e-8c1b0ed610d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697514823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3697514823
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.537642260
Short name T287
Test name
Test status
Simulation time 553281826733 ps
CPU time 1361.14 seconds
Started Aug 04 05:02:15 PM PDT 24
Finished Aug 04 05:24:56 PM PDT 24
Peak memory 201328 kb
Host smart-099070fc-ebf7-4d47-9c41-f95b08199795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537642260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.537642260
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1025665333
Short name T166
Test name
Test status
Simulation time 336246873959 ps
CPU time 212.86 seconds
Started Aug 04 05:02:34 PM PDT 24
Finished Aug 04 05:06:07 PM PDT 24
Peak memory 201340 kb
Host smart-142bd724-04c6-4d2b-91d5-5b81c8848906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025665333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1025665333
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2169865418
Short name T252
Test name
Test status
Simulation time 492739442223 ps
CPU time 1157.25 seconds
Started Aug 04 05:04:59 PM PDT 24
Finished Aug 04 05:24:16 PM PDT 24
Peak memory 201388 kb
Host smart-c3a4223c-1c48-48ee-80be-524abdd3b75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169865418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2169865418
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2544649734
Short name T323
Test name
Test status
Simulation time 26380536385 ps
CPU time 60.14 seconds
Started Aug 04 04:57:41 PM PDT 24
Finished Aug 04 04:58:41 PM PDT 24
Peak memory 209764 kb
Host smart-e1011a21-3947-4c66-b813-0543ebcf5ea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544649734 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2544649734
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.698165799
Short name T334
Test name
Test status
Simulation time 85552275116 ps
CPU time 442.09 seconds
Started Aug 04 04:58:44 PM PDT 24
Finished Aug 04 05:06:07 PM PDT 24
Peak memory 201792 kb
Host smart-40cab11c-222f-4b14-a8e6-aadd3af9518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698165799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.698165799
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2992436275
Short name T158
Test name
Test status
Simulation time 521097182675 ps
CPU time 1202.64 seconds
Started Aug 04 04:58:48 PM PDT 24
Finished Aug 04 05:18:51 PM PDT 24
Peak memory 201408 kb
Host smart-1a42c6c8-2ef4-4fec-84fe-710d824071b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992436275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2992436275
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.4062670888
Short name T310
Test name
Test status
Simulation time 328581287574 ps
CPU time 750.82 seconds
Started Aug 04 04:59:17 PM PDT 24
Finished Aug 04 05:11:47 PM PDT 24
Peak memory 201376 kb
Host smart-67165ccb-94c8-4c78-8392-5f92727a98a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062670888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.4062670888
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3637196002
Short name T170
Test name
Test status
Simulation time 328245673627 ps
CPU time 67.9 seconds
Started Aug 04 05:01:19 PM PDT 24
Finished Aug 04 05:02:28 PM PDT 24
Peak memory 201436 kb
Host smart-cee2710c-bb00-4268-8e25-5413d4f6fc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637196002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3637196002
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1520291425
Short name T38
Test name
Test status
Simulation time 490427790647 ps
CPU time 299.75 seconds
Started Aug 04 05:02:05 PM PDT 24
Finished Aug 04 05:07:05 PM PDT 24
Peak memory 201404 kb
Host smart-747fa1ef-6ad5-4d7a-8fd6-4f28ebc7acc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520291425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1520291425
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4145771301
Short name T188
Test name
Test status
Simulation time 128123004494 ps
CPU time 424.57 seconds
Started Aug 04 05:02:21 PM PDT 24
Finished Aug 04 05:09:26 PM PDT 24
Peak memory 201852 kb
Host smart-e1872ae6-3625-445b-a024-3f8e0c29e0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145771301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4145771301
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3603124336
Short name T149
Test name
Test status
Simulation time 409188936795 ps
CPU time 69.2 seconds
Started Aug 04 05:03:52 PM PDT 24
Finished Aug 04 05:05:02 PM PDT 24
Peak memory 201420 kb
Host smart-70a56251-502a-4bbe-a99d-8bcc483c9005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603124336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3603124336
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1940132574
Short name T214
Test name
Test status
Simulation time 503918346773 ps
CPU time 317.85 seconds
Started Aug 04 05:04:13 PM PDT 24
Finished Aug 04 05:09:31 PM PDT 24
Peak memory 201328 kb
Host smart-120a735d-e211-4ef2-90bd-146dfb08fde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940132574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1940132574
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1676330760
Short name T81
Test name
Test status
Simulation time 4152766707 ps
CPU time 10.32 seconds
Started Aug 04 05:30:25 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201580 kb
Host smart-baf0b860-fa9d-42dd-a9ec-334913ad5171
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676330760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1676330760
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.715181801
Short name T331
Test name
Test status
Simulation time 5498742716 ps
CPU time 2.5 seconds
Started Aug 04 05:30:23 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 201564 kb
Host smart-1c36bb3d-0a67-4b3c-93eb-7a9c720d9a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715181801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.715181801
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2166890924
Short name T332
Test name
Test status
Simulation time 4201101609 ps
CPU time 3.92 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:30:34 PM PDT 24
Peak memory 201668 kb
Host smart-76b1c0e6-7553-47a9-ad57-a83539a0d681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166890924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2166890924
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2421597396
Short name T189
Test name
Test status
Simulation time 130209332090 ps
CPU time 470.98 seconds
Started Aug 04 04:57:38 PM PDT 24
Finished Aug 04 05:05:30 PM PDT 24
Peak memory 201864 kb
Host smart-32afdb26-aa48-4c41-ab24-b961e2e0437e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421597396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2421597396
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.180777889
Short name T203
Test name
Test status
Simulation time 526083259378 ps
CPU time 1172.84 seconds
Started Aug 04 04:58:41 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 201396 kb
Host smart-18035b2d-ec03-439b-a5b5-a88d3dbfd646
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180777889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.180777889
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1624994920
Short name T335
Test name
Test status
Simulation time 77082243567 ps
CPU time 251.92 seconds
Started Aug 04 04:59:54 PM PDT 24
Finished Aug 04 05:04:06 PM PDT 24
Peak memory 201776 kb
Host smart-e7397018-6a42-4ed4-a2cc-14ff85b90457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624994920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1624994920
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2812173891
Short name T2
Test name
Test status
Simulation time 421202486424 ps
CPU time 226.71 seconds
Started Aug 04 05:00:43 PM PDT 24
Finished Aug 04 05:04:30 PM PDT 24
Peak memory 201388 kb
Host smart-3700dc41-f629-466e-82bd-fcfb0ca87491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812173891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2812173891
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1215868585
Short name T261
Test name
Test status
Simulation time 31986878763 ps
CPU time 53.98 seconds
Started Aug 04 05:00:48 PM PDT 24
Finished Aug 04 05:01:42 PM PDT 24
Peak memory 210120 kb
Host smart-ef86b3b7-6dc4-4954-995f-0cbd48e57873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215868585 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1215868585
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2887328974
Short name T268
Test name
Test status
Simulation time 182476741903 ps
CPU time 54.82 seconds
Started Aug 04 05:01:41 PM PDT 24
Finished Aug 04 05:02:36 PM PDT 24
Peak memory 201344 kb
Host smart-27ee0cb6-0f84-40f6-8b24-89692337ded4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887328974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2887328974
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1086602934
Short name T318
Test name
Test status
Simulation time 489907653772 ps
CPU time 558.1 seconds
Started Aug 04 05:01:59 PM PDT 24
Finished Aug 04 05:11:17 PM PDT 24
Peak memory 201380 kb
Host smart-6e991a77-e2bb-4af1-a769-a41c68788254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086602934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1086602934
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3863734241
Short name T320
Test name
Test status
Simulation time 343486253747 ps
CPU time 62.28 seconds
Started Aug 04 05:02:55 PM PDT 24
Finished Aug 04 05:03:57 PM PDT 24
Peak memory 201380 kb
Host smart-945fd65f-45f4-4d66-be57-44bec26cda61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863734241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3863734241
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1291894360
Short name T321
Test name
Test status
Simulation time 532028501924 ps
CPU time 1181.66 seconds
Started Aug 04 05:03:05 PM PDT 24
Finished Aug 04 05:22:47 PM PDT 24
Peak memory 201308 kb
Host smart-9e9db850-29d8-44b1-9c29-a5a0cdfdf68c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291894360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1291894360
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2625962408
Short name T298
Test name
Test status
Simulation time 482776205757 ps
CPU time 81.48 seconds
Started Aug 04 05:03:18 PM PDT 24
Finished Aug 04 05:04:39 PM PDT 24
Peak memory 201348 kb
Host smart-4ebc062e-5b39-410b-b285-905c4605bcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625962408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2625962408
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3509452767
Short name T187
Test name
Test status
Simulation time 98112026344 ps
CPU time 523.9 seconds
Started Aug 04 05:03:52 PM PDT 24
Finished Aug 04 05:12:36 PM PDT 24
Peak memory 201724 kb
Host smart-675f3af0-f8e1-451e-b627-862fa4fbddbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509452767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3509452767
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1752963014
Short name T116
Test name
Test status
Simulation time 793983021 ps
CPU time 3.89 seconds
Started Aug 04 05:30:18 PM PDT 24
Finished Aug 04 05:30:22 PM PDT 24
Peak memory 201500 kb
Host smart-0bb81610-5a32-4d7c-89c2-dea50001d97a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752963014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1752963014
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2791546710
Short name T852
Test name
Test status
Simulation time 607803902 ps
CPU time 2.03 seconds
Started Aug 04 05:30:23 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 201292 kb
Host smart-0ba6f46f-968d-4c2f-ab03-fb1b98c01481
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791546710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2791546710
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1915182820
Short name T842
Test name
Test status
Simulation time 501539870 ps
CPU time 2.04 seconds
Started Aug 04 05:30:17 PM PDT 24
Finished Aug 04 05:30:19 PM PDT 24
Peak memory 201484 kb
Host smart-21990d93-9668-48eb-b6c7-ae9504c48307
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915182820 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1915182820
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.600354888
Short name T891
Test name
Test status
Simulation time 467769725 ps
CPU time 1.03 seconds
Started Aug 04 05:30:20 PM PDT 24
Finished Aug 04 05:30:22 PM PDT 24
Peak memory 201336 kb
Host smart-6a5dc5b0-b0d7-403d-9a3f-a703e5732ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600354888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.600354888
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1884213881
Short name T803
Test name
Test status
Simulation time 319836622 ps
CPU time 1.01 seconds
Started Aug 04 05:30:17 PM PDT 24
Finished Aug 04 05:30:18 PM PDT 24
Peak memory 201288 kb
Host smart-8bd59153-e0c7-4484-a090-6a7adb9180d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884213881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1884213881
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4228053204
Short name T865
Test name
Test status
Simulation time 2443477976 ps
CPU time 2.14 seconds
Started Aug 04 05:30:18 PM PDT 24
Finished Aug 04 05:30:20 PM PDT 24
Peak memory 201356 kb
Host smart-aa75fe8f-bd0e-4c3d-95b6-6a6f9f958a46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228053204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.4228053204
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2297655134
Short name T74
Test name
Test status
Simulation time 385963576 ps
CPU time 3.72 seconds
Started Aug 04 05:30:19 PM PDT 24
Finished Aug 04 05:30:23 PM PDT 24
Peak memory 201532 kb
Host smart-56d71eae-47e9-49ef-bc13-6aeb61a3ae81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297655134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2297655134
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.740740507
Short name T888
Test name
Test status
Simulation time 4943416400 ps
CPU time 2.05 seconds
Started Aug 04 05:30:21 PM PDT 24
Finished Aug 04 05:30:23 PM PDT 24
Peak memory 201644 kb
Host smart-664cf666-6bb5-42c8-90fe-650befc6402a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740740507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.740740507
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1182243482
Short name T117
Test name
Test status
Simulation time 1089901264 ps
CPU time 4.77 seconds
Started Aug 04 05:30:20 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 201560 kb
Host smart-f8d7e2c8-26c4-4d9c-9dc2-585017c9bbce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182243482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1182243482
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4004430125
Short name T917
Test name
Test status
Simulation time 25360585157 ps
CPU time 33.41 seconds
Started Aug 04 05:30:21 PM PDT 24
Finished Aug 04 05:30:55 PM PDT 24
Peak memory 201584 kb
Host smart-857f9c0d-dec6-4e00-b689-2c2cd6e95606
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004430125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4004430125
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1039962922
Short name T824
Test name
Test status
Simulation time 873105849 ps
CPU time 1.77 seconds
Started Aug 04 05:30:21 PM PDT 24
Finished Aug 04 05:30:23 PM PDT 24
Peak memory 201348 kb
Host smart-d790a4d4-809e-4b32-af27-6d7f494aa3f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039962922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1039962922
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3397195827
Short name T853
Test name
Test status
Simulation time 502679243 ps
CPU time 1.23 seconds
Started Aug 04 05:30:21 PM PDT 24
Finished Aug 04 05:30:22 PM PDT 24
Peak memory 201420 kb
Host smart-096dc24f-a962-4a5b-a107-da597f35c87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397195827 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3397195827
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2568803321
Short name T886
Test name
Test status
Simulation time 474563352 ps
CPU time 0.98 seconds
Started Aug 04 05:30:22 PM PDT 24
Finished Aug 04 05:30:23 PM PDT 24
Peak memory 201380 kb
Host smart-4b928976-997b-4a51-a6ef-f66eb6a1b1d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568803321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2568803321
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3480656199
Short name T832
Test name
Test status
Simulation time 541874514 ps
CPU time 1.24 seconds
Started Aug 04 05:30:22 PM PDT 24
Finished Aug 04 05:30:23 PM PDT 24
Peak memory 201532 kb
Host smart-e841dc29-04d1-492d-ae31-35de1a0f0966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480656199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3480656199
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1924098908
Short name T863
Test name
Test status
Simulation time 4410981298 ps
CPU time 2.3 seconds
Started Aug 04 05:30:24 PM PDT 24
Finished Aug 04 05:30:27 PM PDT 24
Peak memory 201796 kb
Host smart-7cf4b886-d949-40cc-8e36-771e465c2e8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924098908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1924098908
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2336124884
Short name T860
Test name
Test status
Simulation time 393450517 ps
CPU time 2.93 seconds
Started Aug 04 05:30:22 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 201520 kb
Host smart-cf13702e-1706-4a91-a26a-0362481d1044
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336124884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2336124884
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1875899875
Short name T847
Test name
Test status
Simulation time 416206814 ps
CPU time 1.04 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201500 kb
Host smart-12f15670-6660-42a5-84d3-8857ed993c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875899875 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1875899875
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4222546748
Short name T121
Test name
Test status
Simulation time 524647778 ps
CPU time 1.04 seconds
Started Aug 04 05:30:42 PM PDT 24
Finished Aug 04 05:30:44 PM PDT 24
Peak memory 201348 kb
Host smart-8f451f94-bed2-484c-a0c0-c798c0d8ad46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222546748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.4222546748
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3632899019
Short name T819
Test name
Test status
Simulation time 412635356 ps
CPU time 0.79 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:30 PM PDT 24
Peak memory 201276 kb
Host smart-a3e9b9c7-fd03-4ab9-a029-0d9894e2e37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632899019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3632899019
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1466590722
Short name T72
Test name
Test status
Simulation time 688693845 ps
CPU time 1.76 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201688 kb
Host smart-36b6c707-9945-48d2-8787-59aa49cedef0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466590722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1466590722
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1338588642
Short name T61
Test name
Test status
Simulation time 4385921944 ps
CPU time 11.73 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:41 PM PDT 24
Peak memory 201620 kb
Host smart-159d6b3c-57bc-4a90-a2f9-ba92292a2b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338588642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1338588642
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2510074185
Short name T69
Test name
Test status
Simulation time 377309956 ps
CPU time 1.04 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201504 kb
Host smart-c5899257-268d-4ff2-bb37-7059c96f6aec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510074185 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2510074185
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3515717553
Short name T58
Test name
Test status
Simulation time 568748304 ps
CPU time 1.57 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:33 PM PDT 24
Peak memory 201272 kb
Host smart-188c6207-f848-4e11-8581-6b5444f87c6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515717553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3515717553
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2290504320
Short name T801
Test name
Test status
Simulation time 420794380 ps
CPU time 0.92 seconds
Started Aug 04 05:31:00 PM PDT 24
Finished Aug 04 05:31:01 PM PDT 24
Peak memory 201372 kb
Host smart-52075a11-4b08-47a0-91ef-ecf7c0459533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290504320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2290504320
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.317438212
Short name T823
Test name
Test status
Simulation time 2210735446 ps
CPU time 5.04 seconds
Started Aug 04 05:30:45 PM PDT 24
Finished Aug 04 05:30:50 PM PDT 24
Peak memory 201448 kb
Host smart-2493c6e6-ccf0-4557-b3a4-7150abbed337
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317438212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.317438212
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2322383639
Short name T874
Test name
Test status
Simulation time 3939265995 ps
CPU time 10.26 seconds
Started Aug 04 05:30:54 PM PDT 24
Finished Aug 04 05:31:04 PM PDT 24
Peak memory 201688 kb
Host smart-c7fff7f4-c2d1-4d30-b03e-a3942a10fd9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322383639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2322383639
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.315833281
Short name T831
Test name
Test status
Simulation time 667293151 ps
CPU time 1.18 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201492 kb
Host smart-153736e5-db9a-4a59-8a4f-7c5aa657417d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315833281 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.315833281
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2973868004
Short name T127
Test name
Test status
Simulation time 317656714 ps
CPU time 1.37 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:32 PM PDT 24
Peak memory 201348 kb
Host smart-17c45cc6-1f5d-4437-82cc-24d7f73af077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973868004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2973868004
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3479517666
Short name T804
Test name
Test status
Simulation time 550190922 ps
CPU time 1.01 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201364 kb
Host smart-90bad85b-7b00-432b-a060-54bdcb5eef7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479517666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3479517666
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.140669377
Short name T901
Test name
Test status
Simulation time 4896282130 ps
CPU time 4.38 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201604 kb
Host smart-8aa16313-6de2-48c3-9edb-1801d1d70abe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140669377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.140669377
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2151989877
Short name T881
Test name
Test status
Simulation time 654891551 ps
CPU time 3.45 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:32 PM PDT 24
Peak memory 217892 kb
Host smart-d6d68948-8d13-45ac-9304-70810e742a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151989877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2151989877
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2995510703
Short name T63
Test name
Test status
Simulation time 4376944552 ps
CPU time 11.68 seconds
Started Aug 04 05:30:28 PM PDT 24
Finished Aug 04 05:30:40 PM PDT 24
Peak memory 201640 kb
Host smart-b8189424-8b51-4afb-a1b1-acc70ed4ebd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995510703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2995510703
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2850835699
Short name T94
Test name
Test status
Simulation time 483247705 ps
CPU time 1.9 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:33 PM PDT 24
Peak memory 201504 kb
Host smart-69636a9a-bb3d-421a-b623-6cbe8ba8fa65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850835699 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2850835699
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3336150205
Short name T112
Test name
Test status
Simulation time 399949720 ps
CPU time 1.59 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201356 kb
Host smart-b06cc038-3792-4931-8b9e-5494df9871b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336150205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3336150205
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2841578004
Short name T818
Test name
Test status
Simulation time 519753176 ps
CPU time 1.11 seconds
Started Aug 04 05:30:58 PM PDT 24
Finished Aug 04 05:30:59 PM PDT 24
Peak memory 201372 kb
Host smart-f33a9759-e597-4b7e-bc04-b06cbd061443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841578004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2841578004
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3320475540
Short name T828
Test name
Test status
Simulation time 4378769462 ps
CPU time 10.45 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:30:41 PM PDT 24
Peak memory 201512 kb
Host smart-c64ffcef-74cb-4b0a-898b-fa2fd2571817
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320475540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3320475540
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1487706662
Short name T79
Test name
Test status
Simulation time 426190139 ps
CPU time 3.08 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:30:33 PM PDT 24
Peak memory 201604 kb
Host smart-3894a5e2-435b-48eb-9151-b86a53a53df1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487706662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1487706662
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2848351667
Short name T879
Test name
Test status
Simulation time 8482737818 ps
CPU time 5.96 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 201684 kb
Host smart-227b1228-66e4-4117-8133-b2cad7308f45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848351667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2848351667
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3203572485
Short name T110
Test name
Test status
Simulation time 517823305 ps
CPU time 2.02 seconds
Started Aug 04 05:30:34 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 201484 kb
Host smart-057ad649-8889-437f-ab6c-a188c4de869b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203572485 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3203572485
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1034925517
Short name T834
Test name
Test status
Simulation time 364100928 ps
CPU time 1.72 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 201368 kb
Host smart-2712d903-0a71-4dbc-8148-301f5e572261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034925517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1034925517
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1081072724
Short name T800
Test name
Test status
Simulation time 348653858 ps
CPU time 1.38 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:34 PM PDT 24
Peak memory 201336 kb
Host smart-ece6681f-addd-46c1-b71f-27629b1cb6d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081072724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1081072724
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2870925597
Short name T836
Test name
Test status
Simulation time 4311130922 ps
CPU time 3.86 seconds
Started Aug 04 05:30:34 PM PDT 24
Finished Aug 04 05:30:38 PM PDT 24
Peak memory 201620 kb
Host smart-1d9dce3b-3289-4ab4-8ff2-9ba6d6a84790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870925597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2870925597
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1171994379
Short name T905
Test name
Test status
Simulation time 590036684 ps
CPU time 3.16 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:33 PM PDT 24
Peak memory 201500 kb
Host smart-735e1be1-d517-4186-bf8d-4d883cae06d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171994379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1171994379
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3418835917
Short name T80
Test name
Test status
Simulation time 4390263649 ps
CPU time 10.67 seconds
Started Aug 04 05:30:40 PM PDT 24
Finished Aug 04 05:30:51 PM PDT 24
Peak memory 201644 kb
Host smart-031301f8-e188-4389-92d9-8fc8f64f53cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418835917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3418835917
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1526367787
Short name T855
Test name
Test status
Simulation time 476072537 ps
CPU time 2.15 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201456 kb
Host smart-64e1b81c-4bda-42a8-b038-4e5261e6dbac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526367787 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1526367787
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.586838953
Short name T899
Test name
Test status
Simulation time 489636974 ps
CPU time 1.22 seconds
Started Aug 04 05:30:35 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 201360 kb
Host smart-16383b22-461b-4113-b613-0cdbccb3d054
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586838953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.586838953
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3076813004
Short name T870
Test name
Test status
Simulation time 478776044 ps
CPU time 1.12 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201348 kb
Host smart-4c54ea4a-c327-46f4-b83b-85c46e44be37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076813004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3076813004
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1292170498
Short name T854
Test name
Test status
Simulation time 2082965819 ps
CPU time 2.3 seconds
Started Aug 04 05:30:34 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 201384 kb
Host smart-e987292a-8bed-4f4b-bf63-f5d92b24b950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292170498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1292170498
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.30632692
Short name T849
Test name
Test status
Simulation time 432134733 ps
CPU time 2.52 seconds
Started Aug 04 05:30:32 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201644 kb
Host smart-f36caf18-759f-4f92-b27e-9b5044ce729f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30632692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.30632692
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.508934827
Short name T893
Test name
Test status
Simulation time 8483351991 ps
CPU time 22.52 seconds
Started Aug 04 05:30:32 PM PDT 24
Finished Aug 04 05:30:55 PM PDT 24
Peak memory 201680 kb
Host smart-d09d25fc-8dd4-478f-b4da-8041c88ea7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508934827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.508934827
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2735851911
Short name T829
Test name
Test status
Simulation time 335270033 ps
CPU time 1.72 seconds
Started Aug 04 05:30:39 PM PDT 24
Finished Aug 04 05:30:41 PM PDT 24
Peak memory 201364 kb
Host smart-19ad5b60-e261-4e7e-957e-5987b2d34cf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735851911 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2735851911
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.801305978
Short name T118
Test name
Test status
Simulation time 577612258 ps
CPU time 1.23 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201376 kb
Host smart-2cc01fa2-cfd6-4487-a6ee-1004bb9cbe2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801305978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.801305978
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3457086182
Short name T808
Test name
Test status
Simulation time 523595067 ps
CPU time 1.61 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 201272 kb
Host smart-3bef25aa-005c-4d91-ac91-1c0883565837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457086182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3457086182
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.133569452
Short name T884
Test name
Test status
Simulation time 5527420577 ps
CPU time 4.59 seconds
Started Aug 04 05:30:39 PM PDT 24
Finished Aug 04 05:30:44 PM PDT 24
Peak memory 201476 kb
Host smart-38a06890-2b83-411a-b4db-757a7f607606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133569452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.133569452
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1169043230
Short name T871
Test name
Test status
Simulation time 453003007 ps
CPU time 2.48 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 209832 kb
Host smart-71978b86-be7e-4c99-92d3-568ec061905c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169043230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1169043230
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.827998437
Short name T827
Test name
Test status
Simulation time 7998445824 ps
CPU time 22.28 seconds
Started Aug 04 05:30:35 PM PDT 24
Finished Aug 04 05:30:57 PM PDT 24
Peak memory 201664 kb
Host smart-3e13b572-ddb8-47b9-b2b0-90c3bfd3ab35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827998437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.827998437
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2877566082
Short name T821
Test name
Test status
Simulation time 507441506 ps
CPU time 1.95 seconds
Started Aug 04 05:30:35 PM PDT 24
Finished Aug 04 05:30:37 PM PDT 24
Peak memory 201492 kb
Host smart-27035043-2c57-4b59-ba86-8ccf9d0012f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877566082 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2877566082
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2078282677
Short name T123
Test name
Test status
Simulation time 438288752 ps
CPU time 1.23 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201268 kb
Host smart-c9644982-2f86-4a3c-80da-bc52148333a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078282677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2078282677
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1101804036
Short name T880
Test name
Test status
Simulation time 492273319 ps
CPU time 1.18 seconds
Started Aug 04 05:30:32 PM PDT 24
Finished Aug 04 05:30:34 PM PDT 24
Peak memory 201348 kb
Host smart-981b4365-7f64-4991-aec7-5f289a359e3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101804036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1101804036
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2973245473
Short name T840
Test name
Test status
Simulation time 4374974202 ps
CPU time 2.98 seconds
Started Aug 04 05:30:34 PM PDT 24
Finished Aug 04 05:30:37 PM PDT 24
Peak memory 201552 kb
Host smart-d1edb8e7-7a13-43b8-aaee-f07ea0c2818b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973245473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2973245473
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2038097200
Short name T890
Test name
Test status
Simulation time 648801637 ps
CPU time 1.97 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201684 kb
Host smart-1af92648-b200-4548-a392-6910bf2efe16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038097200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2038097200
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.423653482
Short name T844
Test name
Test status
Simulation time 4346174911 ps
CPU time 11.97 seconds
Started Aug 04 05:30:33 PM PDT 24
Finished Aug 04 05:30:45 PM PDT 24
Peak memory 201652 kb
Host smart-39d911b6-869e-4f6d-8278-47fe4adeee60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423653482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.423653482
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2081923661
Short name T71
Test name
Test status
Simulation time 559418080 ps
CPU time 1.28 seconds
Started Aug 04 05:30:40 PM PDT 24
Finished Aug 04 05:30:41 PM PDT 24
Peak memory 201476 kb
Host smart-0703e836-bf21-432d-becf-35ed1c516573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081923661 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2081923661
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1948593373
Short name T908
Test name
Test status
Simulation time 313712554 ps
CPU time 1.38 seconds
Started Aug 04 05:30:45 PM PDT 24
Finished Aug 04 05:30:47 PM PDT 24
Peak memory 201276 kb
Host smart-df76ccdd-4615-4e26-8233-f7639438a2c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948593373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1948593373
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3671426818
Short name T903
Test name
Test status
Simulation time 432762642 ps
CPU time 0.82 seconds
Started Aug 04 05:30:36 PM PDT 24
Finished Aug 04 05:30:37 PM PDT 24
Peak memory 201340 kb
Host smart-20693baf-0856-421b-ad8b-1d326cd6a6d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671426818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3671426818
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2744861562
Short name T125
Test name
Test status
Simulation time 2256908406 ps
CPU time 3.04 seconds
Started Aug 04 05:30:46 PM PDT 24
Finished Aug 04 05:30:50 PM PDT 24
Peak memory 201424 kb
Host smart-fcbbb101-0c07-4361-95cb-03bf268323ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744861562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2744861562
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3504572378
Short name T872
Test name
Test status
Simulation time 735992090 ps
CPU time 2.6 seconds
Started Aug 04 05:30:39 PM PDT 24
Finished Aug 04 05:30:42 PM PDT 24
Peak memory 209736 kb
Host smart-bab703dc-ce86-4c37-862c-c6cc1e5b4cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504572378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3504572378
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1371874430
Short name T330
Test name
Test status
Simulation time 8382825886 ps
CPU time 6.68 seconds
Started Aug 04 05:30:36 PM PDT 24
Finished Aug 04 05:30:43 PM PDT 24
Peak memory 201660 kb
Host smart-9e14d137-c0a8-4480-864d-859d5b55e460
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371874430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1371874430
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2882613291
Short name T77
Test name
Test status
Simulation time 671092113 ps
CPU time 1.34 seconds
Started Aug 04 05:30:35 PM PDT 24
Finished Aug 04 05:30:37 PM PDT 24
Peak memory 201504 kb
Host smart-f8d9bd78-4825-405c-8c9b-957f886dfd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882613291 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2882613291
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.233319633
Short name T113
Test name
Test status
Simulation time 566110238 ps
CPU time 1.09 seconds
Started Aug 04 05:30:36 PM PDT 24
Finished Aug 04 05:30:38 PM PDT 24
Peak memory 201328 kb
Host smart-2ce669af-1e07-431b-a55e-fa66f47ca2ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233319633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.233319633
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.886656554
Short name T820
Test name
Test status
Simulation time 307055756 ps
CPU time 0.78 seconds
Started Aug 04 05:30:35 PM PDT 24
Finished Aug 04 05:30:36 PM PDT 24
Peak memory 201376 kb
Host smart-a51a68dc-4583-493a-9eec-07f1705d9bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886656554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.886656554
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1386619598
Short name T883
Test name
Test status
Simulation time 4329866058 ps
CPU time 21.63 seconds
Started Aug 04 05:30:43 PM PDT 24
Finished Aug 04 05:31:05 PM PDT 24
Peak memory 201612 kb
Host smart-d365b67c-e81a-4068-87d2-d7a825657e9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386619598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1386619598
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1738473094
Short name T73
Test name
Test status
Simulation time 618987206 ps
CPU time 3.24 seconds
Started Aug 04 05:30:35 PM PDT 24
Finished Aug 04 05:30:39 PM PDT 24
Peak memory 209892 kb
Host smart-5dd0a97a-6f3d-417a-994f-2f4be980b973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738473094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1738473094
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1278910843
Short name T866
Test name
Test status
Simulation time 4796440028 ps
CPU time 4.82 seconds
Started Aug 04 05:30:44 PM PDT 24
Finished Aug 04 05:30:49 PM PDT 24
Peak memory 201676 kb
Host smart-59e34eee-6bd6-4f3b-9dd8-fe421b07b261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278910843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1278910843
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.598806480
Short name T114
Test name
Test status
Simulation time 943535199 ps
CPU time 2.98 seconds
Started Aug 04 05:30:20 PM PDT 24
Finished Aug 04 05:30:23 PM PDT 24
Peak memory 201480 kb
Host smart-c20bcd26-3f7c-4573-b591-83f968713e98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598806480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.598806480
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2004474105
Short name T57
Test name
Test status
Simulation time 26482981404 ps
CPU time 17.53 seconds
Started Aug 04 05:30:21 PM PDT 24
Finished Aug 04 05:30:38 PM PDT 24
Peak memory 201540 kb
Host smart-f6f0c3d4-af0a-4f58-a590-ce289f973a0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004474105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2004474105
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.788490681
Short name T885
Test name
Test status
Simulation time 748779767 ps
CPU time 2.34 seconds
Started Aug 04 05:30:21 PM PDT 24
Finished Aug 04 05:30:23 PM PDT 24
Peak memory 201348 kb
Host smart-63f38893-37cf-4e09-92b8-fcca44cbf9ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788490681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.788490681
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2259290889
Short name T845
Test name
Test status
Simulation time 349239181 ps
CPU time 1.14 seconds
Started Aug 04 05:30:21 PM PDT 24
Finished Aug 04 05:30:22 PM PDT 24
Peak memory 201416 kb
Host smart-ace86ac6-91a1-40ba-8903-d60d83298040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259290889 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2259290889
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3529822106
Short name T848
Test name
Test status
Simulation time 483518686 ps
CPU time 1.87 seconds
Started Aug 04 05:30:23 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 201364 kb
Host smart-34b2ee64-9fff-4837-84d0-a4219f696e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529822106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3529822106
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1515055036
Short name T873
Test name
Test status
Simulation time 397412999 ps
CPU time 0.8 seconds
Started Aug 04 05:30:24 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 201356 kb
Host smart-75633a7b-bff8-41d3-b0bf-0082e9a4c6b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515055036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1515055036
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.749451014
Short name T126
Test name
Test status
Simulation time 5698378375 ps
CPU time 7.38 seconds
Started Aug 04 05:30:22 PM PDT 24
Finished Aug 04 05:30:29 PM PDT 24
Peak memory 201576 kb
Host smart-f2e795e7-e2ba-44e6-99a4-8521119a109b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749451014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.749451014
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2428901138
Short name T892
Test name
Test status
Simulation time 582260626 ps
CPU time 3.6 seconds
Started Aug 04 05:30:22 PM PDT 24
Finished Aug 04 05:30:26 PM PDT 24
Peak memory 210864 kb
Host smart-f7819344-1d13-41b8-92ee-c6f57ba00cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428901138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2428901138
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.877511276
Short name T861
Test name
Test status
Simulation time 7936348521 ps
CPU time 11.88 seconds
Started Aug 04 05:30:23 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201480 kb
Host smart-febd1091-a15e-495b-b128-7e40524303e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877511276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.877511276
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.666014608
Short name T805
Test name
Test status
Simulation time 429971352 ps
CPU time 0.87 seconds
Started Aug 04 05:30:43 PM PDT 24
Finished Aug 04 05:30:44 PM PDT 24
Peak memory 201352 kb
Host smart-b2aaab0b-627b-4d11-b30f-af1d23cb1b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666014608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.666014608
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1009811502
Short name T894
Test name
Test status
Simulation time 398992162 ps
CPU time 0.88 seconds
Started Aug 04 05:30:43 PM PDT 24
Finished Aug 04 05:30:44 PM PDT 24
Peak memory 201324 kb
Host smart-a85eba2c-29fd-4732-9f62-1ccf4f69f070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009811502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1009811502
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.634364724
Short name T858
Test name
Test status
Simulation time 400442494 ps
CPU time 1.05 seconds
Started Aug 04 05:30:43 PM PDT 24
Finished Aug 04 05:30:44 PM PDT 24
Peak memory 201280 kb
Host smart-83e7c328-ada2-4582-83e4-5c7729527bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634364724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.634364724
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.412198420
Short name T898
Test name
Test status
Simulation time 530795823 ps
CPU time 1.83 seconds
Started Aug 04 05:30:37 PM PDT 24
Finished Aug 04 05:30:39 PM PDT 24
Peak memory 201160 kb
Host smart-c40bdc1c-48d4-4efd-bc31-e95d24bdbb14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412198420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.412198420
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3161323103
Short name T835
Test name
Test status
Simulation time 419482062 ps
CPU time 1.62 seconds
Started Aug 04 05:30:40 PM PDT 24
Finished Aug 04 05:30:41 PM PDT 24
Peak memory 201336 kb
Host smart-65fa6ef7-075f-42da-9171-d851bcbdac95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161323103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3161323103
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2420014715
Short name T862
Test name
Test status
Simulation time 359476524 ps
CPU time 0.86 seconds
Started Aug 04 05:30:36 PM PDT 24
Finished Aug 04 05:30:37 PM PDT 24
Peak memory 201272 kb
Host smart-1ec5d9d9-cb45-4d31-969e-2e80c436b54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420014715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2420014715
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2899130439
Short name T867
Test name
Test status
Simulation time 324855295 ps
CPU time 0.97 seconds
Started Aug 04 05:30:42 PM PDT 24
Finished Aug 04 05:30:44 PM PDT 24
Peak memory 201228 kb
Host smart-5fe0d6a8-1add-4f01-9aa8-e8ed7b209cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899130439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2899130439
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2470396459
Short name T875
Test name
Test status
Simulation time 351402157 ps
CPU time 0.83 seconds
Started Aug 04 05:30:39 PM PDT 24
Finished Aug 04 05:30:40 PM PDT 24
Peak memory 201224 kb
Host smart-fed7ee49-cf25-4808-9ab8-edb4c2b3f3b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470396459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2470396459
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3819065892
Short name T859
Test name
Test status
Simulation time 425646144 ps
CPU time 0.87 seconds
Started Aug 04 05:30:38 PM PDT 24
Finished Aug 04 05:30:39 PM PDT 24
Peak memory 201360 kb
Host smart-7d83bd2d-60cb-45a2-83e6-d625a23a2cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819065892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3819065892
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1587593609
Short name T837
Test name
Test status
Simulation time 287549521 ps
CPU time 1.29 seconds
Started Aug 04 05:30:38 PM PDT 24
Finished Aug 04 05:30:39 PM PDT 24
Peak memory 201360 kb
Host smart-0932094a-4356-40a5-897b-518244afca8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587593609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1587593609
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3126520844
Short name T915
Test name
Test status
Simulation time 1323419009 ps
CPU time 2.85 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:34 PM PDT 24
Peak memory 201552 kb
Host smart-a785abeb-782c-4989-b915-a28c9936eb11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126520844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3126520844
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4258391053
Short name T896
Test name
Test status
Simulation time 26016467886 ps
CPU time 8.59 seconds
Started Aug 04 05:30:24 PM PDT 24
Finished Aug 04 05:30:33 PM PDT 24
Peak memory 201780 kb
Host smart-9d084298-f0c8-4dc4-86c4-86305aaa25b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258391053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.4258391053
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1176141155
Short name T846
Test name
Test status
Simulation time 760243689 ps
CPU time 2.39 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:34 PM PDT 24
Peak memory 201368 kb
Host smart-1644c4ff-b65a-4d22-8e21-ac292b26e688
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176141155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1176141155
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3686653264
Short name T111
Test name
Test status
Simulation time 478325344 ps
CPU time 1.2 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:32 PM PDT 24
Peak memory 201500 kb
Host smart-f9d2808c-5454-4a83-84a3-bbc333f5f0bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686653264 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3686653264
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.748621787
Short name T119
Test name
Test status
Simulation time 447111787 ps
CPU time 1.97 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:33 PM PDT 24
Peak memory 201364 kb
Host smart-5415cee4-6386-4e3b-a94f-8737ad4821f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748621787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.748621787
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4072945546
Short name T900
Test name
Test status
Simulation time 410651550 ps
CPU time 1.64 seconds
Started Aug 04 05:30:21 PM PDT 24
Finished Aug 04 05:30:23 PM PDT 24
Peak memory 201272 kb
Host smart-daf5fe46-02ea-4625-ae07-2ba8a6f403aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072945546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4072945546
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2263234377
Short name T124
Test name
Test status
Simulation time 3046129395 ps
CPU time 4.07 seconds
Started Aug 04 05:30:21 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 201232 kb
Host smart-18a11e1f-383a-4388-9a35-345ef6988e39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263234377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2263234377
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.963784863
Short name T64
Test name
Test status
Simulation time 403130198 ps
CPU time 2.5 seconds
Started Aug 04 05:30:20 PM PDT 24
Finished Aug 04 05:30:23 PM PDT 24
Peak memory 201680 kb
Host smart-8a0e8e97-4fba-4337-87c6-f7264af53655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963784863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.963784863
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.579990384
Short name T869
Test name
Test status
Simulation time 515540200 ps
CPU time 1.74 seconds
Started Aug 04 05:30:41 PM PDT 24
Finished Aug 04 05:30:43 PM PDT 24
Peak memory 201336 kb
Host smart-2f478522-718d-401a-967f-ddf35e163513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579990384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.579990384
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2100530842
Short name T895
Test name
Test status
Simulation time 463097887 ps
CPU time 1.63 seconds
Started Aug 04 05:30:38 PM PDT 24
Finished Aug 04 05:30:40 PM PDT 24
Peak memory 201352 kb
Host smart-4b859d71-cd4c-44a3-8089-861dbbefa56f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100530842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2100530842
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.222466808
Short name T878
Test name
Test status
Simulation time 395790294 ps
CPU time 1.5 seconds
Started Aug 04 05:30:46 PM PDT 24
Finished Aug 04 05:30:52 PM PDT 24
Peak memory 201352 kb
Host smart-aac8805d-ae96-4819-9983-c2d99c69ea73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222466808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.222466808
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.656420817
Short name T910
Test name
Test status
Simulation time 311690524 ps
CPU time 1.25 seconds
Started Aug 04 05:31:00 PM PDT 24
Finished Aug 04 05:31:01 PM PDT 24
Peak memory 201276 kb
Host smart-0e05bad2-0096-487d-ba92-d266b7dbaabe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656420817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.656420817
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2051977045
Short name T838
Test name
Test status
Simulation time 470018112 ps
CPU time 1.64 seconds
Started Aug 04 05:30:44 PM PDT 24
Finished Aug 04 05:30:46 PM PDT 24
Peak memory 201212 kb
Host smart-c2332f1b-edbf-4693-830f-172f33ea466d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051977045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2051977045
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3823524620
Short name T813
Test name
Test status
Simulation time 330170181 ps
CPU time 0.8 seconds
Started Aug 04 05:30:44 PM PDT 24
Finished Aug 04 05:30:45 PM PDT 24
Peak memory 201292 kb
Host smart-e4e86ba0-97f2-4885-b235-6dbe7a8b8626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823524620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3823524620
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.640245646
Short name T887
Test name
Test status
Simulation time 414917106 ps
CPU time 1.6 seconds
Started Aug 04 05:30:59 PM PDT 24
Finished Aug 04 05:31:01 PM PDT 24
Peak memory 201372 kb
Host smart-90f3f7fe-ff32-47bb-add2-7e96a370a370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640245646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.640245646
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4029341248
Short name T811
Test name
Test status
Simulation time 334871012 ps
CPU time 0.83 seconds
Started Aug 04 05:30:56 PM PDT 24
Finished Aug 04 05:30:57 PM PDT 24
Peak memory 201344 kb
Host smart-0c235a9c-4ae2-48ec-97a2-4637efcc9a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029341248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4029341248
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2264844667
Short name T909
Test name
Test status
Simulation time 479069782 ps
CPU time 0.91 seconds
Started Aug 04 05:30:53 PM PDT 24
Finished Aug 04 05:30:54 PM PDT 24
Peak memory 201380 kb
Host smart-750c446d-147f-4753-a743-6f8b31de5fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264844667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2264844667
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.521857215
Short name T857
Test name
Test status
Simulation time 325645621 ps
CPU time 1.44 seconds
Started Aug 04 05:31:06 PM PDT 24
Finished Aug 04 05:31:07 PM PDT 24
Peak memory 201340 kb
Host smart-705482ce-00ec-45b4-8501-99121930261d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521857215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.521857215
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2102429521
Short name T826
Test name
Test status
Simulation time 1090343673 ps
CPU time 4.43 seconds
Started Aug 04 05:30:28 PM PDT 24
Finished Aug 04 05:30:33 PM PDT 24
Peak memory 201552 kb
Host smart-50470a53-63b0-4caf-a447-3ba25cafccaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102429521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2102429521
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2989044848
Short name T825
Test name
Test status
Simulation time 26014606101 ps
CPU time 66.07 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:31:36 PM PDT 24
Peak memory 201636 kb
Host smart-a96234b5-4295-4529-a7e6-5b871bfb9fcb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989044848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2989044848
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1262339843
Short name T882
Test name
Test status
Simulation time 1036591361 ps
CPU time 2.08 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:34 PM PDT 24
Peak memory 201364 kb
Host smart-e1a95c46-7ac9-4151-8cb9-074cc9e4d03b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262339843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1262339843
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.217067660
Short name T95
Test name
Test status
Simulation time 368531435 ps
CPU time 1.06 seconds
Started Aug 04 05:30:26 PM PDT 24
Finished Aug 04 05:30:27 PM PDT 24
Peak memory 201504 kb
Host smart-12cd944f-c881-4577-90fb-5ee843522cac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217067660 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.217067660
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2500586788
Short name T115
Test name
Test status
Simulation time 411532200 ps
CPU time 1.03 seconds
Started Aug 04 05:30:24 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 201292 kb
Host smart-106821bc-11bf-4e6a-973a-af7f9d8f68d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500586788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2500586788
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3625336276
Short name T816
Test name
Test status
Simulation time 447436719 ps
CPU time 1.64 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:33 PM PDT 24
Peak memory 201348 kb
Host smart-bd4301d6-e9be-4644-b743-f0fc5107aec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625336276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3625336276
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3494044350
Short name T822
Test name
Test status
Simulation time 3983899789 ps
CPU time 4.25 seconds
Started Aug 04 05:30:24 PM PDT 24
Finished Aug 04 05:30:29 PM PDT 24
Peak memory 201604 kb
Host smart-d34e1bac-246e-44df-accf-869c800b3298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494044350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3494044350
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3939114880
Short name T911
Test name
Test status
Simulation time 957343758 ps
CPU time 2.76 seconds
Started Aug 04 05:30:22 PM PDT 24
Finished Aug 04 05:30:25 PM PDT 24
Peak memory 201572 kb
Host smart-5bc396f8-0bfa-4716-aaf2-76735ea69964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939114880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3939114880
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3694450694
Short name T329
Test name
Test status
Simulation time 8084580411 ps
CPU time 15.36 seconds
Started Aug 04 05:30:22 PM PDT 24
Finished Aug 04 05:30:37 PM PDT 24
Peak memory 201648 kb
Host smart-ac3dbdce-57d5-49b2-87ec-87d7672f06a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694450694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3694450694
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1677219904
Short name T918
Test name
Test status
Simulation time 290611712 ps
CPU time 0.96 seconds
Started Aug 04 05:30:41 PM PDT 24
Finished Aug 04 05:30:42 PM PDT 24
Peak memory 201368 kb
Host smart-9700effa-8016-4eb9-94c8-aec2d60fb295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677219904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1677219904
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3635147518
Short name T830
Test name
Test status
Simulation time 495653997 ps
CPU time 1.76 seconds
Started Aug 04 05:30:57 PM PDT 24
Finished Aug 04 05:30:59 PM PDT 24
Peak memory 201376 kb
Host smart-4cbd1340-d2c2-43c9-9c05-1b6b962e186a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635147518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3635147518
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2680507063
Short name T812
Test name
Test status
Simulation time 503801366 ps
CPU time 1.82 seconds
Started Aug 04 05:30:40 PM PDT 24
Finished Aug 04 05:30:42 PM PDT 24
Peak memory 201356 kb
Host smart-d2ef9f93-356b-473a-a1f6-507f340b889e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680507063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2680507063
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1498202218
Short name T815
Test name
Test status
Simulation time 306320897 ps
CPU time 0.83 seconds
Started Aug 04 05:30:44 PM PDT 24
Finished Aug 04 05:30:45 PM PDT 24
Peak memory 201344 kb
Host smart-033fcc5d-73d3-4211-851b-d0bec7a52a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498202218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1498202218
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3634673830
Short name T833
Test name
Test status
Simulation time 414318518 ps
CPU time 0.87 seconds
Started Aug 04 05:30:48 PM PDT 24
Finished Aug 04 05:30:49 PM PDT 24
Peak memory 201360 kb
Host smart-3fae0bbd-9d6f-4733-a021-0ff3d6f163dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634673830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3634673830
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2552435309
Short name T814
Test name
Test status
Simulation time 403953767 ps
CPU time 0.96 seconds
Started Aug 04 05:30:41 PM PDT 24
Finished Aug 04 05:30:42 PM PDT 24
Peak memory 201336 kb
Host smart-9265463e-c489-465d-981e-1f780216ced8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552435309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2552435309
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2266012195
Short name T810
Test name
Test status
Simulation time 456365226 ps
CPU time 1.17 seconds
Started Aug 04 05:30:59 PM PDT 24
Finished Aug 04 05:31:00 PM PDT 24
Peak memory 201372 kb
Host smart-98b0b954-4187-467c-b055-df9a549a814e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266012195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2266012195
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3803213014
Short name T841
Test name
Test status
Simulation time 510920339 ps
CPU time 1.71 seconds
Started Aug 04 05:30:40 PM PDT 24
Finished Aug 04 05:30:42 PM PDT 24
Peak memory 201364 kb
Host smart-862b7445-f71b-4049-b972-516392ae7ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803213014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3803213014
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.4019238446
Short name T817
Test name
Test status
Simulation time 294838634 ps
CPU time 1.3 seconds
Started Aug 04 05:30:42 PM PDT 24
Finished Aug 04 05:30:43 PM PDT 24
Peak memory 201372 kb
Host smart-3aaa9475-8f04-4cf4-86ff-4cef15926cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019238446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.4019238446
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2674063641
Short name T809
Test name
Test status
Simulation time 493086163 ps
CPU time 1.12 seconds
Started Aug 04 05:30:46 PM PDT 24
Finished Aug 04 05:30:53 PM PDT 24
Peak memory 201280 kb
Host smart-c93c87de-3446-448c-80c3-dc6f6ced02d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674063641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2674063641
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.976443809
Short name T864
Test name
Test status
Simulation time 385665983 ps
CPU time 1.87 seconds
Started Aug 04 05:30:25 PM PDT 24
Finished Aug 04 05:30:27 PM PDT 24
Peak memory 201504 kb
Host smart-f3ea8aa2-4e50-46a0-b9f5-ffebc9608a99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976443809 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.976443809
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.121457149
Short name T122
Test name
Test status
Simulation time 535226327 ps
CPU time 1.22 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201380 kb
Host smart-0c12214d-bc73-4c54-a5b4-e6fc7090d36b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121457149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.121457149
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2592869358
Short name T906
Test name
Test status
Simulation time 378315118 ps
CPU time 1.46 seconds
Started Aug 04 05:30:27 PM PDT 24
Finished Aug 04 05:30:29 PM PDT 24
Peak memory 201260 kb
Host smart-5f9aea29-cf27-466c-a073-dc501c6d00d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592869358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2592869358
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1443766598
Short name T889
Test name
Test status
Simulation time 5514240894 ps
CPU time 10 seconds
Started Aug 04 05:30:24 PM PDT 24
Finished Aug 04 05:30:34 PM PDT 24
Peak memory 201456 kb
Host smart-3cccca3a-4c1f-464a-a01b-f4660aa23342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443766598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1443766598
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2865715607
Short name T78
Test name
Test status
Simulation time 396151878 ps
CPU time 1.9 seconds
Started Aug 04 05:30:27 PM PDT 24
Finished Aug 04 05:30:30 PM PDT 24
Peak memory 201392 kb
Host smart-2ed10bc5-ac50-423b-9983-151fabfe18f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865715607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2865715607
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.676286040
Short name T333
Test name
Test status
Simulation time 8281336040 ps
CPU time 4.73 seconds
Started Aug 04 05:30:24 PM PDT 24
Finished Aug 04 05:30:29 PM PDT 24
Peak memory 201616 kb
Host smart-0dc14a15-a5ae-4924-8ba3-7b964b3aa285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676286040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.676286040
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3777010438
Short name T902
Test name
Test status
Simulation time 620282449 ps
CPU time 1.11 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201496 kb
Host smart-ceaecd47-598e-4f2d-a11d-0cf9b58db762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777010438 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3777010438
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3456685552
Short name T907
Test name
Test status
Simulation time 404411343 ps
CPU time 1.09 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201220 kb
Host smart-a9ee3771-8207-4ebb-8e04-55d298232302
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456685552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3456685552
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1659509562
Short name T806
Test name
Test status
Simulation time 453577184 ps
CPU time 1.68 seconds
Started Aug 04 05:30:28 PM PDT 24
Finished Aug 04 05:30:29 PM PDT 24
Peak memory 201392 kb
Host smart-fe393b30-0b8e-4e64-942d-74888ca56c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659509562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1659509562
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2052865411
Short name T904
Test name
Test status
Simulation time 4203016688 ps
CPU time 2.81 seconds
Started Aug 04 05:30:27 PM PDT 24
Finished Aug 04 05:30:30 PM PDT 24
Peak memory 201592 kb
Host smart-16720a49-cba0-4921-882f-39fe1b14b020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052865411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2052865411
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2032551896
Short name T839
Test name
Test status
Simulation time 527687973 ps
CPU time 1.85 seconds
Started Aug 04 05:30:26 PM PDT 24
Finished Aug 04 05:30:28 PM PDT 24
Peak memory 201684 kb
Host smart-f184e948-70e6-4717-ae3e-6e2e34f3c427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032551896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2032551896
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1690714967
Short name T62
Test name
Test status
Simulation time 4615580131 ps
CPU time 12.62 seconds
Started Aug 04 05:30:28 PM PDT 24
Finished Aug 04 05:30:40 PM PDT 24
Peak memory 201568 kb
Host smart-6f1de0cb-f40e-4be0-96a9-b030c532d154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690714967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1690714967
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.99492061
Short name T843
Test name
Test status
Simulation time 562706844 ps
CPU time 1.23 seconds
Started Aug 04 05:30:26 PM PDT 24
Finished Aug 04 05:30:27 PM PDT 24
Peak memory 209872 kb
Host smart-23851562-4d99-406f-b8e4-3e182bfa2ece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99492061 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.99492061
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3755962850
Short name T851
Test name
Test status
Simulation time 347965469 ps
CPU time 1.45 seconds
Started Aug 04 05:30:26 PM PDT 24
Finished Aug 04 05:30:27 PM PDT 24
Peak memory 201376 kb
Host smart-c865eb45-fd83-4461-bd3d-c459dff061bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755962850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3755962850
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2642374304
Short name T807
Test name
Test status
Simulation time 411170294 ps
CPU time 1.49 seconds
Started Aug 04 05:30:25 PM PDT 24
Finished Aug 04 05:30:26 PM PDT 24
Peak memory 201368 kb
Host smart-09543c4b-1231-4721-8f39-a967cc037b50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642374304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2642374304
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3928990173
Short name T868
Test name
Test status
Simulation time 2299803394 ps
CPU time 2.86 seconds
Started Aug 04 05:30:27 PM PDT 24
Finished Aug 04 05:30:30 PM PDT 24
Peak memory 201436 kb
Host smart-aad2d7b4-fdf8-4225-b569-9c67ab300167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928990173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3928990173
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4039126309
Short name T913
Test name
Test status
Simulation time 647445909 ps
CPU time 3.86 seconds
Started Aug 04 05:30:27 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201604 kb
Host smart-2b5c1622-d8fa-44c7-a4cb-99971a7e01a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039126309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4039126309
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3831789076
Short name T914
Test name
Test status
Simulation time 414752748 ps
CPU time 1.59 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201492 kb
Host smart-4480493a-f7c3-4afb-92ef-d301eb486865
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831789076 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3831789076
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3015349755
Short name T912
Test name
Test status
Simulation time 403829579 ps
CPU time 1.1 seconds
Started Aug 04 05:30:26 PM PDT 24
Finished Aug 04 05:30:27 PM PDT 24
Peak memory 201228 kb
Host smart-49de0b85-9ee4-4d94-8980-4c77c1b540cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015349755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3015349755
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.983050713
Short name T856
Test name
Test status
Simulation time 488828412 ps
CPU time 0.91 seconds
Started Aug 04 05:30:28 PM PDT 24
Finished Aug 04 05:30:30 PM PDT 24
Peak memory 201388 kb
Host smart-f8942c29-2262-406e-933f-9c43c03ff86b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983050713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.983050713
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2564960919
Short name T916
Test name
Test status
Simulation time 2533575804 ps
CPU time 6.38 seconds
Started Aug 04 05:30:28 PM PDT 24
Finished Aug 04 05:30:35 PM PDT 24
Peak memory 201352 kb
Host smart-6bc4e82a-54d0-4d7c-888e-33de726a8e76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564960919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2564960919
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2787078181
Short name T75
Test name
Test status
Simulation time 534438494 ps
CPU time 2.56 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201612 kb
Host smart-8b89e9eb-0fc0-42f7-ab4c-17150b48f1cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787078181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2787078181
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3208263900
Short name T897
Test name
Test status
Simulation time 471630485 ps
CPU time 1.82 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:30:32 PM PDT 24
Peak memory 201488 kb
Host smart-b46a9269-302a-422f-ab58-a25319beb3f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208263900 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3208263900
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2061144686
Short name T120
Test name
Test status
Simulation time 491278287 ps
CPU time 1.42 seconds
Started Aug 04 05:30:30 PM PDT 24
Finished Aug 04 05:30:31 PM PDT 24
Peak memory 201384 kb
Host smart-9958b7eb-749e-408e-a140-2d08305b30ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061144686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2061144686
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.158296222
Short name T802
Test name
Test status
Simulation time 392002904 ps
CPU time 0.83 seconds
Started Aug 04 05:30:31 PM PDT 24
Finished Aug 04 05:30:32 PM PDT 24
Peak memory 201336 kb
Host smart-ac04f00a-0a40-4497-8cdd-594e67ce4ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158296222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.158296222
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1002330845
Short name T877
Test name
Test status
Simulation time 2108556251 ps
CPU time 3.14 seconds
Started Aug 04 05:30:29 PM PDT 24
Finished Aug 04 05:30:32 PM PDT 24
Peak memory 201372 kb
Host smart-7e8280f9-f542-488b-9a1a-9097d2b815d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002330845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1002330845
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.643246654
Short name T850
Test name
Test status
Simulation time 7900061102 ps
CPU time 20.14 seconds
Started Aug 04 05:30:52 PM PDT 24
Finished Aug 04 05:31:12 PM PDT 24
Peak memory 201696 kb
Host smart-1e6bcf1d-699c-41af-bfa9-085d02d8f13e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643246654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.643246654
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1417790220
Short name T596
Test name
Test status
Simulation time 343287638 ps
CPU time 1.44 seconds
Started Aug 04 04:57:42 PM PDT 24
Finished Aug 04 04:57:43 PM PDT 24
Peak memory 201084 kb
Host smart-68099403-75f2-4aab-8e7b-b582d917f9c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417790220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1417790220
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2596577206
Short name T797
Test name
Test status
Simulation time 487422973087 ps
CPU time 424.91 seconds
Started Aug 04 04:57:39 PM PDT 24
Finished Aug 04 05:04:44 PM PDT 24
Peak memory 201344 kb
Host smart-d82ca5ff-b5c8-4103-85be-6bfc8cf09173
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596577206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2596577206
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1968241272
Short name T219
Test name
Test status
Simulation time 326853016222 ps
CPU time 744.55 seconds
Started Aug 04 04:57:39 PM PDT 24
Finished Aug 04 05:10:04 PM PDT 24
Peak memory 201308 kb
Host smart-0db192b7-d7a5-4054-84d2-69851b1cf54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968241272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1968241272
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.936496765
Short name T715
Test name
Test status
Simulation time 330612504589 ps
CPU time 763.19 seconds
Started Aug 04 04:57:39 PM PDT 24
Finished Aug 04 05:10:22 PM PDT 24
Peak memory 201388 kb
Host smart-eb1470e0-2ce1-4e01-ae51-85163680d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936496765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.936496765
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2156351771
Short name T454
Test name
Test status
Simulation time 331080889701 ps
CPU time 653.12 seconds
Started Aug 04 04:57:40 PM PDT 24
Finished Aug 04 05:08:33 PM PDT 24
Peak memory 201292 kb
Host smart-049ab89e-bc31-4443-aad9-aa7929a09377
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156351771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2156351771
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.68341836
Short name T716
Test name
Test status
Simulation time 493699726502 ps
CPU time 1127.25 seconds
Started Aug 04 04:57:38 PM PDT 24
Finished Aug 04 05:16:25 PM PDT 24
Peak memory 201304 kb
Host smart-7c8faa74-2886-4c39-bfb9-2396243f5d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68341836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.68341836
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2015402685
Short name T711
Test name
Test status
Simulation time 493053060772 ps
CPU time 1126.74 seconds
Started Aug 04 04:57:39 PM PDT 24
Finished Aug 04 05:16:26 PM PDT 24
Peak memory 201344 kb
Host smart-e4842512-4392-414f-aa4b-f8c03ec717ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015402685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2015402685
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2094335828
Short name T505
Test name
Test status
Simulation time 643858676286 ps
CPU time 1564.04 seconds
Started Aug 04 04:57:41 PM PDT 24
Finished Aug 04 05:23:45 PM PDT 24
Peak memory 201416 kb
Host smart-b3b79a3a-8aff-4769-88a2-c88c8dea776f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094335828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2094335828
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2002263982
Short name T768
Test name
Test status
Simulation time 38002359414 ps
CPU time 79.43 seconds
Started Aug 04 04:57:40 PM PDT 24
Finished Aug 04 04:58:59 PM PDT 24
Peak memory 201308 kb
Host smart-cddfb83c-47b1-47d1-8555-b61d245ce4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002263982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2002263982
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3461171684
Short name T621
Test name
Test status
Simulation time 3207075104 ps
CPU time 8.72 seconds
Started Aug 04 04:57:40 PM PDT 24
Finished Aug 04 04:57:49 PM PDT 24
Peak memory 201308 kb
Host smart-248a911d-1db9-4c3e-8509-8b7b5951ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461171684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3461171684
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.874110537
Short name T67
Test name
Test status
Simulation time 4589349611 ps
CPU time 10.39 seconds
Started Aug 04 04:57:40 PM PDT 24
Finished Aug 04 04:57:51 PM PDT 24
Peak memory 217084 kb
Host smart-a9deff96-ccd9-4192-9240-e4591ed38c3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874110537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.874110537
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.569363945
Short name T668
Test name
Test status
Simulation time 5558419401 ps
CPU time 7.35 seconds
Started Aug 04 04:57:38 PM PDT 24
Finished Aug 04 04:57:46 PM PDT 24
Peak memory 201304 kb
Host smart-b7af6705-6f1f-4b4a-896d-fd1026d81d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569363945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.569363945
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1836336946
Short name T228
Test name
Test status
Simulation time 534008704512 ps
CPU time 1175.62 seconds
Started Aug 04 04:57:38 PM PDT 24
Finished Aug 04 05:17:14 PM PDT 24
Peak memory 201440 kb
Host smart-3c1132e3-543f-45b0-af7d-cbcafb033d40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836336946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1836336946
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.153827013
Short name T97
Test name
Test status
Simulation time 172590484041 ps
CPU time 106.48 seconds
Started Aug 04 04:57:45 PM PDT 24
Finished Aug 04 04:59:32 PM PDT 24
Peak memory 201372 kb
Host smart-5f88caf9-ba55-41cf-96c9-ee3cabc5a4da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153827013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.153827013
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2936402676
Short name T741
Test name
Test status
Simulation time 487638235646 ps
CPU time 1103.6 seconds
Started Aug 04 04:57:45 PM PDT 24
Finished Aug 04 05:16:08 PM PDT 24
Peak memory 201392 kb
Host smart-a65f12b1-2ece-4de1-b82f-5a952e456841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936402676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2936402676
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1772030675
Short name T173
Test name
Test status
Simulation time 482330965840 ps
CPU time 304.24 seconds
Started Aug 04 04:57:43 PM PDT 24
Finished Aug 04 05:02:47 PM PDT 24
Peak memory 201420 kb
Host smart-377b9af7-fa3f-4461-a6cb-53c43ef605ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772030675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1772030675
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3973656327
Short name T586
Test name
Test status
Simulation time 325729128064 ps
CPU time 192.14 seconds
Started Aug 04 04:57:42 PM PDT 24
Finished Aug 04 05:00:54 PM PDT 24
Peak memory 201292 kb
Host smart-1d4c075a-3811-4666-a82c-605f8c00dafb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973656327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3973656327
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4179839524
Short name T449
Test name
Test status
Simulation time 328953338298 ps
CPU time 743.8 seconds
Started Aug 04 04:57:42 PM PDT 24
Finished Aug 04 05:10:06 PM PDT 24
Peak memory 201392 kb
Host smart-0dab30e6-e3d9-4a46-8375-a58acb66d793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179839524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4179839524
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.4015098871
Short name T487
Test name
Test status
Simulation time 492656462190 ps
CPU time 294.59 seconds
Started Aug 04 04:57:43 PM PDT 24
Finished Aug 04 05:02:37 PM PDT 24
Peak memory 201272 kb
Host smart-9fd0ff95-c3d2-47ae-9874-cb48334ea544
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015098871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.4015098871
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.615344511
Short name T6
Test name
Test status
Simulation time 541342162552 ps
CPU time 278.89 seconds
Started Aug 04 04:57:41 PM PDT 24
Finished Aug 04 05:02:20 PM PDT 24
Peak memory 201404 kb
Host smart-a518d4d5-fc8c-413b-bbf0-76687adf0d20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615344511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.615344511
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2507410786
Short name T411
Test name
Test status
Simulation time 403834339556 ps
CPU time 245.89 seconds
Started Aug 04 04:57:44 PM PDT 24
Finished Aug 04 05:01:50 PM PDT 24
Peak memory 201328 kb
Host smart-fa381642-b599-454c-b651-220afcbcc1b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507410786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2507410786
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3439653842
Short name T336
Test name
Test status
Simulation time 92818108648 ps
CPU time 357.84 seconds
Started Aug 04 04:57:45 PM PDT 24
Finished Aug 04 05:03:43 PM PDT 24
Peak memory 201776 kb
Host smart-1d320a24-d7d2-40a5-b31b-3cff6674fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439653842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3439653842
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2806090535
Short name T455
Test name
Test status
Simulation time 36245036474 ps
CPU time 18.97 seconds
Started Aug 04 04:57:47 PM PDT 24
Finished Aug 04 04:58:06 PM PDT 24
Peak memory 201180 kb
Host smart-e996e9d8-3e2b-44b9-9ad5-11186b13032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806090535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2806090535
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2174328850
Short name T719
Test name
Test status
Simulation time 4799945628 ps
CPU time 11.97 seconds
Started Aug 04 04:57:45 PM PDT 24
Finished Aug 04 04:57:57 PM PDT 24
Peak memory 201308 kb
Host smart-eeda4677-8382-4eda-af0e-4dd03f98923e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174328850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2174328850
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1962806373
Short name T83
Test name
Test status
Simulation time 8166132844 ps
CPU time 18.08 seconds
Started Aug 04 04:57:50 PM PDT 24
Finished Aug 04 04:58:09 PM PDT 24
Peak memory 218052 kb
Host smart-4954bbe7-466f-4e4d-96c8-2566d5a451fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962806373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1962806373
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.302783644
Short name T106
Test name
Test status
Simulation time 6019536315 ps
CPU time 9.64 seconds
Started Aug 04 04:57:42 PM PDT 24
Finished Aug 04 04:57:52 PM PDT 24
Peak memory 201272 kb
Host smart-3d2c1171-44d8-4273-b2ba-75641cbc990d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302783644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.302783644
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2973003428
Short name T274
Test name
Test status
Simulation time 222292900944 ps
CPU time 465.25 seconds
Started Aug 04 04:57:46 PM PDT 24
Finished Aug 04 05:05:31 PM PDT 24
Peak memory 201376 kb
Host smart-d7642f8e-9bfa-4edd-926e-258ccafc86d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973003428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2973003428
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3269817390
Short name T172
Test name
Test status
Simulation time 177712451358 ps
CPU time 214.93 seconds
Started Aug 04 04:57:46 PM PDT 24
Finished Aug 04 05:01:21 PM PDT 24
Peak memory 209740 kb
Host smart-f82badcd-69c1-49a6-8700-f12a85f1ce47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269817390 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3269817390
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1952204948
Short name T560
Test name
Test status
Simulation time 625210647 ps
CPU time 0.69 seconds
Started Aug 04 04:58:33 PM PDT 24
Finished Aug 04 04:58:34 PM PDT 24
Peak memory 201108 kb
Host smart-72ded3e1-8489-4e8c-ae84-5c3237bd3869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952204948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1952204948
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3172632937
Short name T263
Test name
Test status
Simulation time 354824700215 ps
CPU time 120.27 seconds
Started Aug 04 04:58:29 PM PDT 24
Finished Aug 04 05:00:29 PM PDT 24
Peak memory 201320 kb
Host smart-759d6ada-c632-4523-9655-970742ea9ada
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172632937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3172632937
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1060195616
Short name T161
Test name
Test status
Simulation time 373586063766 ps
CPU time 236.08 seconds
Started Aug 04 04:58:28 PM PDT 24
Finished Aug 04 05:02:25 PM PDT 24
Peak memory 201392 kb
Host smart-b5497591-d299-43f9-970a-6cf66a5e4e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060195616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1060195616
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.677949015
Short name T640
Test name
Test status
Simulation time 320597940713 ps
CPU time 410.37 seconds
Started Aug 04 04:58:30 PM PDT 24
Finished Aug 04 05:05:20 PM PDT 24
Peak memory 201468 kb
Host smart-16ead681-06cf-4d00-82f3-cb297c20ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677949015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.677949015
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1742304730
Short name T728
Test name
Test status
Simulation time 494397299825 ps
CPU time 643.13 seconds
Started Aug 04 04:58:29 PM PDT 24
Finished Aug 04 05:09:13 PM PDT 24
Peak memory 201344 kb
Host smart-49c55a77-3059-43cc-92b5-13bbda096790
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742304730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1742304730
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1920669601
Short name T418
Test name
Test status
Simulation time 164434705184 ps
CPU time 105.89 seconds
Started Aug 04 04:58:26 PM PDT 24
Finished Aug 04 05:00:12 PM PDT 24
Peak memory 201276 kb
Host smart-d79fc671-d7d9-4700-a362-7fd0a0bae176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920669601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1920669601
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1732033955
Short name T463
Test name
Test status
Simulation time 156910048786 ps
CPU time 46.33 seconds
Started Aug 04 04:58:32 PM PDT 24
Finished Aug 04 04:59:19 PM PDT 24
Peak memory 201352 kb
Host smart-17afd072-9938-4f00-8df2-5850e9947cb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732033955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1732033955
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1583048097
Short name T96
Test name
Test status
Simulation time 595175286040 ps
CPU time 425.14 seconds
Started Aug 04 04:58:33 PM PDT 24
Finished Aug 04 05:05:38 PM PDT 24
Peak memory 201420 kb
Host smart-832d01e3-d2a7-409d-9ade-f34a43fe90b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583048097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1583048097
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3024487771
Short name T482
Test name
Test status
Simulation time 603147920413 ps
CPU time 1474.68 seconds
Started Aug 04 04:58:29 PM PDT 24
Finished Aug 04 05:23:04 PM PDT 24
Peak memory 201344 kb
Host smart-2a2d4d76-8ef0-4e69-aa55-df4c67e5893e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024487771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3024487771
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1990244384
Short name T549
Test name
Test status
Simulation time 99607798074 ps
CPU time 452.81 seconds
Started Aug 04 04:58:34 PM PDT 24
Finished Aug 04 05:06:07 PM PDT 24
Peak memory 201772 kb
Host smart-207cdd13-f38c-4fcc-9cf5-7a642b69936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990244384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1990244384
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3937839105
Short name T467
Test name
Test status
Simulation time 36160436363 ps
CPU time 13.28 seconds
Started Aug 04 04:58:32 PM PDT 24
Finished Aug 04 04:58:45 PM PDT 24
Peak memory 201256 kb
Host smart-9806148d-cfd2-40d8-bcce-b7475ee23f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937839105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3937839105
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.180160082
Short name T528
Test name
Test status
Simulation time 5180047326 ps
CPU time 7.09 seconds
Started Aug 04 04:58:30 PM PDT 24
Finished Aug 04 04:58:37 PM PDT 24
Peak memory 201292 kb
Host smart-44759d19-87bb-4025-9419-8511d1c0be0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180160082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.180160082
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.279976586
Short name T763
Test name
Test status
Simulation time 5967295351 ps
CPU time 4.95 seconds
Started Aug 04 04:58:26 PM PDT 24
Finished Aug 04 04:58:31 PM PDT 24
Peak memory 201212 kb
Host smart-ed719ef2-363a-4b2c-afd5-bc27f75427a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279976586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.279976586
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3798121399
Short name T612
Test name
Test status
Simulation time 364300568518 ps
CPU time 733.13 seconds
Started Aug 04 04:58:32 PM PDT 24
Finished Aug 04 05:10:46 PM PDT 24
Peak memory 201408 kb
Host smart-3c2fc4de-af5a-40c0-9b82-bbf1433465f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798121399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3798121399
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1267221854
Short name T554
Test name
Test status
Simulation time 238123805634 ps
CPU time 162.94 seconds
Started Aug 04 04:58:35 PM PDT 24
Finished Aug 04 05:01:18 PM PDT 24
Peak memory 210084 kb
Host smart-5ed51cf8-fbc4-4449-abb1-d379bc4247b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267221854 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1267221854
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2541251564
Short name T693
Test name
Test status
Simulation time 404265675 ps
CPU time 0.86 seconds
Started Aug 04 04:58:38 PM PDT 24
Finished Aug 04 04:58:39 PM PDT 24
Peak memory 201204 kb
Host smart-21847473-4061-4aaa-be15-a5d89d676458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541251564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2541251564
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2754220939
Short name T781
Test name
Test status
Simulation time 167877601011 ps
CPU time 206.39 seconds
Started Aug 04 04:58:37 PM PDT 24
Finished Aug 04 05:02:03 PM PDT 24
Peak memory 201308 kb
Host smart-11fab331-c440-4c05-a80b-506fb114af85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754220939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2754220939
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.4055767317
Short name T175
Test name
Test status
Simulation time 499468621117 ps
CPU time 310.29 seconds
Started Aug 04 04:58:36 PM PDT 24
Finished Aug 04 05:03:46 PM PDT 24
Peak memory 201340 kb
Host smart-29b84a90-8eb2-41a5-8538-17fc6248a77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055767317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.4055767317
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1407288017
Short name T730
Test name
Test status
Simulation time 172788161398 ps
CPU time 197.08 seconds
Started Aug 04 04:58:37 PM PDT 24
Finished Aug 04 05:01:54 PM PDT 24
Peak memory 201352 kb
Host smart-d496b839-b8d4-4159-af9a-574190214969
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407288017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1407288017
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.720865878
Short name T508
Test name
Test status
Simulation time 493320536812 ps
CPU time 270.96 seconds
Started Aug 04 04:58:32 PM PDT 24
Finished Aug 04 05:03:03 PM PDT 24
Peak memory 201328 kb
Host smart-f5a28a57-e762-4075-af6f-08debc18d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720865878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.720865878
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1709594506
Short name T380
Test name
Test status
Simulation time 487176461831 ps
CPU time 129.36 seconds
Started Aug 04 04:58:34 PM PDT 24
Finished Aug 04 05:00:43 PM PDT 24
Peak memory 201372 kb
Host smart-310e5988-9ffd-4366-a105-f7f1403f4310
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709594506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1709594506
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.272598804
Short name T758
Test name
Test status
Simulation time 351571116527 ps
CPU time 217.83 seconds
Started Aug 04 04:58:39 PM PDT 24
Finished Aug 04 05:02:17 PM PDT 24
Peak memory 201408 kb
Host smart-44598027-e780-4009-93f8-f4c7be635ac7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272598804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.272598804
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3057614023
Short name T722
Test name
Test status
Simulation time 382986480234 ps
CPU time 787.31 seconds
Started Aug 04 04:58:36 PM PDT 24
Finished Aug 04 05:11:44 PM PDT 24
Peak memory 201336 kb
Host smart-6d9fcdb6-028c-4d44-aab8-37fcf8f88c1a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057614023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3057614023
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1736964880
Short name T194
Test name
Test status
Simulation time 92460132554 ps
CPU time 367.57 seconds
Started Aug 04 04:58:35 PM PDT 24
Finished Aug 04 05:04:43 PM PDT 24
Peak memory 201680 kb
Host smart-d08467e3-1462-408a-825e-df4a1fe05202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736964880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1736964880
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3459370333
Short name T488
Test name
Test status
Simulation time 44445882158 ps
CPU time 96.3 seconds
Started Aug 04 04:58:39 PM PDT 24
Finished Aug 04 05:00:16 PM PDT 24
Peak memory 201320 kb
Host smart-64051256-44b5-45f7-a479-f1c56c7ab273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459370333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3459370333
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3639715617
Short name T690
Test name
Test status
Simulation time 4086319824 ps
CPU time 3.7 seconds
Started Aug 04 04:58:36 PM PDT 24
Finished Aug 04 04:58:40 PM PDT 24
Peak memory 201224 kb
Host smart-e1aa11ca-64e1-4874-85ab-4fb46be2e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639715617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3639715617
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.4003756135
Short name T619
Test name
Test status
Simulation time 5626146257 ps
CPU time 14.13 seconds
Started Aug 04 04:58:32 PM PDT 24
Finished Aug 04 04:58:46 PM PDT 24
Peak memory 201336 kb
Host smart-3fdde6ca-d4cc-4f0c-9677-0845235e3d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003756135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.4003756135
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.442225005
Short name T442
Test name
Test status
Simulation time 30593643311 ps
CPU time 37.08 seconds
Started Aug 04 04:58:39 PM PDT 24
Finished Aug 04 04:59:16 PM PDT 24
Peak memory 201224 kb
Host smart-86806b4b-c50b-4e8c-84bb-47aa8f9acecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442225005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
442225005
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3087890958
Short name T799
Test name
Test status
Simulation time 470834013 ps
CPU time 1.02 seconds
Started Aug 04 04:58:46 PM PDT 24
Finished Aug 04 04:58:47 PM PDT 24
Peak memory 201192 kb
Host smart-d6bc3614-9a8b-44ba-bd4c-ee3757de340c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087890958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3087890958
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3336233502
Short name T477
Test name
Test status
Simulation time 370412352595 ps
CPU time 193.17 seconds
Started Aug 04 04:58:43 PM PDT 24
Finished Aug 04 05:01:56 PM PDT 24
Peak memory 201412 kb
Host smart-c9b65cb7-49e7-4739-b3b8-b7e17668b27e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336233502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3336233502
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.641973777
Short name T272
Test name
Test status
Simulation time 162477166145 ps
CPU time 94.91 seconds
Started Aug 04 04:58:43 PM PDT 24
Finished Aug 04 05:00:18 PM PDT 24
Peak memory 201368 kb
Host smart-c624db19-8a20-41d8-be06-3d643fe434fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641973777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.641973777
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3121894530
Short name T459
Test name
Test status
Simulation time 489912575760 ps
CPU time 594.49 seconds
Started Aug 04 04:58:38 PM PDT 24
Finished Aug 04 05:08:33 PM PDT 24
Peak memory 201364 kb
Host smart-839047d9-aca6-4391-a45d-a41076c9bfe8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121894530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3121894530
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1475172800
Short name T691
Test name
Test status
Simulation time 323974113859 ps
CPU time 100.92 seconds
Started Aug 04 04:58:38 PM PDT 24
Finished Aug 04 05:00:19 PM PDT 24
Peak memory 201408 kb
Host smart-b9fa05aa-236e-4c32-8410-2b9b7949b2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475172800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1475172800
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3085716182
Short name T386
Test name
Test status
Simulation time 328843245549 ps
CPU time 71.45 seconds
Started Aug 04 04:58:39 PM PDT 24
Finished Aug 04 04:59:50 PM PDT 24
Peak memory 201308 kb
Host smart-8da6f635-b06b-46c1-96c8-04095692b7a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085716182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3085716182
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1188408149
Short name T631
Test name
Test status
Simulation time 200003966156 ps
CPU time 130.52 seconds
Started Aug 04 04:58:41 PM PDT 24
Finished Aug 04 05:00:52 PM PDT 24
Peak memory 201392 kb
Host smart-2177a015-cbd0-4856-9b4f-7f282a8bced2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188408149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1188408149
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.731406166
Short name T680
Test name
Test status
Simulation time 42647384969 ps
CPU time 36.19 seconds
Started Aug 04 04:58:45 PM PDT 24
Finished Aug 04 04:59:21 PM PDT 24
Peak memory 201296 kb
Host smart-b1a573ee-c300-4ad3-b223-72ee81aacb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731406166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.731406166
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2675264605
Short name T105
Test name
Test status
Simulation time 4879756417 ps
CPU time 5.84 seconds
Started Aug 04 04:58:42 PM PDT 24
Finished Aug 04 04:58:48 PM PDT 24
Peak memory 201204 kb
Host smart-81f4754e-ed7d-4201-9fbf-73da7e8a2f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675264605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2675264605
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2070967748
Short name T625
Test name
Test status
Simulation time 5665985430 ps
CPU time 3.73 seconds
Started Aug 04 04:58:38 PM PDT 24
Finished Aug 04 04:58:42 PM PDT 24
Peak memory 201220 kb
Host smart-255bef9f-b85e-4e17-9b13-36e90ba9a71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070967748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2070967748
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2401683044
Short name T204
Test name
Test status
Simulation time 322106998390 ps
CPU time 162.74 seconds
Started Aug 04 04:58:44 PM PDT 24
Finished Aug 04 05:01:27 PM PDT 24
Peak memory 201336 kb
Host smart-73342f59-2257-4922-b1db-cc8e2f48d6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401683044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2401683044
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.677157546
Short name T29
Test name
Test status
Simulation time 216257383264 ps
CPU time 141.39 seconds
Started Aug 04 04:58:44 PM PDT 24
Finished Aug 04 05:01:06 PM PDT 24
Peak memory 210088 kb
Host smart-126f510e-6eab-4fc7-8914-e88413ae20c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677157546 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.677157546
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.723881882
Short name T522
Test name
Test status
Simulation time 345051396 ps
CPU time 0.82 seconds
Started Aug 04 04:58:53 PM PDT 24
Finished Aug 04 04:58:54 PM PDT 24
Peak memory 201152 kb
Host smart-8541e800-94b6-4680-b93b-f48ebefcdba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723881882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.723881882
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.538672804
Short name T627
Test name
Test status
Simulation time 524247357949 ps
CPU time 1113.08 seconds
Started Aug 04 04:58:48 PM PDT 24
Finished Aug 04 05:17:21 PM PDT 24
Peak memory 201392 kb
Host smart-6e122361-9209-4dd7-a969-c5611f0f776d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538672804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.538672804
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.532647176
Short name T212
Test name
Test status
Simulation time 331872199293 ps
CPU time 747.68 seconds
Started Aug 04 04:58:47 PM PDT 24
Finished Aug 04 05:11:15 PM PDT 24
Peak memory 201364 kb
Host smart-b1efe7b6-0ebb-4e12-8e17-cb26b02b96fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532647176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.532647176
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3010287747
Short name T231
Test name
Test status
Simulation time 326683058287 ps
CPU time 386.87 seconds
Started Aug 04 04:58:46 PM PDT 24
Finished Aug 04 05:05:13 PM PDT 24
Peak memory 201400 kb
Host smart-8a6aaa4b-6a66-4ab9-be24-76e5aad28e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010287747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3010287747
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1972457281
Short name T653
Test name
Test status
Simulation time 494436693387 ps
CPU time 1133.07 seconds
Started Aug 04 04:58:49 PM PDT 24
Finished Aug 04 05:17:43 PM PDT 24
Peak memory 201408 kb
Host smart-0bb004eb-fe21-473d-9408-7e97f31f5907
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972457281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1972457281
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2246594893
Short name T160
Test name
Test status
Simulation time 167690003389 ps
CPU time 364.11 seconds
Started Aug 04 04:58:48 PM PDT 24
Finished Aug 04 05:04:52 PM PDT 24
Peak memory 201316 kb
Host smart-2e3b9425-e427-44dc-9e0f-42da2b2607bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246594893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2246594893
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.980555065
Short name T9
Test name
Test status
Simulation time 320757345055 ps
CPU time 770.7 seconds
Started Aug 04 04:58:50 PM PDT 24
Finished Aug 04 05:11:40 PM PDT 24
Peak memory 201424 kb
Host smart-e6fce2b6-3132-4dc0-b1fa-8a721d7f29c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=980555065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.980555065
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2685348380
Short name T777
Test name
Test status
Simulation time 600441524220 ps
CPU time 357.37 seconds
Started Aug 04 04:58:48 PM PDT 24
Finished Aug 04 05:04:45 PM PDT 24
Peak memory 201292 kb
Host smart-234e5174-19a9-435f-ba0a-02f3f385c099
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685348380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2685348380
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2243977688
Short name T435
Test name
Test status
Simulation time 87340556740 ps
CPU time 444.78 seconds
Started Aug 04 04:58:50 PM PDT 24
Finished Aug 04 05:06:15 PM PDT 24
Peak memory 201796 kb
Host smart-60fd25dc-9192-4677-9566-6553a1827182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243977688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2243977688
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.654945226
Short name T558
Test name
Test status
Simulation time 32812072461 ps
CPU time 75.1 seconds
Started Aug 04 04:58:51 PM PDT 24
Finished Aug 04 05:00:06 PM PDT 24
Peak memory 201236 kb
Host smart-05024063-1d80-4281-9565-2612b02e65b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654945226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.654945226
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.764936879
Short name T630
Test name
Test status
Simulation time 4544398616 ps
CPU time 2.66 seconds
Started Aug 04 04:58:48 PM PDT 24
Finished Aug 04 04:58:51 PM PDT 24
Peak memory 201312 kb
Host smart-dda640ea-70f1-4f16-8b84-44a1ddc4f96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764936879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.764936879
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1934317103
Short name T420
Test name
Test status
Simulation time 6172862166 ps
CPU time 4.55 seconds
Started Aug 04 04:58:48 PM PDT 24
Finished Aug 04 04:58:52 PM PDT 24
Peak memory 201280 kb
Host smart-bc39f142-4ec4-40ca-bc4b-f5ba7e3e4bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934317103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1934317103
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1410993055
Short name T220
Test name
Test status
Simulation time 1223593217135 ps
CPU time 3230.58 seconds
Started Aug 04 04:58:49 PM PDT 24
Finished Aug 04 05:52:40 PM PDT 24
Peak memory 209984 kb
Host smart-b0b340d8-cd30-479a-a64b-75b34fbcfaea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410993055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1410993055
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3052251599
Short name T780
Test name
Test status
Simulation time 177255946867 ps
CPU time 145.39 seconds
Started Aug 04 04:58:49 PM PDT 24
Finished Aug 04 05:01:15 PM PDT 24
Peak memory 209972 kb
Host smart-a955f8e0-e740-4a0e-88ca-95e64d981bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052251599 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3052251599
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1150958214
Short name T76
Test name
Test status
Simulation time 464797704 ps
CPU time 0.96 seconds
Started Aug 04 04:58:58 PM PDT 24
Finished Aug 04 04:58:59 PM PDT 24
Peak memory 201112 kb
Host smart-5dccfcae-cb7c-4c54-8aeb-f44030cfc7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150958214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1150958214
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3854869658
Short name T476
Test name
Test status
Simulation time 161597017831 ps
CPU time 124.36 seconds
Started Aug 04 04:58:55 PM PDT 24
Finished Aug 04 05:00:59 PM PDT 24
Peak memory 201384 kb
Host smart-b2a543be-1935-449c-975e-173f8f18c1f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854869658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3854869658
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2938987633
Short name T133
Test name
Test status
Simulation time 165342244672 ps
CPU time 99.62 seconds
Started Aug 04 04:58:55 PM PDT 24
Finished Aug 04 05:00:34 PM PDT 24
Peak memory 201296 kb
Host smart-0d119aff-13f5-4cd8-97f6-0b4c142feb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938987633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2938987633
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1598443081
Short name T552
Test name
Test status
Simulation time 334107715871 ps
CPU time 198.49 seconds
Started Aug 04 04:58:56 PM PDT 24
Finished Aug 04 05:02:15 PM PDT 24
Peak memory 201456 kb
Host smart-9e11ffb5-7952-41c3-97de-545bac4bfc89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598443081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1598443081
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.555283952
Short name T46
Test name
Test status
Simulation time 491165597167 ps
CPU time 282.94 seconds
Started Aug 04 04:58:50 PM PDT 24
Finished Aug 04 05:03:33 PM PDT 24
Peak memory 201384 kb
Host smart-6cca6e2b-b141-4396-a04a-a7aa3998fa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555283952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.555283952
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.391382224
Short name T357
Test name
Test status
Simulation time 327938103059 ps
CPU time 418.55 seconds
Started Aug 04 04:58:53 PM PDT 24
Finished Aug 04 05:05:52 PM PDT 24
Peak memory 201364 kb
Host smart-28ff78db-a7c2-4bc6-a46a-d22c13089521
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=391382224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.391382224
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3069033755
Short name T557
Test name
Test status
Simulation time 191958271851 ps
CPU time 108.31 seconds
Started Aug 04 04:58:53 PM PDT 24
Finished Aug 04 05:00:42 PM PDT 24
Peak memory 201292 kb
Host smart-848278c9-6f15-4234-844b-9721acc83fdf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069033755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3069033755
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4152037625
Short name T388
Test name
Test status
Simulation time 203211396711 ps
CPU time 481.16 seconds
Started Aug 04 04:58:54 PM PDT 24
Finished Aug 04 05:06:55 PM PDT 24
Peak memory 201408 kb
Host smart-df9a3300-9b98-4592-9a6f-525483b0a53d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152037625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.4152037625
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.315874192
Short name T547
Test name
Test status
Simulation time 67769446281 ps
CPU time 298.01 seconds
Started Aug 04 04:58:57 PM PDT 24
Finished Aug 04 05:03:55 PM PDT 24
Peak memory 201780 kb
Host smart-320597ac-c1ff-4497-b920-b973451d3908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315874192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.315874192
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1811596727
Short name T423
Test name
Test status
Simulation time 42001763578 ps
CPU time 90.8 seconds
Started Aug 04 04:58:56 PM PDT 24
Finished Aug 04 05:00:27 PM PDT 24
Peak memory 201252 kb
Host smart-be85bae1-74be-4c9a-bfb8-1bbb18fc9513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811596727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1811596727
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1301759666
Short name T708
Test name
Test status
Simulation time 4491291160 ps
CPU time 5.85 seconds
Started Aug 04 04:58:59 PM PDT 24
Finished Aug 04 04:59:05 PM PDT 24
Peak memory 201264 kb
Host smart-49dc307b-60e9-4885-bfa4-77f09a514304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301759666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1301759666
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4256448868
Short name T753
Test name
Test status
Simulation time 5944336179 ps
CPU time 14.86 seconds
Started Aug 04 04:58:53 PM PDT 24
Finished Aug 04 04:59:08 PM PDT 24
Peak memory 201240 kb
Host smart-c57dcff4-a83d-45f2-9a09-58f58e91816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256448868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4256448868
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1307769200
Short name T593
Test name
Test status
Simulation time 617700973551 ps
CPU time 358.08 seconds
Started Aug 04 04:58:58 PM PDT 24
Finished Aug 04 05:04:56 PM PDT 24
Peak memory 209712 kb
Host smart-961c5b7b-46f5-43e2-aac1-a0aa50b0e6b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307769200 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1307769200
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1645939431
Short name T618
Test name
Test status
Simulation time 477125175 ps
CPU time 1.78 seconds
Started Aug 04 04:59:09 PM PDT 24
Finished Aug 04 04:59:11 PM PDT 24
Peak memory 201152 kb
Host smart-5876a1e2-8402-4698-a298-122190f23d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645939431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1645939431
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2053961560
Short name T107
Test name
Test status
Simulation time 197664974528 ps
CPU time 96.2 seconds
Started Aug 04 04:59:05 PM PDT 24
Finished Aug 04 05:00:41 PM PDT 24
Peak memory 201364 kb
Host smart-8ec8f58b-24ad-410c-a6d1-8e9385f065b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053961560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2053961560
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1362232038
Short name T292
Test name
Test status
Simulation time 179185835900 ps
CPU time 266.29 seconds
Started Aug 04 04:59:03 PM PDT 24
Finished Aug 04 05:03:30 PM PDT 24
Peak memory 201304 kb
Host smart-d9f7ea3f-50ee-472d-873c-57d0684696a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362232038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1362232038
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1001147310
Short name T207
Test name
Test status
Simulation time 317471084208 ps
CPU time 198.55 seconds
Started Aug 04 04:59:00 PM PDT 24
Finished Aug 04 05:02:19 PM PDT 24
Peak memory 201356 kb
Host smart-3a231a42-d979-4833-a8e7-3a53e2b1e7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001147310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1001147310
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1627556580
Short name T99
Test name
Test status
Simulation time 497501278954 ps
CPU time 1016.79 seconds
Started Aug 04 04:59:00 PM PDT 24
Finished Aug 04 05:15:57 PM PDT 24
Peak memory 201456 kb
Host smart-aa184641-9cfd-4e94-b2cf-607a0012c7cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627556580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1627556580
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2376904936
Short name T474
Test name
Test status
Simulation time 333894232256 ps
CPU time 395.04 seconds
Started Aug 04 04:58:57 PM PDT 24
Finished Aug 04 05:05:32 PM PDT 24
Peak memory 201304 kb
Host smart-31be3ebe-cc36-46f2-bc5a-ffa85f8e41d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376904936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2376904936
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1398898037
Short name T494
Test name
Test status
Simulation time 487080642646 ps
CPU time 190.04 seconds
Started Aug 04 04:58:59 PM PDT 24
Finished Aug 04 05:02:09 PM PDT 24
Peak memory 201348 kb
Host smart-dd5b2ed9-34d9-4d9a-9648-3b0f01a6e624
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398898037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1398898037
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.175115342
Short name T784
Test name
Test status
Simulation time 364725013143 ps
CPU time 832.38 seconds
Started Aug 04 04:59:00 PM PDT 24
Finished Aug 04 05:12:53 PM PDT 24
Peak memory 201364 kb
Host smart-3d5ad67b-4aa1-435c-9261-f26fdc4dd1d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175115342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.175115342
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2786224667
Short name T550
Test name
Test status
Simulation time 200551605098 ps
CPU time 459.87 seconds
Started Aug 04 04:58:59 PM PDT 24
Finished Aug 04 05:06:39 PM PDT 24
Peak memory 201364 kb
Host smart-caccd81c-e920-4239-8dd3-28ba21015e21
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786224667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2786224667
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1276963358
Short name T507
Test name
Test status
Simulation time 116706986377 ps
CPU time 513.96 seconds
Started Aug 04 04:59:04 PM PDT 24
Finished Aug 04 05:07:38 PM PDT 24
Peak memory 201584 kb
Host smart-e8f63d74-6392-46ff-b4a2-9f2ec843c2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276963358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1276963358
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1461727567
Short name T546
Test name
Test status
Simulation time 40728208022 ps
CPU time 50.24 seconds
Started Aug 04 04:59:02 PM PDT 24
Finished Aug 04 04:59:53 PM PDT 24
Peak memory 201268 kb
Host smart-ec4a1766-583b-40b5-bed4-ce10f68aed47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461727567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1461727567
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3557895684
Short name T373
Test name
Test status
Simulation time 4563405240 ps
CPU time 3.33 seconds
Started Aug 04 04:59:04 PM PDT 24
Finished Aug 04 04:59:08 PM PDT 24
Peak memory 201264 kb
Host smart-a72c012b-07ae-4779-916e-2ccb4cbce02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557895684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3557895684
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.726146096
Short name T675
Test name
Test status
Simulation time 5731958210 ps
CPU time 4.2 seconds
Started Aug 04 04:58:57 PM PDT 24
Finished Aug 04 04:59:02 PM PDT 24
Peak memory 201232 kb
Host smart-2b80e742-9753-45ba-8036-a32cfaf5f8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726146096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.726146096
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.695520967
Short name T491
Test name
Test status
Simulation time 122299498728 ps
CPU time 652.36 seconds
Started Aug 04 04:59:06 PM PDT 24
Finished Aug 04 05:09:59 PM PDT 24
Peak memory 201696 kb
Host smart-64e26959-8d19-4887-95d5-f2dfefed4ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695520967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
695520967
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3954144308
Short name T269
Test name
Test status
Simulation time 44555234165 ps
CPU time 105.89 seconds
Started Aug 04 04:59:08 PM PDT 24
Finished Aug 04 05:00:54 PM PDT 24
Peak memory 209700 kb
Host smart-6b7082bd-390e-4079-b17b-7089260a4091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954144308 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3954144308
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.4124385377
Short name T713
Test name
Test status
Simulation time 451924254 ps
CPU time 1.63 seconds
Started Aug 04 04:59:11 PM PDT 24
Finished Aug 04 04:59:13 PM PDT 24
Peak memory 201144 kb
Host smart-11ee9549-957a-4905-b4e9-efb8f0b4717f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124385377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.4124385377
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3099237338
Short name T24
Test name
Test status
Simulation time 162580247179 ps
CPU time 97.98 seconds
Started Aug 04 04:59:10 PM PDT 24
Finished Aug 04 05:00:48 PM PDT 24
Peak memory 201472 kb
Host smart-e6a590c1-faef-4d6a-8d6b-a83f4f1b85a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099237338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3099237338
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3430931747
Short name T208
Test name
Test status
Simulation time 161675524952 ps
CPU time 200.33 seconds
Started Aug 04 04:59:07 PM PDT 24
Finished Aug 04 05:02:27 PM PDT 24
Peak memory 201400 kb
Host smart-2e2e2f7b-961b-43f3-879d-430923237f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430931747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3430931747
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1820830892
Short name T600
Test name
Test status
Simulation time 335464151904 ps
CPU time 687.9 seconds
Started Aug 04 04:59:08 PM PDT 24
Finished Aug 04 05:10:37 PM PDT 24
Peak memory 201312 kb
Host smart-17fe1eca-a29b-4099-9931-b7504650baeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820830892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1820830892
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2310652097
Short name T307
Test name
Test status
Simulation time 490886328333 ps
CPU time 1180.52 seconds
Started Aug 04 04:59:09 PM PDT 24
Finished Aug 04 05:18:49 PM PDT 24
Peak memory 201352 kb
Host smart-b62fff8a-64cd-4567-b06b-a2d273ca57eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310652097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2310652097
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2523834909
Short name T413
Test name
Test status
Simulation time 169341937495 ps
CPU time 411.56 seconds
Started Aug 04 04:59:06 PM PDT 24
Finished Aug 04 05:05:58 PM PDT 24
Peak memory 201324 kb
Host smart-f6e822c3-cc00-46b1-8724-69070fdddc63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523834909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2523834909
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.4137713311
Short name T571
Test name
Test status
Simulation time 199374242112 ps
CPU time 63.28 seconds
Started Aug 04 04:59:12 PM PDT 24
Finished Aug 04 05:00:15 PM PDT 24
Peak memory 201412 kb
Host smart-f919262d-521d-479e-a6e3-4cb57f59e29b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137713311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.4137713311
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.448833633
Short name T735
Test name
Test status
Simulation time 201888734054 ps
CPU time 449.24 seconds
Started Aug 04 04:59:11 PM PDT 24
Finished Aug 04 05:06:40 PM PDT 24
Peak memory 201348 kb
Host smart-8fe3b5b6-6479-49ac-822e-6da2ba0d2fe9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448833633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.448833633
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.978218606
Short name T92
Test name
Test status
Simulation time 80832578659 ps
CPU time 294.72 seconds
Started Aug 04 04:59:11 PM PDT 24
Finished Aug 04 05:04:06 PM PDT 24
Peak memory 201792 kb
Host smart-e37303d7-1108-4f3a-b90b-c5d543a4e7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978218606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.978218606
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1687868038
Short name T648
Test name
Test status
Simulation time 22528089348 ps
CPU time 53.91 seconds
Started Aug 04 04:59:13 PM PDT 24
Finished Aug 04 05:00:07 PM PDT 24
Peak memory 201292 kb
Host smart-031d659e-11be-4349-8dfa-3ae3b8c99599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687868038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1687868038
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4089237252
Short name T588
Test name
Test status
Simulation time 5035796608 ps
CPU time 6.34 seconds
Started Aug 04 04:59:14 PM PDT 24
Finished Aug 04 04:59:21 PM PDT 24
Peak memory 201252 kb
Host smart-9a19887b-3dbb-4e38-88ad-ba50052e370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089237252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4089237252
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.753533016
Short name T540
Test name
Test status
Simulation time 5836288035 ps
CPU time 14.5 seconds
Started Aug 04 04:59:06 PM PDT 24
Finished Aug 04 04:59:20 PM PDT 24
Peak memory 201304 kb
Host smart-3a403e0b-f230-48e1-8f76-56717064cf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753533016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.753533016
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1447322223
Short name T304
Test name
Test status
Simulation time 181033008395 ps
CPU time 103.52 seconds
Started Aug 04 04:59:14 PM PDT 24
Finished Aug 04 05:00:57 PM PDT 24
Peak memory 201360 kb
Host smart-aefc5dbd-31f7-442e-8cb4-b3195f3b60c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447322223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1447322223
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1628164662
Short name T20
Test name
Test status
Simulation time 93116773901 ps
CPU time 209.58 seconds
Started Aug 04 04:59:13 PM PDT 24
Finished Aug 04 05:02:42 PM PDT 24
Peak memory 209664 kb
Host smart-0306ccfd-e499-4d98-b6e5-13de45428371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628164662 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1628164662
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1298906295
Short name T606
Test name
Test status
Simulation time 343049204 ps
CPU time 0.72 seconds
Started Aug 04 04:59:18 PM PDT 24
Finished Aug 04 04:59:19 PM PDT 24
Peak memory 201092 kb
Host smart-7ae1deda-b415-4d3e-9a96-5b9b46d8d3eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298906295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1298906295
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.4246776034
Short name T259
Test name
Test status
Simulation time 187678055126 ps
CPU time 423.24 seconds
Started Aug 04 04:59:14 PM PDT 24
Finished Aug 04 05:06:18 PM PDT 24
Peak memory 201356 kb
Host smart-3bbfacf7-bad4-45cf-8c5b-77d7cba0dfbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246776034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.4246776034
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2407461069
Short name T249
Test name
Test status
Simulation time 178857126915 ps
CPU time 364.83 seconds
Started Aug 04 04:59:16 PM PDT 24
Finished Aug 04 05:05:21 PM PDT 24
Peak memory 201316 kb
Host smart-e16c7d09-63cc-4c3b-ad1b-2214c300c3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407461069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2407461069
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2665557518
Short name T153
Test name
Test status
Simulation time 493841101883 ps
CPU time 315.04 seconds
Started Aug 04 04:59:17 PM PDT 24
Finished Aug 04 05:04:32 PM PDT 24
Peak memory 201320 kb
Host smart-1ad23ba2-20af-4e7a-8fef-e67a9598df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665557518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2665557518
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1957230237
Short name T752
Test name
Test status
Simulation time 324329740405 ps
CPU time 209.78 seconds
Started Aug 04 04:59:15 PM PDT 24
Finished Aug 04 05:02:45 PM PDT 24
Peak memory 201380 kb
Host smart-cca1e576-f398-479d-8a9b-c7197808bff7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957230237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1957230237
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2703806385
Short name T497
Test name
Test status
Simulation time 161473454455 ps
CPU time 194.9 seconds
Started Aug 04 04:59:15 PM PDT 24
Finished Aug 04 05:02:30 PM PDT 24
Peak memory 201388 kb
Host smart-6890168c-8bd0-4a8a-9f31-848cd18e590b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703806385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2703806385
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4013287778
Short name T200
Test name
Test status
Simulation time 186164424416 ps
CPU time 429.82 seconds
Started Aug 04 04:59:15 PM PDT 24
Finished Aug 04 05:06:25 PM PDT 24
Peak memory 201340 kb
Host smart-9e9484d7-5273-4854-a4f3-d028ffa2abdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013287778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4013287778
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1898822594
Short name T526
Test name
Test status
Simulation time 611818674670 ps
CPU time 513.25 seconds
Started Aug 04 04:59:16 PM PDT 24
Finished Aug 04 05:07:49 PM PDT 24
Peak memory 201376 kb
Host smart-d5b61fca-e7ff-45f0-83d7-a2b14a084e44
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898822594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1898822594
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2137130755
Short name T50
Test name
Test status
Simulation time 76264089177 ps
CPU time 413.25 seconds
Started Aug 04 04:59:17 PM PDT 24
Finished Aug 04 05:06:11 PM PDT 24
Peak memory 201728 kb
Host smart-84db0081-231b-4659-aac4-b9cc50bab03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137130755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2137130755
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3458921339
Short name T430
Test name
Test status
Simulation time 25736540627 ps
CPU time 15 seconds
Started Aug 04 04:59:19 PM PDT 24
Finished Aug 04 04:59:34 PM PDT 24
Peak memory 201292 kb
Host smart-811c870c-cb8d-436d-9c77-7f3d4c7f6832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458921339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3458921339
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4153319616
Short name T534
Test name
Test status
Simulation time 5416044230 ps
CPU time 3.07 seconds
Started Aug 04 04:59:17 PM PDT 24
Finished Aug 04 04:59:20 PM PDT 24
Peak memory 201340 kb
Host smart-c2054c8c-5644-45fb-a60f-489c6528154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153319616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4153319616
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3754053268
Short name T402
Test name
Test status
Simulation time 5982882519 ps
CPU time 3.01 seconds
Started Aug 04 04:59:15 PM PDT 24
Finished Aug 04 04:59:18 PM PDT 24
Peak memory 201228 kb
Host smart-1a71d210-4e15-4dea-92e0-58ec902b7350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754053268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3754053268
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.4105825695
Short name T313
Test name
Test status
Simulation time 1141655028230 ps
CPU time 904.24 seconds
Started Aug 04 04:59:18 PM PDT 24
Finished Aug 04 05:14:23 PM PDT 24
Peak memory 212016 kb
Host smart-36bf6b80-5eee-467f-a51c-fc3ef4a38f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105825695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.4105825695
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.990824053
Short name T19
Test name
Test status
Simulation time 59719884991 ps
CPU time 134.28 seconds
Started Aug 04 04:59:19 PM PDT 24
Finished Aug 04 05:01:33 PM PDT 24
Peak memory 217372 kb
Host smart-c1999212-b6f0-4efd-83a0-5688cce438c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990824053 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.990824053
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1213857004
Short name T707
Test name
Test status
Simulation time 528149115 ps
CPU time 1 seconds
Started Aug 04 04:59:29 PM PDT 24
Finished Aug 04 04:59:30 PM PDT 24
Peak memory 201204 kb
Host smart-1e55ee6a-b334-48e1-98a7-e1767b2909b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213857004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1213857004
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2729816986
Short name T135
Test name
Test status
Simulation time 170612194159 ps
CPU time 182.63 seconds
Started Aug 04 04:59:26 PM PDT 24
Finished Aug 04 05:02:29 PM PDT 24
Peak memory 201412 kb
Host smart-702cc724-48c6-41d8-865e-558388b67ecf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729816986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2729816986
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2763760839
Short name T84
Test name
Test status
Simulation time 344330849056 ps
CPU time 104.58 seconds
Started Aug 04 04:59:27 PM PDT 24
Finished Aug 04 05:01:12 PM PDT 24
Peak memory 201272 kb
Host smart-139724f3-8658-4ac1-9f73-72b69e512ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763760839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2763760839
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1928879642
Short name T661
Test name
Test status
Simulation time 495456112392 ps
CPU time 288.02 seconds
Started Aug 04 04:59:23 PM PDT 24
Finished Aug 04 05:04:11 PM PDT 24
Peak memory 201400 kb
Host smart-a9a27a20-912d-4c96-92bf-9b8ca8f762db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928879642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1928879642
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2600382292
Short name T734
Test name
Test status
Simulation time 339223902220 ps
CPU time 209.38 seconds
Started Aug 04 04:59:21 PM PDT 24
Finished Aug 04 05:02:51 PM PDT 24
Peak memory 201344 kb
Host smart-49ad1ae2-5626-4428-94b7-04e440eb58cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600382292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2600382292
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1932574531
Short name T776
Test name
Test status
Simulation time 166642874914 ps
CPU time 214.32 seconds
Started Aug 04 04:59:18 PM PDT 24
Finished Aug 04 05:02:53 PM PDT 24
Peak memory 201432 kb
Host smart-3cd15036-4ace-4d38-8a5b-36ace1cfcae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932574531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1932574531
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2448701361
Short name T390
Test name
Test status
Simulation time 331694847742 ps
CPU time 207.11 seconds
Started Aug 04 04:59:18 PM PDT 24
Finished Aug 04 05:02:46 PM PDT 24
Peak memory 201332 kb
Host smart-1112418d-399d-4447-bf3c-ed05993be12b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448701361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2448701361
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.542265218
Short name T251
Test name
Test status
Simulation time 352540652164 ps
CPU time 735.35 seconds
Started Aug 04 04:59:23 PM PDT 24
Finished Aug 04 05:11:39 PM PDT 24
Peak memory 201636 kb
Host smart-b69021be-d269-4e94-80c1-2daa231e9876
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542265218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.542265218
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.129356119
Short name T49
Test name
Test status
Simulation time 196739815971 ps
CPU time 108.74 seconds
Started Aug 04 04:59:29 PM PDT 24
Finished Aug 04 05:01:17 PM PDT 24
Peak memory 201296 kb
Host smart-337ed8bd-212c-4761-a1c3-af14d25703ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129356119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.129356119
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3385403471
Short name T427
Test name
Test status
Simulation time 124924537861 ps
CPU time 643.37 seconds
Started Aug 04 04:59:28 PM PDT 24
Finished Aug 04 05:10:12 PM PDT 24
Peak memory 201720 kb
Host smart-31a7eec6-7efe-4587-880e-ee977e2dcbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385403471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3385403471
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3144292590
Short name T609
Test name
Test status
Simulation time 42185317314 ps
CPU time 25.62 seconds
Started Aug 04 04:59:27 PM PDT 24
Finished Aug 04 04:59:53 PM PDT 24
Peak memory 201208 kb
Host smart-ef47df60-dc5b-4034-a6e9-1b96130256a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144292590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3144292590
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.990084677
Short name T103
Test name
Test status
Simulation time 5091436186 ps
CPU time 11.45 seconds
Started Aug 04 04:59:25 PM PDT 24
Finished Aug 04 04:59:37 PM PDT 24
Peak memory 201308 kb
Host smart-082df590-98a8-4bc0-959e-41198eb1f7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990084677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.990084677
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.525310761
Short name T410
Test name
Test status
Simulation time 5630173002 ps
CPU time 14.5 seconds
Started Aug 04 04:59:20 PM PDT 24
Finished Aug 04 04:59:34 PM PDT 24
Peak memory 201540 kb
Host smart-ae65ab0b-d1c7-4993-ace7-f2e9e546bc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525310761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.525310761
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3128373483
Short name T645
Test name
Test status
Simulation time 338484128 ps
CPU time 1.41 seconds
Started Aug 04 04:59:40 PM PDT 24
Finished Aug 04 04:59:41 PM PDT 24
Peak memory 201172 kb
Host smart-b12a93d9-a6e8-4eb0-af3f-78b161a0b6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128373483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3128373483
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3461267820
Short name T227
Test name
Test status
Simulation time 185630184511 ps
CPU time 73.8 seconds
Started Aug 04 04:59:31 PM PDT 24
Finished Aug 04 05:00:45 PM PDT 24
Peak memory 201372 kb
Host smart-a9a36f8e-8b9c-4fa0-b924-af94ab1a282d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461267820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3461267820
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1608758636
Short name T44
Test name
Test status
Simulation time 162248802727 ps
CPU time 173.93 seconds
Started Aug 04 04:59:32 PM PDT 24
Finished Aug 04 05:02:26 PM PDT 24
Peak memory 201412 kb
Host smart-3feb6e5c-b2a2-4660-a3c8-fd444f20c64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608758636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1608758636
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.576708651
Short name T523
Test name
Test status
Simulation time 488124972024 ps
CPU time 1073.35 seconds
Started Aug 04 04:59:31 PM PDT 24
Finished Aug 04 05:17:25 PM PDT 24
Peak memory 201420 kb
Host smart-ac4bf392-5f7d-4921-b162-bb632aa32cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576708651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.576708651
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1762365713
Short name T398
Test name
Test status
Simulation time 489403511385 ps
CPU time 605.47 seconds
Started Aug 04 04:59:31 PM PDT 24
Finished Aug 04 05:09:37 PM PDT 24
Peak memory 201396 kb
Host smart-efaba743-7b5e-43b1-845b-02c3bee3e9e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762365713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1762365713
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1394502753
Short name T142
Test name
Test status
Simulation time 161099735858 ps
CPU time 168.43 seconds
Started Aug 04 04:59:29 PM PDT 24
Finished Aug 04 05:02:18 PM PDT 24
Peak memory 201348 kb
Host smart-e5c961a7-e440-4970-b9cb-ecbd4467cab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394502753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1394502753
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1032390492
Short name T366
Test name
Test status
Simulation time 481943206582 ps
CPU time 240.18 seconds
Started Aug 04 04:59:29 PM PDT 24
Finished Aug 04 05:03:29 PM PDT 24
Peak memory 201396 kb
Host smart-2e92642b-278b-4f60-b02e-d4b01e3b04e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032390492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1032390492
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3870032814
Short name T201
Test name
Test status
Simulation time 624458782421 ps
CPU time 1486.69 seconds
Started Aug 04 04:59:32 PM PDT 24
Finished Aug 04 05:24:19 PM PDT 24
Peak memory 201408 kb
Host smart-47192651-81b3-4567-acde-2e3be34877b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870032814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3870032814
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4153956015
Short name T702
Test name
Test status
Simulation time 391429007148 ps
CPU time 213.57 seconds
Started Aug 04 04:59:32 PM PDT 24
Finished Aug 04 05:03:06 PM PDT 24
Peak memory 201704 kb
Host smart-647f86a1-578e-4a2e-b98b-f49a17e84c05
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153956015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.4153956015
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2649173323
Short name T679
Test name
Test status
Simulation time 114949922663 ps
CPU time 416.84 seconds
Started Aug 04 04:59:35 PM PDT 24
Finished Aug 04 05:06:32 PM PDT 24
Peak memory 201688 kb
Host smart-e8f7a335-4ef4-4a0f-94ff-5fbb8c53ac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649173323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2649173323
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1959505802
Short name T773
Test name
Test status
Simulation time 30703663043 ps
CPU time 73.52 seconds
Started Aug 04 04:59:35 PM PDT 24
Finished Aug 04 05:00:49 PM PDT 24
Peak memory 201296 kb
Host smart-266a08ca-9da6-45de-aa58-387f1d7aaa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959505802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1959505802
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.241845252
Short name T659
Test name
Test status
Simulation time 2898247935 ps
CPU time 1.49 seconds
Started Aug 04 04:59:36 PM PDT 24
Finished Aug 04 04:59:38 PM PDT 24
Peak memory 201220 kb
Host smart-156067db-0230-477a-8fe1-639a42966659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241845252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.241845252
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2431656452
Short name T727
Test name
Test status
Simulation time 5877136206 ps
CPU time 4.34 seconds
Started Aug 04 04:59:30 PM PDT 24
Finished Aug 04 04:59:34 PM PDT 24
Peak memory 201248 kb
Host smart-268a3163-1374-47b9-9e08-0daaab22d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431656452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2431656452
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3169905795
Short name T90
Test name
Test status
Simulation time 195017450471 ps
CPU time 218.05 seconds
Started Aug 04 04:59:41 PM PDT 24
Finished Aug 04 05:03:19 PM PDT 24
Peak memory 201380 kb
Host smart-9c8cef28-5266-4173-b828-4165116114f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169905795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3169905795
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3267081712
Short name T155
Test name
Test status
Simulation time 160652046400 ps
CPU time 324.24 seconds
Started Aug 04 04:59:40 PM PDT 24
Finished Aug 04 05:05:04 PM PDT 24
Peak memory 210100 kb
Host smart-47754b55-35b9-4051-84bb-c288568e41fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267081712 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3267081712
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3876549361
Short name T382
Test name
Test status
Simulation time 533146231 ps
CPU time 1.79 seconds
Started Aug 04 04:57:55 PM PDT 24
Finished Aug 04 04:57:57 PM PDT 24
Peak memory 201152 kb
Host smart-550e51c7-d05c-4bd3-b84d-54454961c83f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876549361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3876549361
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1359466291
Short name T257
Test name
Test status
Simulation time 534109070424 ps
CPU time 246.93 seconds
Started Aug 04 04:57:52 PM PDT 24
Finished Aug 04 05:01:59 PM PDT 24
Peak memory 201324 kb
Host smart-be7ecec9-53ab-4fa6-bfe8-f92963ba87af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359466291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1359466291
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.642919605
Short name T241
Test name
Test status
Simulation time 324107388885 ps
CPU time 730.71 seconds
Started Aug 04 04:57:48 PM PDT 24
Finished Aug 04 05:09:59 PM PDT 24
Peak memory 201368 kb
Host smart-d84a5a18-2927-4a84-93ad-9b960030e8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642919605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.642919605
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2442754539
Short name T163
Test name
Test status
Simulation time 325180389664 ps
CPU time 84.42 seconds
Started Aug 04 04:57:50 PM PDT 24
Finished Aug 04 04:59:14 PM PDT 24
Peak memory 201348 kb
Host smart-ce896255-3939-4e95-b73e-5ad7871ac7c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442754539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2442754539
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3862242253
Short name T440
Test name
Test status
Simulation time 484769986465 ps
CPU time 581.67 seconds
Started Aug 04 04:57:50 PM PDT 24
Finished Aug 04 05:07:31 PM PDT 24
Peak memory 201280 kb
Host smart-526cbbec-cbb2-4980-a87d-a8dac7a39a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862242253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3862242253
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2380922207
Short name T597
Test name
Test status
Simulation time 508460170488 ps
CPU time 709.46 seconds
Started Aug 04 04:57:48 PM PDT 24
Finished Aug 04 05:09:37 PM PDT 24
Peak memory 201380 kb
Host smart-6a98b2fd-672b-48df-944f-ecdf36077305
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380922207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2380922207
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.268188561
Short name T589
Test name
Test status
Simulation time 405414849554 ps
CPU time 399.62 seconds
Started Aug 04 04:57:57 PM PDT 24
Finished Aug 04 05:04:37 PM PDT 24
Peak memory 201360 kb
Host smart-cf33f28d-3fd5-4360-99fd-694b8a7a63e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268188561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.268188561
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.4208582911
Short name T500
Test name
Test status
Simulation time 86494763708 ps
CPU time 462.19 seconds
Started Aug 04 04:57:52 PM PDT 24
Finished Aug 04 05:05:34 PM PDT 24
Peak memory 201752 kb
Host smart-dc8f0cb2-9215-4230-a323-e9655f36d48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208582911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.4208582911
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1446019311
Short name T22
Test name
Test status
Simulation time 25870376758 ps
CPU time 60.29 seconds
Started Aug 04 04:57:55 PM PDT 24
Finished Aug 04 04:58:56 PM PDT 24
Peak memory 201284 kb
Host smart-21a887cf-de68-43dc-8eba-8249d4a97cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446019311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1446019311
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.703768417
Short name T409
Test name
Test status
Simulation time 2776441537 ps
CPU time 7.04 seconds
Started Aug 04 04:57:52 PM PDT 24
Finished Aug 04 04:57:59 PM PDT 24
Peak memory 201248 kb
Host smart-ad2e924c-e923-450c-8780-f6d0d8baa69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703768417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.703768417
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4053739025
Short name T343
Test name
Test status
Simulation time 5862312372 ps
CPU time 14.81 seconds
Started Aug 04 04:57:49 PM PDT 24
Finished Aug 04 04:58:04 PM PDT 24
Peak memory 201208 kb
Host smart-7ed017e0-c242-45b3-bcd2-135d91fc5b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053739025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4053739025
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3777834168
Short name T772
Test name
Test status
Simulation time 708884041775 ps
CPU time 295 seconds
Started Aug 04 04:57:57 PM PDT 24
Finished Aug 04 05:02:52 PM PDT 24
Peak memory 201380 kb
Host smart-4c476116-68d0-45ed-9fc5-f8b01f88a031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777834168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3777834168
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.414626429
Short name T109
Test name
Test status
Simulation time 9824957207 ps
CPU time 25.3 seconds
Started Aug 04 04:57:57 PM PDT 24
Finished Aug 04 04:58:23 PM PDT 24
Peak memory 211300 kb
Host smart-e5743507-f8ad-4d7a-b252-2291d49edda1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414626429 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.414626429
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2667393754
Short name T353
Test name
Test status
Simulation time 427704757 ps
CPU time 0.77 seconds
Started Aug 04 04:59:53 PM PDT 24
Finished Aug 04 04:59:54 PM PDT 24
Peak memory 201092 kb
Host smart-5f609b99-7d81-43a5-8e84-87620f51f3a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667393754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2667393754
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4104210787
Short name T250
Test name
Test status
Simulation time 331627650682 ps
CPU time 779.54 seconds
Started Aug 04 04:59:53 PM PDT 24
Finished Aug 04 05:12:52 PM PDT 24
Peak memory 201404 kb
Host smart-a56711e1-6197-40b1-ad7e-6e816789aec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104210787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4104210787
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.701794895
Short name T176
Test name
Test status
Simulation time 322991421448 ps
CPU time 178.31 seconds
Started Aug 04 04:59:44 PM PDT 24
Finished Aug 04 05:02:43 PM PDT 24
Peak memory 201368 kb
Host smart-4a9cd61c-2469-4ce2-bded-3d5ddee2a654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701794895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.701794895
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.4232678178
Short name T775
Test name
Test status
Simulation time 497712023642 ps
CPU time 1156.86 seconds
Started Aug 04 04:59:50 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201372 kb
Host smart-3a11b344-2e64-476e-9e32-1c9caba56b5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232678178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.4232678178
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.413838491
Short name T417
Test name
Test status
Simulation time 333681540781 ps
CPU time 196.5 seconds
Started Aug 04 04:59:45 PM PDT 24
Finished Aug 04 05:03:01 PM PDT 24
Peak memory 201320 kb
Host smart-8bfd9095-49e2-4791-a10b-7fce4464c4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413838491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.413838491
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.475747226
Short name T601
Test name
Test status
Simulation time 163767435806 ps
CPU time 399.83 seconds
Started Aug 04 04:59:46 PM PDT 24
Finished Aug 04 05:06:26 PM PDT 24
Peak memory 201244 kb
Host smart-f21a00c0-0522-4e4c-8603-1c961114c935
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=475747226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.475747226
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2359604140
Short name T296
Test name
Test status
Simulation time 597107308520 ps
CPU time 323.44 seconds
Started Aug 04 04:59:51 PM PDT 24
Finished Aug 04 05:05:15 PM PDT 24
Peak memory 201404 kb
Host smart-62f597c9-2704-4a9e-b1f0-9c234b267413
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359604140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2359604140
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.562033192
Short name T415
Test name
Test status
Simulation time 414299342503 ps
CPU time 470.82 seconds
Started Aug 04 04:59:49 PM PDT 24
Finished Aug 04 05:07:40 PM PDT 24
Peak memory 201364 kb
Host smart-0aed2179-a637-4a3a-9afa-ebc0a1cb1fc9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562033192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.562033192
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1128880201
Short name T416
Test name
Test status
Simulation time 38159672345 ps
CPU time 46.53 seconds
Started Aug 04 04:59:54 PM PDT 24
Finished Aug 04 05:00:41 PM PDT 24
Peak memory 201320 kb
Host smart-dc2cf664-95c4-4b72-b1f0-dea9ee139135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128880201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1128880201
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3515082313
Short name T577
Test name
Test status
Simulation time 4918396248 ps
CPU time 10.83 seconds
Started Aug 04 04:59:53 PM PDT 24
Finished Aug 04 05:00:04 PM PDT 24
Peak memory 201328 kb
Host smart-cd550265-569e-4b4a-a440-6ac856768cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515082313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3515082313
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1673876041
Short name T436
Test name
Test status
Simulation time 5998967054 ps
CPU time 5.54 seconds
Started Aug 04 04:59:41 PM PDT 24
Finished Aug 04 04:59:46 PM PDT 24
Peak memory 201288 kb
Host smart-7e922ac0-e205-460d-97ba-135e51200731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673876041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1673876041
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2290129941
Short name T748
Test name
Test status
Simulation time 253994452368 ps
CPU time 151.12 seconds
Started Aug 04 04:59:53 PM PDT 24
Finished Aug 04 05:02:24 PM PDT 24
Peak memory 209740 kb
Host smart-bf05d2e7-fe4f-41eb-8ff2-a13411b0fc27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290129941 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2290129941
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3556250349
Short name T635
Test name
Test status
Simulation time 405635015 ps
CPU time 0.85 seconds
Started Aug 04 05:00:07 PM PDT 24
Finished Aug 04 05:00:08 PM PDT 24
Peak memory 201204 kb
Host smart-13dc6408-67cb-45b6-a8ac-0f137f596b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556250349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3556250349
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2207307839
Short name T671
Test name
Test status
Simulation time 338891494776 ps
CPU time 194.57 seconds
Started Aug 04 05:00:05 PM PDT 24
Finished Aug 04 05:03:20 PM PDT 24
Peak memory 201332 kb
Host smart-b7694a71-1cc4-4fb9-8ae0-7d675baf10a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207307839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2207307839
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.990946571
Short name T159
Test name
Test status
Simulation time 334160865097 ps
CPU time 107.77 seconds
Started Aug 04 05:00:05 PM PDT 24
Finished Aug 04 05:01:53 PM PDT 24
Peak memory 201288 kb
Host smart-6ec1828d-acb9-4acc-b9e3-4d6ad3527ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990946571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.990946571
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1508898395
Short name T302
Test name
Test status
Simulation time 484212818268 ps
CPU time 270.89 seconds
Started Aug 04 04:59:57 PM PDT 24
Finished Aug 04 05:04:28 PM PDT 24
Peak memory 201348 kb
Host smart-ef7f8744-3ecd-4374-9b26-abf3e04b24c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508898395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1508898395
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.679488397
Short name T342
Test name
Test status
Simulation time 492030410712 ps
CPU time 684.92 seconds
Started Aug 04 05:00:01 PM PDT 24
Finished Aug 04 05:11:26 PM PDT 24
Peak memory 201324 kb
Host smart-c4c87ee6-98f6-4c1e-97a8-acd4b110d4d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=679488397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.679488397
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1099817748
Short name T729
Test name
Test status
Simulation time 328099462351 ps
CPU time 739.08 seconds
Started Aug 04 04:59:56 PM PDT 24
Finished Aug 04 05:12:16 PM PDT 24
Peak memory 201380 kb
Host smart-a06c7dd3-50a5-4cac-82dc-f9d8162a96a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099817748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1099817748
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2562547955
Short name T389
Test name
Test status
Simulation time 162255844091 ps
CPU time 349.53 seconds
Started Aug 04 04:59:57 PM PDT 24
Finished Aug 04 05:05:46 PM PDT 24
Peak memory 201320 kb
Host smart-6ea8693f-43e4-4670-b37d-a4ecd139a64c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562547955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2562547955
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1433158521
Short name T475
Test name
Test status
Simulation time 383836774840 ps
CPU time 899.35 seconds
Started Aug 04 05:00:00 PM PDT 24
Finished Aug 04 05:15:00 PM PDT 24
Peak memory 201328 kb
Host smart-d9f23fa1-9895-46e6-b793-f9bad852a312
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433158521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1433158521
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3512426255
Short name T704
Test name
Test status
Simulation time 403246801478 ps
CPU time 235.42 seconds
Started Aug 04 05:00:01 PM PDT 24
Finished Aug 04 05:04:01 PM PDT 24
Peak memory 201336 kb
Host smart-d61b70b6-df89-497f-804b-dbbfef8a00e0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512426255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3512426255
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2476362192
Short name T185
Test name
Test status
Simulation time 99700828130 ps
CPU time 493.66 seconds
Started Aug 04 05:00:05 PM PDT 24
Finished Aug 04 05:08:19 PM PDT 24
Peak memory 201764 kb
Host smart-981b5199-5324-4b1d-a14b-44d3442903a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476362192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2476362192
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3265652398
Short name T339
Test name
Test status
Simulation time 44782747867 ps
CPU time 49.26 seconds
Started Aug 04 05:00:06 PM PDT 24
Finished Aug 04 05:00:55 PM PDT 24
Peak memory 201288 kb
Host smart-ce0d34b4-6f70-43c5-bd82-10d30744b02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265652398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3265652398
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1126834581
Short name T575
Test name
Test status
Simulation time 4690344321 ps
CPU time 10.77 seconds
Started Aug 04 05:00:05 PM PDT 24
Finished Aug 04 05:00:16 PM PDT 24
Peak memory 201300 kb
Host smart-9562931f-36f9-4789-986f-860a373d8554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126834581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1126834581
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3684551649
Short name T536
Test name
Test status
Simulation time 5714273427 ps
CPU time 13.71 seconds
Started Aug 04 04:59:57 PM PDT 24
Finished Aug 04 05:00:11 PM PDT 24
Peak memory 201228 kb
Host smart-51e99c05-65ed-4a80-bcaf-ac5df337f9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684551649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3684551649
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3516474408
Short name T279
Test name
Test status
Simulation time 496061556445 ps
CPU time 371.37 seconds
Started Aug 04 05:00:05 PM PDT 24
Finished Aug 04 05:06:17 PM PDT 24
Peak memory 201456 kb
Host smart-cc763761-aafb-4fd9-90d1-76f318635b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516474408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3516474408
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1311945378
Short name T446
Test name
Test status
Simulation time 40549999900 ps
CPU time 106.03 seconds
Started Aug 04 05:00:05 PM PDT 24
Finished Aug 04 05:01:52 PM PDT 24
Peak memory 210096 kb
Host smart-d250e9b3-81ba-484e-8ff1-06791859d241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311945378 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1311945378
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4036112268
Short name T469
Test name
Test status
Simulation time 289376881 ps
CPU time 0.91 seconds
Started Aug 04 05:00:17 PM PDT 24
Finished Aug 04 05:00:18 PM PDT 24
Peak memory 201120 kb
Host smart-9aaaebe1-fdc1-4afc-a19e-96fadd47508c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036112268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4036112268
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.19986038
Short name T706
Test name
Test status
Simulation time 170803888860 ps
CPU time 2.52 seconds
Started Aug 04 05:00:12 PM PDT 24
Finished Aug 04 05:00:15 PM PDT 24
Peak memory 201404 kb
Host smart-8b6fbb2e-ec2a-425f-b1b1-29cfda3aeefc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19986038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gatin
g.19986038
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.34960227
Short name T294
Test name
Test status
Simulation time 492061726988 ps
CPU time 1178.32 seconds
Started Aug 04 05:00:10 PM PDT 24
Finished Aug 04 05:19:49 PM PDT 24
Peak memory 201332 kb
Host smart-ce8aea89-45d7-412e-beb2-cbdbd955ff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34960227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.34960227
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3208150743
Short name T543
Test name
Test status
Simulation time 162361005917 ps
CPU time 340.87 seconds
Started Aug 04 05:00:10 PM PDT 24
Finished Aug 04 05:05:51 PM PDT 24
Peak memory 201380 kb
Host smart-f800173e-ec03-46d3-9f93-13b399ce0bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208150743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3208150743
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.281243560
Short name T581
Test name
Test status
Simulation time 164390438424 ps
CPU time 370.23 seconds
Started Aug 04 05:00:09 PM PDT 24
Finished Aug 04 05:06:19 PM PDT 24
Peak memory 201376 kb
Host smart-fab14f7b-1579-41c8-b6da-4e7570de8cab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=281243560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.281243560
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2952772299
Short name T750
Test name
Test status
Simulation time 167447897510 ps
CPU time 360.63 seconds
Started Aug 04 05:00:08 PM PDT 24
Finished Aug 04 05:06:09 PM PDT 24
Peak memory 201372 kb
Host smart-b2ed3139-a5dc-4945-afa2-83493b053739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952772299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2952772299
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2045945483
Short name T370
Test name
Test status
Simulation time 160258051175 ps
CPU time 68 seconds
Started Aug 04 05:00:10 PM PDT 24
Finished Aug 04 05:01:18 PM PDT 24
Peak memory 201356 kb
Host smart-1a26f22a-a5b1-489a-9b00-e10333c7f4f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045945483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2045945483
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.858135212
Short name T273
Test name
Test status
Simulation time 192925649253 ps
CPU time 115.31 seconds
Started Aug 04 05:00:09 PM PDT 24
Finished Aug 04 05:02:04 PM PDT 24
Peak memory 201396 kb
Host smart-f3474510-5986-47ac-b1d4-b534ba6c8fbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858135212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.858135212
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.309070233
Short name T584
Test name
Test status
Simulation time 615884815090 ps
CPU time 1267.74 seconds
Started Aug 04 05:00:11 PM PDT 24
Finished Aug 04 05:21:19 PM PDT 24
Peak memory 201360 kb
Host smart-393532c0-b0bc-4c2b-881a-c11d5f604ac3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309070233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.309070233
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.4162536061
Short name T687
Test name
Test status
Simulation time 84175300024 ps
CPU time 303.74 seconds
Started Aug 04 05:00:15 PM PDT 24
Finished Aug 04 05:05:19 PM PDT 24
Peak memory 201700 kb
Host smart-0ec88c89-85b1-4528-aecb-c277b726e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162536061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.4162536061
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.492438953
Short name T701
Test name
Test status
Simulation time 40607912676 ps
CPU time 96.46 seconds
Started Aug 04 05:00:13 PM PDT 24
Finished Aug 04 05:01:49 PM PDT 24
Peak memory 201288 kb
Host smart-7621c3e6-041b-432b-8ee7-b352a800d90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492438953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.492438953
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.822227304
Short name T4
Test name
Test status
Simulation time 2711147167 ps
CPU time 2.66 seconds
Started Aug 04 05:00:13 PM PDT 24
Finished Aug 04 05:00:16 PM PDT 24
Peak memory 201288 kb
Host smart-9079acfc-71de-44aa-89c2-d6452ca73b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822227304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.822227304
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1821577340
Short name T611
Test name
Test status
Simulation time 5873409350 ps
CPU time 2.82 seconds
Started Aug 04 05:00:09 PM PDT 24
Finished Aug 04 05:00:12 PM PDT 24
Peak memory 201312 kb
Host smart-07d056a7-f909-455d-bee0-a60e1d0dd275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821577340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1821577340
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.858608646
Short name T311
Test name
Test status
Simulation time 192318049534 ps
CPU time 72.83 seconds
Started Aug 04 05:00:18 PM PDT 24
Finished Aug 04 05:01:31 PM PDT 24
Peak memory 201400 kb
Host smart-04262d81-b357-45b5-8759-de67471e329c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858608646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
858608646
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3450323178
Short name T100
Test name
Test status
Simulation time 110264396851 ps
CPU time 153.95 seconds
Started Aug 04 05:00:18 PM PDT 24
Finished Aug 04 05:02:52 PM PDT 24
Peak memory 217540 kb
Host smart-696c3b2c-cbb0-4b37-b5e2-67824897d189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450323178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3450323178
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3265036368
Short name T779
Test name
Test status
Simulation time 295195888 ps
CPU time 1.2 seconds
Started Aug 04 05:00:36 PM PDT 24
Finished Aug 04 05:00:37 PM PDT 24
Peak memory 201152 kb
Host smart-893d0188-4d9c-4bb7-a555-121597d9b1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265036368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3265036368
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.762202145
Short name T743
Test name
Test status
Simulation time 176643064571 ps
CPU time 365.34 seconds
Started Aug 04 05:00:26 PM PDT 24
Finished Aug 04 05:06:31 PM PDT 24
Peak memory 201360 kb
Host smart-be220e59-11d3-4fa9-8179-ffaf6fdc7d57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762202145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.762202145
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3340888989
Short name T281
Test name
Test status
Simulation time 487178095751 ps
CPU time 592.78 seconds
Started Aug 04 05:00:21 PM PDT 24
Finished Aug 04 05:10:14 PM PDT 24
Peak memory 201392 kb
Host smart-36848aff-46b8-4442-8a52-d94ab257d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340888989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3340888989
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3346737621
Short name T350
Test name
Test status
Simulation time 484890606892 ps
CPU time 996.35 seconds
Started Aug 04 05:00:21 PM PDT 24
Finished Aug 04 05:16:58 PM PDT 24
Peak memory 201424 kb
Host smart-d264c180-2016-4423-a0b5-a0016b19c19c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346737621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3346737621
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3895591538
Short name T637
Test name
Test status
Simulation time 163989624806 ps
CPU time 378.71 seconds
Started Aug 04 05:00:21 PM PDT 24
Finished Aug 04 05:06:40 PM PDT 24
Peak memory 201344 kb
Host smart-cc44d83f-5934-4ae6-8d1f-815fe6cabe8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895591538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3895591538
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.4023578542
Short name T643
Test name
Test status
Simulation time 333211288829 ps
CPU time 384.73 seconds
Started Aug 04 05:00:21 PM PDT 24
Finished Aug 04 05:06:46 PM PDT 24
Peak memory 201396 kb
Host smart-e314e496-c67c-4750-ad7a-302d6671b78f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023578542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.4023578542
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3837323250
Short name T265
Test name
Test status
Simulation time 191096111720 ps
CPU time 218.86 seconds
Started Aug 04 05:00:24 PM PDT 24
Finished Aug 04 05:04:03 PM PDT 24
Peak memory 201400 kb
Host smart-61566b2f-579b-4a58-b94e-2cbfd204966d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837323250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3837323250
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.584612822
Short name T514
Test name
Test status
Simulation time 407877410511 ps
CPU time 137.66 seconds
Started Aug 04 05:00:26 PM PDT 24
Finished Aug 04 05:02:43 PM PDT 24
Peak memory 201364 kb
Host smart-2ab9b96a-68ef-47fa-999e-53051d07f42e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584612822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.584612822
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2559698689
Short name T191
Test name
Test status
Simulation time 96304860101 ps
CPU time 538.07 seconds
Started Aug 04 05:00:29 PM PDT 24
Finished Aug 04 05:09:27 PM PDT 24
Peak memory 201664 kb
Host smart-c9c5a7b1-9573-42b8-8fb5-721881ada354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559698689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2559698689
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2089490079
Short name T515
Test name
Test status
Simulation time 38824316472 ps
CPU time 89.22 seconds
Started Aug 04 05:00:27 PM PDT 24
Finished Aug 04 05:01:57 PM PDT 24
Peak memory 201212 kb
Host smart-608aa219-8ca5-4185-be8b-25520103c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089490079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2089490079
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2299889212
Short name T444
Test name
Test status
Simulation time 3179000124 ps
CPU time 2.44 seconds
Started Aug 04 05:00:29 PM PDT 24
Finished Aug 04 05:00:31 PM PDT 24
Peak memory 201288 kb
Host smart-402bdd2b-8419-49c6-853a-f67b5632a315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299889212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2299889212
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1896203705
Short name T567
Test name
Test status
Simulation time 6100978549 ps
CPU time 4.34 seconds
Started Aug 04 05:00:17 PM PDT 24
Finished Aug 04 05:00:21 PM PDT 24
Peak memory 201240 kb
Host smart-50011ce0-256d-4df9-baa4-e70e1f5e9332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896203705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1896203705
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2398011216
Short name T180
Test name
Test status
Simulation time 268639249446 ps
CPU time 817.97 seconds
Started Aug 04 05:00:36 PM PDT 24
Finished Aug 04 05:14:14 PM PDT 24
Peak memory 201712 kb
Host smart-c899f55b-1655-413e-9adc-25d35457acae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398011216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2398011216
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.941746611
Short name T327
Test name
Test status
Simulation time 134592255653 ps
CPU time 383.2 seconds
Started Aug 04 05:00:30 PM PDT 24
Finished Aug 04 05:06:53 PM PDT 24
Peak memory 210088 kb
Host smart-4d01f3ab-e5ef-4676-8876-5e8a4ca3f314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941746611 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.941746611
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1900697841
Short name T480
Test name
Test status
Simulation time 399261015 ps
CPU time 0.75 seconds
Started Aug 04 05:00:47 PM PDT 24
Finished Aug 04 05:00:48 PM PDT 24
Peak memory 201108 kb
Host smart-b3e4f9e5-5317-4cee-ab13-aac756459767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900697841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1900697841
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3682380875
Short name T196
Test name
Test status
Simulation time 166102307937 ps
CPU time 341.04 seconds
Started Aug 04 05:00:44 PM PDT 24
Finished Aug 04 05:06:25 PM PDT 24
Peak memory 201608 kb
Host smart-4f0236f1-1572-466b-a33d-7060346fb75b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682380875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3682380875
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2933001831
Short name T647
Test name
Test status
Simulation time 325297214285 ps
CPU time 177.18 seconds
Started Aug 04 05:00:40 PM PDT 24
Finished Aug 04 05:03:37 PM PDT 24
Peak memory 201388 kb
Host smart-5e1d412b-17a7-479c-bfe6-df0ca3e75ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933001831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2933001831
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1305745073
Short name T670
Test name
Test status
Simulation time 168221288044 ps
CPU time 51.33 seconds
Started Aug 04 05:00:40 PM PDT 24
Finished Aug 04 05:01:31 PM PDT 24
Peak memory 201388 kb
Host smart-ac3510cb-bf67-4487-b6bb-243a7c756091
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305745073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1305745073
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.374592571
Short name T574
Test name
Test status
Simulation time 159305236131 ps
CPU time 101.36 seconds
Started Aug 04 05:00:40 PM PDT 24
Finished Aug 04 05:02:21 PM PDT 24
Peak memory 201280 kb
Host smart-8de4d661-9691-4480-8006-024815dc396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374592571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.374592571
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3885642221
Short name T545
Test name
Test status
Simulation time 160348318391 ps
CPU time 183.21 seconds
Started Aug 04 05:00:39 PM PDT 24
Finished Aug 04 05:03:43 PM PDT 24
Peak memory 201284 kb
Host smart-3e02b3d8-cdd3-4cf6-a613-48e36a41c35f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885642221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3885642221
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1862993930
Short name T397
Test name
Test status
Simulation time 198853570419 ps
CPU time 205.35 seconds
Started Aug 04 05:00:40 PM PDT 24
Finished Aug 04 05:04:06 PM PDT 24
Peak memory 201324 kb
Host smart-592a1c22-e359-405a-a834-63087b4c27f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862993930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1862993930
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1498705344
Short name T53
Test name
Test status
Simulation time 118582447955 ps
CPU time 443.12 seconds
Started Aug 04 05:00:43 PM PDT 24
Finished Aug 04 05:08:07 PM PDT 24
Peak memory 201732 kb
Host smart-10d133c5-2a94-4fd0-9be7-e0854cc2cc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498705344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1498705344
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3622138349
Short name T457
Test name
Test status
Simulation time 33388435964 ps
CPU time 74.26 seconds
Started Aug 04 05:00:43 PM PDT 24
Finished Aug 04 05:01:58 PM PDT 24
Peak memory 201236 kb
Host smart-4b106916-c6f2-4be1-93df-1f4f3118f1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622138349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3622138349
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1216316926
Short name T486
Test name
Test status
Simulation time 3048069425 ps
CPU time 2.13 seconds
Started Aug 04 05:00:44 PM PDT 24
Finished Aug 04 05:00:46 PM PDT 24
Peak memory 201536 kb
Host smart-5888a1ba-9c2a-4424-bdbc-e6ccc6ea5c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216316926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1216316926
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1412881021
Short name T128
Test name
Test status
Simulation time 5934079437 ps
CPU time 7.63 seconds
Started Aug 04 05:00:39 PM PDT 24
Finished Aug 04 05:00:46 PM PDT 24
Peak memory 201212 kb
Host smart-c117ee7d-ab6a-48e8-b50f-a48d2b3bc8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412881021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1412881021
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1081030906
Short name T489
Test name
Test status
Simulation time 96398863119 ps
CPU time 290.98 seconds
Started Aug 04 05:00:48 PM PDT 24
Finished Aug 04 05:05:39 PM PDT 24
Peak memory 210060 kb
Host smart-cd107362-fe9b-4226-aeeb-b75e4c68a58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081030906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1081030906
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1601587953
Short name T450
Test name
Test status
Simulation time 481814769 ps
CPU time 0.88 seconds
Started Aug 04 05:00:56 PM PDT 24
Finished Aug 04 05:00:57 PM PDT 24
Peak memory 201164 kb
Host smart-11db428e-3459-49e5-bb54-858d64513de5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601587953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1601587953
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1096042215
Short name T322
Test name
Test status
Simulation time 513061712472 ps
CPU time 211.14 seconds
Started Aug 04 05:00:51 PM PDT 24
Finished Aug 04 05:04:23 PM PDT 24
Peak memory 201304 kb
Host smart-241d20a6-ab6b-4367-9392-afe94f0ecb8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096042215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1096042215
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.112369292
Short name T42
Test name
Test status
Simulation time 164336592600 ps
CPU time 51.35 seconds
Started Aug 04 05:00:52 PM PDT 24
Finished Aug 04 05:01:43 PM PDT 24
Peak memory 201292 kb
Host smart-b50985ab-6096-42ad-9db6-7003d3b97464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112369292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.112369292
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1761212468
Short name T429
Test name
Test status
Simulation time 492440630979 ps
CPU time 1160.64 seconds
Started Aug 04 05:00:47 PM PDT 24
Finished Aug 04 05:20:08 PM PDT 24
Peak memory 201388 kb
Host smart-2ddc398a-1b6a-4700-88aa-4a1d63fa6b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761212468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1761212468
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.592047059
Short name T381
Test name
Test status
Simulation time 322947696316 ps
CPU time 262.79 seconds
Started Aug 04 05:00:51 PM PDT 24
Finished Aug 04 05:05:14 PM PDT 24
Peak memory 201412 kb
Host smart-20b50803-eff8-438f-8f62-2048d98dce4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=592047059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.592047059
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.175286449
Short name T148
Test name
Test status
Simulation time 330905396335 ps
CPU time 179.17 seconds
Started Aug 04 05:00:52 PM PDT 24
Finished Aug 04 05:03:51 PM PDT 24
Peak memory 201400 kb
Host smart-329a6767-e0d9-462a-b0aa-c34e06e0b877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175286449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.175286449
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1874354627
Short name T787
Test name
Test status
Simulation time 484536009894 ps
CPU time 296.92 seconds
Started Aug 04 05:00:49 PM PDT 24
Finished Aug 04 05:05:47 PM PDT 24
Peak memory 201308 kb
Host smart-fb20d600-08aa-4565-b91f-a1ad4476f634
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874354627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1874354627
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.978010673
Short name T769
Test name
Test status
Simulation time 556090308654 ps
CPU time 1014.04 seconds
Started Aug 04 05:00:51 PM PDT 24
Finished Aug 04 05:17:46 PM PDT 24
Peak memory 201332 kb
Host smart-ae6169f5-e352-4b3b-b310-054f9379a747
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978010673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.978010673
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.329940358
Short name T5
Test name
Test status
Simulation time 192766042841 ps
CPU time 111.41 seconds
Started Aug 04 05:00:50 PM PDT 24
Finished Aug 04 05:02:42 PM PDT 24
Peak memory 201288 kb
Host smart-b6963e0c-4559-4257-912e-cf28c58140f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329940358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.329940358
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3873313063
Short name T51
Test name
Test status
Simulation time 87476439465 ps
CPU time 464.64 seconds
Started Aug 04 05:00:52 PM PDT 24
Finished Aug 04 05:08:37 PM PDT 24
Peak memory 201848 kb
Host smart-041f9513-39ab-488a-b962-bd97ec5c525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873313063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3873313063
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2238467794
Short name T517
Test name
Test status
Simulation time 41795813342 ps
CPU time 23.07 seconds
Started Aug 04 05:00:50 PM PDT 24
Finished Aug 04 05:01:14 PM PDT 24
Peak memory 201312 kb
Host smart-e453ff46-2462-4f46-8b23-1a2457760c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238467794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2238467794
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1733976927
Short name T579
Test name
Test status
Simulation time 2925331249 ps
CPU time 7.11 seconds
Started Aug 04 05:00:52 PM PDT 24
Finished Aug 04 05:00:59 PM PDT 24
Peak memory 201300 kb
Host smart-9d04cd4a-2aec-4408-ab2c-224e480ec29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733976927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1733976927
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1522237646
Short name T583
Test name
Test status
Simulation time 6057222262 ps
CPU time 16.48 seconds
Started Aug 04 05:00:49 PM PDT 24
Finished Aug 04 05:01:05 PM PDT 24
Peak memory 201300 kb
Host smart-0e3af23c-9a38-44d3-8ba9-fd3faeb1a226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522237646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1522237646
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2265625812
Short name T622
Test name
Test status
Simulation time 335106021879 ps
CPU time 1139.23 seconds
Started Aug 04 05:01:07 PM PDT 24
Finished Aug 04 05:20:06 PM PDT 24
Peak memory 209972 kb
Host smart-1ee69ded-b9bc-40ab-be6b-aa453e8faf8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265625812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2265625812
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1921302699
Short name T548
Test name
Test status
Simulation time 517092669 ps
CPU time 1.14 seconds
Started Aug 04 05:01:04 PM PDT 24
Finished Aug 04 05:01:05 PM PDT 24
Peak memory 201132 kb
Host smart-644ba5a4-ea53-479a-bd2f-a2a4312ad382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921302699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1921302699
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3706953294
Short name T760
Test name
Test status
Simulation time 198666763156 ps
CPU time 405.11 seconds
Started Aug 04 05:01:00 PM PDT 24
Finished Aug 04 05:07:45 PM PDT 24
Peak memory 201356 kb
Host smart-b52102fa-4614-4ec7-9d29-05d53acc22ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706953294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3706953294
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.4255735779
Short name T223
Test name
Test status
Simulation time 354866292522 ps
CPU time 794.37 seconds
Started Aug 04 05:01:00 PM PDT 24
Finished Aug 04 05:14:14 PM PDT 24
Peak memory 201308 kb
Host smart-78a0e415-0be8-4eb3-987a-f3f7629de7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255735779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.4255735779
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.154409143
Short name T551
Test name
Test status
Simulation time 164513348612 ps
CPU time 100.54 seconds
Started Aug 04 05:00:56 PM PDT 24
Finished Aug 04 05:02:37 PM PDT 24
Peak memory 201392 kb
Host smart-d0e6e905-e69b-4175-a253-6f30f83a6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154409143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.154409143
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.616323864
Short name T401
Test name
Test status
Simulation time 163352092930 ps
CPU time 184.92 seconds
Started Aug 04 05:01:01 PM PDT 24
Finished Aug 04 05:04:06 PM PDT 24
Peak memory 201380 kb
Host smart-0a91901e-f385-4b52-9144-8a089c17e606
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=616323864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.616323864
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2898858823
Short name T766
Test name
Test status
Simulation time 321595867458 ps
CPU time 385.02 seconds
Started Aug 04 05:01:04 PM PDT 24
Finished Aug 04 05:07:29 PM PDT 24
Peak memory 201384 kb
Host smart-2b7c74fc-3a59-427a-a502-83807db72983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898858823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2898858823
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3633757455
Short name T755
Test name
Test status
Simulation time 328506067035 ps
CPU time 182.24 seconds
Started Aug 04 05:00:57 PM PDT 24
Finished Aug 04 05:03:59 PM PDT 24
Peak memory 201392 kb
Host smart-c27f81d3-f764-412d-a6a2-881ee9ba61d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633757455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3633757455
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3407559823
Short name T751
Test name
Test status
Simulation time 531280098308 ps
CPU time 282.43 seconds
Started Aug 04 05:00:59 PM PDT 24
Finished Aug 04 05:05:41 PM PDT 24
Peak memory 201396 kb
Host smart-b1997031-e60c-4e54-8214-56d34a74453d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407559823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3407559823
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2636353482
Short name T408
Test name
Test status
Simulation time 400987342699 ps
CPU time 887.15 seconds
Started Aug 04 05:01:00 PM PDT 24
Finished Aug 04 05:15:47 PM PDT 24
Peak memory 201416 kb
Host smart-a49b0cce-4213-45ff-bd43-8999ca84075b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636353482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2636353482
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.382939005
Short name T179
Test name
Test status
Simulation time 105981109728 ps
CPU time 550.8 seconds
Started Aug 04 05:01:03 PM PDT 24
Finished Aug 04 05:10:14 PM PDT 24
Peak memory 201764 kb
Host smart-b6ccf08a-e79e-4532-b6ec-71f98f1ae359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382939005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.382939005
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1692128041
Short name T393
Test name
Test status
Simulation time 45006619756 ps
CPU time 53.5 seconds
Started Aug 04 05:01:03 PM PDT 24
Finished Aug 04 05:01:56 PM PDT 24
Peak memory 201336 kb
Host smart-19ce0f2c-f5ba-4a7f-a946-287cdc4876e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692128041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1692128041
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2962890960
Short name T385
Test name
Test status
Simulation time 5362163501 ps
CPU time 2.23 seconds
Started Aug 04 05:00:59 PM PDT 24
Finished Aug 04 05:01:02 PM PDT 24
Peak memory 201284 kb
Host smart-c152b46d-11a0-4b38-9a65-84db045c986c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962890960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2962890960
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2221579111
Short name T666
Test name
Test status
Simulation time 5544545168 ps
CPU time 3.79 seconds
Started Aug 04 05:00:55 PM PDT 24
Finished Aug 04 05:00:59 PM PDT 24
Peak memory 201288 kb
Host smart-2b08042a-8df5-4eca-b609-afc42d3d4bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221579111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2221579111
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2709430663
Short name T721
Test name
Test status
Simulation time 297429081 ps
CPU time 1.28 seconds
Started Aug 04 05:01:20 PM PDT 24
Finished Aug 04 05:01:21 PM PDT 24
Peak memory 201120 kb
Host smart-6ade11f8-6ba6-45f1-9789-d5095f3f32be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709430663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2709430663
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.4067901890
Short name T230
Test name
Test status
Simulation time 330911356492 ps
CPU time 783.61 seconds
Started Aug 04 05:01:22 PM PDT 24
Finished Aug 04 05:14:26 PM PDT 24
Peak memory 201360 kb
Host smart-de8c8e88-9b40-4554-84bc-bfd89e23027a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067901890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.4067901890
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1840350080
Short name T553
Test name
Test status
Simulation time 490483498873 ps
CPU time 1095.45 seconds
Started Aug 04 05:01:16 PM PDT 24
Finished Aug 04 05:19:32 PM PDT 24
Peak memory 201312 kb
Host smart-6ac25213-5ea5-4cf2-a3e0-ce9e5bd18479
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840350080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1840350080
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2636471600
Short name T154
Test name
Test status
Simulation time 321433164173 ps
CPU time 204.14 seconds
Started Aug 04 05:01:07 PM PDT 24
Finished Aug 04 05:04:32 PM PDT 24
Peak memory 201324 kb
Host smart-5302b474-4745-4d4a-bec5-1f82efe90005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636471600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2636471600
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3078208564
Short name T786
Test name
Test status
Simulation time 329409338676 ps
CPU time 152.06 seconds
Started Aug 04 05:01:10 PM PDT 24
Finished Aug 04 05:03:43 PM PDT 24
Peak memory 201508 kb
Host smart-a24adb81-9723-4b3e-9238-6973e0817f94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078208564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3078208564
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.4001555284
Short name T739
Test name
Test status
Simulation time 378218235680 ps
CPU time 267.74 seconds
Started Aug 04 05:01:17 PM PDT 24
Finished Aug 04 05:05:44 PM PDT 24
Peak memory 201272 kb
Host smart-65934002-f6f1-4aa5-8eeb-fa887f282864
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001555284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.4001555284
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.86292280
Short name T239
Test name
Test status
Simulation time 406918116752 ps
CPU time 862.12 seconds
Started Aug 04 05:01:16 PM PDT 24
Finished Aug 04 05:15:38 PM PDT 24
Peak memory 201292 kb
Host smart-fe3be763-f9a3-4e7e-a8ea-f4ae5efff60a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86292280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
dc_ctrl_filters_wakeup_fixed.86292280
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2142038653
Short name T186
Test name
Test status
Simulation time 96915339350 ps
CPU time 315.94 seconds
Started Aug 04 05:01:20 PM PDT 24
Finished Aug 04 05:06:37 PM PDT 24
Peak memory 201784 kb
Host smart-9362dff6-7a6b-44b4-9bd9-bf12ac9ed3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142038653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2142038653
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3571049846
Short name T338
Test name
Test status
Simulation time 22947702743 ps
CPU time 14.42 seconds
Started Aug 04 05:01:15 PM PDT 24
Finished Aug 04 05:01:29 PM PDT 24
Peak memory 201256 kb
Host smart-2446949f-6881-49ca-96ba-963ab71b3f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571049846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3571049846
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2786842996
Short name T695
Test name
Test status
Simulation time 4853917075 ps
CPU time 12.52 seconds
Started Aug 04 05:01:15 PM PDT 24
Finished Aug 04 05:01:28 PM PDT 24
Peak memory 201280 kb
Host smart-3cab01cf-c6b0-4f19-84b1-f6fc8df224e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786842996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2786842996
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4088911798
Short name T662
Test name
Test status
Simulation time 5850213110 ps
CPU time 14.05 seconds
Started Aug 04 05:01:08 PM PDT 24
Finished Aug 04 05:01:22 PM PDT 24
Peak memory 201308 kb
Host smart-96de88ab-f0d9-4723-84a8-e85ff5b8d5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088911798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4088911798
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3452293618
Short name T712
Test name
Test status
Simulation time 168986266529 ps
CPU time 26.22 seconds
Started Aug 04 05:01:22 PM PDT 24
Finished Aug 04 05:01:48 PM PDT 24
Peak memory 201364 kb
Host smart-12db4692-06f6-4747-a333-1ec6bb79dc51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452293618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3452293618
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1183110643
Short name T733
Test name
Test status
Simulation time 34480546716 ps
CPU time 90.72 seconds
Started Aug 04 05:01:19 PM PDT 24
Finished Aug 04 05:02:50 PM PDT 24
Peak memory 210052 kb
Host smart-739fc39c-ee17-44fe-8661-1d31a120e3f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183110643 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1183110643
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2771685024
Short name T453
Test name
Test status
Simulation time 435191222 ps
CPU time 0.83 seconds
Started Aug 04 05:01:31 PM PDT 24
Finished Aug 04 05:01:32 PM PDT 24
Peak memory 201184 kb
Host smart-c2d42fa3-5b22-4fed-bc76-cb353ca32f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771685024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2771685024
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2401345788
Short name T710
Test name
Test status
Simulation time 512473322195 ps
CPU time 514.3 seconds
Started Aug 04 05:01:28 PM PDT 24
Finished Aug 04 05:10:03 PM PDT 24
Peak memory 201356 kb
Host smart-61ab8882-b15a-4986-827a-ae013ccf9c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401345788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2401345788
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3203349725
Short name T391
Test name
Test status
Simulation time 492247639381 ps
CPU time 272.53 seconds
Started Aug 04 05:01:25 PM PDT 24
Finished Aug 04 05:05:57 PM PDT 24
Peak memory 201356 kb
Host smart-478b27c8-ee9a-4ac2-8ca0-99a25fd21f3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203349725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3203349725
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2850090407
Short name T700
Test name
Test status
Simulation time 329421101350 ps
CPU time 649.78 seconds
Started Aug 04 05:01:21 PM PDT 24
Finished Aug 04 05:12:11 PM PDT 24
Peak memory 201412 kb
Host smart-144acff9-66c3-4bfd-80d2-009ec3b97d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850090407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2850090407
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.466098267
Short name T778
Test name
Test status
Simulation time 491378886492 ps
CPU time 251.31 seconds
Started Aug 04 05:01:21 PM PDT 24
Finished Aug 04 05:05:32 PM PDT 24
Peak memory 201416 kb
Host smart-904b613f-9b1c-43ef-bfc8-9e9464bc17bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=466098267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.466098267
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2935251912
Short name T293
Test name
Test status
Simulation time 543439072533 ps
CPU time 280.17 seconds
Started Aug 04 05:01:26 PM PDT 24
Finished Aug 04 05:06:06 PM PDT 24
Peak memory 201344 kb
Host smart-dc25a606-2994-48d6-a9a6-f54163daf208
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935251912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2935251912
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2989224846
Short name T369
Test name
Test status
Simulation time 203109561800 ps
CPU time 235.06 seconds
Started Aug 04 05:01:25 PM PDT 24
Finished Aug 04 05:05:20 PM PDT 24
Peak memory 201308 kb
Host smart-f188378c-0c10-46e0-a63d-878a38901fa3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989224846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2989224846
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2539938238
Short name T405
Test name
Test status
Simulation time 118804122014 ps
CPU time 390.19 seconds
Started Aug 04 05:01:29 PM PDT 24
Finished Aug 04 05:07:59 PM PDT 24
Peak memory 201764 kb
Host smart-6797f585-510a-4074-8922-4c0a27d33f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539938238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2539938238
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3797658114
Short name T412
Test name
Test status
Simulation time 46837381408 ps
CPU time 56.07 seconds
Started Aug 04 05:01:30 PM PDT 24
Finished Aug 04 05:02:26 PM PDT 24
Peak memory 201340 kb
Host smart-50dd2d47-b675-47b7-9a46-a6b2ca1f69cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797658114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3797658114
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.822873131
Short name T392
Test name
Test status
Simulation time 3889738535 ps
CPU time 4.97 seconds
Started Aug 04 05:01:28 PM PDT 24
Finished Aug 04 05:01:33 PM PDT 24
Peak memory 201532 kb
Host smart-56739967-8ba4-4676-8d6d-37d03d2363a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822873131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.822873131
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2058640377
Short name T377
Test name
Test status
Simulation time 5960969715 ps
CPU time 7.34 seconds
Started Aug 04 05:01:20 PM PDT 24
Finished Aug 04 05:01:28 PM PDT 24
Peak memory 201244 kb
Host smart-35799fbc-d0fb-41f8-9710-431a63de8b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058640377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2058640377
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2332550823
Short name T31
Test name
Test status
Simulation time 1805532789 ps
CPU time 4.64 seconds
Started Aug 04 05:01:32 PM PDT 24
Finished Aug 04 05:01:37 PM PDT 24
Peak memory 201440 kb
Host smart-ca3f6dd4-6273-4b56-964f-0419f18f7baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332550823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2332550823
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2016544729
Short name T21
Test name
Test status
Simulation time 973599828577 ps
CPU time 919.26 seconds
Started Aug 04 05:01:27 PM PDT 24
Finished Aug 04 05:16:47 PM PDT 24
Peak memory 210020 kb
Host smart-e50274da-64cd-4d65-bff1-85945eb5c49d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016544729 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2016544729
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1717112244
Short name T354
Test name
Test status
Simulation time 552154803 ps
CPU time 0.91 seconds
Started Aug 04 05:01:43 PM PDT 24
Finished Aug 04 05:01:44 PM PDT 24
Peak memory 201212 kb
Host smart-a5e67035-5e80-40a5-a3c9-f1a0cdd1e4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717112244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1717112244
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4200129432
Short name T280
Test name
Test status
Simulation time 163728535983 ps
CPU time 381 seconds
Started Aug 04 05:01:41 PM PDT 24
Finished Aug 04 05:08:02 PM PDT 24
Peak memory 201476 kb
Host smart-4ab0eb2c-74fe-4ba8-9209-0ced70339ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200129432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4200129432
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3375400690
Short name T535
Test name
Test status
Simulation time 164356929028 ps
CPU time 399.3 seconds
Started Aug 04 05:01:32 PM PDT 24
Finished Aug 04 05:08:11 PM PDT 24
Peak memory 201480 kb
Host smart-92249053-b8d3-457b-bd98-b7dac023fb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375400690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3375400690
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2827716563
Short name T610
Test name
Test status
Simulation time 325867735778 ps
CPU time 799.81 seconds
Started Aug 04 05:01:32 PM PDT 24
Finished Aug 04 05:14:51 PM PDT 24
Peak memory 201432 kb
Host smart-9639482f-53f2-449f-92c7-038683dccd21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827716563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2827716563
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2728395502
Short name T585
Test name
Test status
Simulation time 499293915684 ps
CPU time 303.68 seconds
Started Aug 04 05:01:33 PM PDT 24
Finished Aug 04 05:06:36 PM PDT 24
Peak memory 201644 kb
Host smart-6a6a7711-cd18-47e5-b7df-269d7df2c5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728395502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2728395502
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1175937541
Short name T340
Test name
Test status
Simulation time 170213931005 ps
CPU time 188.05 seconds
Started Aug 04 05:01:32 PM PDT 24
Finished Aug 04 05:04:40 PM PDT 24
Peak memory 201400 kb
Host smart-2099617b-1fe0-4079-a549-7b8380b87129
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175937541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1175937541
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4172633346
Short name T240
Test name
Test status
Simulation time 345079967704 ps
CPU time 723.01 seconds
Started Aug 04 05:01:36 PM PDT 24
Finished Aug 04 05:13:39 PM PDT 24
Peak memory 201320 kb
Host smart-87a355aa-ad63-46c9-9f89-b4f3a56ab111
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172633346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4172633346
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.586852242
Short name T696
Test name
Test status
Simulation time 414735014108 ps
CPU time 952.26 seconds
Started Aug 04 05:01:35 PM PDT 24
Finished Aug 04 05:17:28 PM PDT 24
Peak memory 201324 kb
Host smart-360a13ad-7bc9-414d-a146-9ebc01e5b0f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586852242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.586852242
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3223941715
Short name T518
Test name
Test status
Simulation time 95377796707 ps
CPU time 357.56 seconds
Started Aug 04 05:01:42 PM PDT 24
Finished Aug 04 05:07:40 PM PDT 24
Peak memory 201764 kb
Host smart-2a26eb64-abad-42bb-8a68-a1db358e0a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223941715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3223941715
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3017001609
Short name T578
Test name
Test status
Simulation time 21626334551 ps
CPU time 23.2 seconds
Started Aug 04 05:01:38 PM PDT 24
Finished Aug 04 05:02:02 PM PDT 24
Peak memory 201316 kb
Host smart-3ff462cf-2fd9-43a8-962d-d4fc8e3e8ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017001609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3017001609
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3747519736
Short name T771
Test name
Test status
Simulation time 3344371221 ps
CPU time 4.49 seconds
Started Aug 04 05:01:39 PM PDT 24
Finished Aug 04 05:01:44 PM PDT 24
Peak memory 201324 kb
Host smart-95827476-a5d5-4e58-9fe1-12121e208fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747519736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3747519736
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2458204293
Short name T355
Test name
Test status
Simulation time 6076144072 ps
CPU time 4.53 seconds
Started Aug 04 05:01:31 PM PDT 24
Finished Aug 04 05:01:36 PM PDT 24
Peak memory 201260 kb
Host smart-bf955157-b6b5-462d-a7b8-e3c4a6dbc4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458204293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2458204293
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1950017938
Short name T456
Test name
Test status
Simulation time 44730813261 ps
CPU time 14.12 seconds
Started Aug 04 05:01:44 PM PDT 24
Finished Aug 04 05:01:58 PM PDT 24
Peak memory 201388 kb
Host smart-2e90f2f3-8bfb-4d6c-956f-20be93ef0651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950017938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1950017938
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3667325318
Short name T757
Test name
Test status
Simulation time 123110872650 ps
CPU time 274.95 seconds
Started Aug 04 05:01:43 PM PDT 24
Finished Aug 04 05:06:18 PM PDT 24
Peak memory 211000 kb
Host smart-f20f5068-a055-4942-9eeb-63ce012e5063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667325318 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3667325318
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2790875417
Short name T363
Test name
Test status
Simulation time 348602846 ps
CPU time 1.37 seconds
Started Aug 04 04:57:59 PM PDT 24
Finished Aug 04 04:58:00 PM PDT 24
Peak memory 201212 kb
Host smart-789c8c02-51c1-47d1-9b7b-f7209514ff20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790875417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2790875417
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1657965174
Short name T209
Test name
Test status
Simulation time 333843243437 ps
CPU time 389.98 seconds
Started Aug 04 04:57:55 PM PDT 24
Finished Aug 04 05:04:25 PM PDT 24
Peak memory 201308 kb
Host smart-72e92d34-5935-411b-b964-66ca60118a89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657965174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1657965174
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.270541229
Short name T3
Test name
Test status
Simulation time 166703392428 ps
CPU time 365.87 seconds
Started Aug 04 04:57:57 PM PDT 24
Finished Aug 04 05:04:03 PM PDT 24
Peak memory 201448 kb
Host smart-db397855-4451-42ab-a07e-7d87cd7bee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270541229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.270541229
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.562293801
Short name T297
Test name
Test status
Simulation time 161895647144 ps
CPU time 148.89 seconds
Started Aug 04 04:57:54 PM PDT 24
Finished Aug 04 05:00:23 PM PDT 24
Peak memory 201428 kb
Host smart-80b1e822-93f2-4f28-a8b2-4111d8e26154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562293801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.562293801
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.92349246
Short name T452
Test name
Test status
Simulation time 498578251346 ps
CPU time 1090.73 seconds
Started Aug 04 04:57:55 PM PDT 24
Finished Aug 04 05:16:06 PM PDT 24
Peak memory 201312 kb
Host smart-cc270934-7767-4cf1-83ce-15c7e4f8d353
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=92349246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_
fixed.92349246
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2626807400
Short name T295
Test name
Test status
Simulation time 329976636462 ps
CPU time 560.17 seconds
Started Aug 04 04:57:54 PM PDT 24
Finished Aug 04 05:07:14 PM PDT 24
Peak memory 201380 kb
Host smart-1ef347e2-1401-4851-99fe-2e3e73e325b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626807400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2626807400
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3618710812
Short name T718
Test name
Test status
Simulation time 488462423300 ps
CPU time 297.66 seconds
Started Aug 04 04:57:53 PM PDT 24
Finished Aug 04 05:02:51 PM PDT 24
Peak memory 201288 kb
Host smart-24f74795-0ed8-437a-85a4-34fce9f519d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618710812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3618710812
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1166066986
Short name T419
Test name
Test status
Simulation time 596643975498 ps
CPU time 1211.95 seconds
Started Aug 04 04:57:55 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201624 kb
Host smart-d384c2ea-2e24-4618-b0a7-9b477d336833
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166066986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1166066986
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2290709557
Short name T510
Test name
Test status
Simulation time 86242440065 ps
CPU time 284.8 seconds
Started Aug 04 04:57:54 PM PDT 24
Finished Aug 04 05:02:39 PM PDT 24
Peak memory 201628 kb
Host smart-6f0b8f6e-c4bf-45bd-b78c-f869c0aab809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290709557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2290709557
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3277257710
Short name T798
Test name
Test status
Simulation time 33707690806 ps
CPU time 19.73 seconds
Started Aug 04 04:57:55 PM PDT 24
Finished Aug 04 04:58:15 PM PDT 24
Peak memory 201312 kb
Host smart-0dff6065-26a6-40f5-8666-efe6dfa09820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277257710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3277257710
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1383835200
Short name T422
Test name
Test status
Simulation time 5001178415 ps
CPU time 3.54 seconds
Started Aug 04 04:57:58 PM PDT 24
Finished Aug 04 04:58:01 PM PDT 24
Peak memory 201264 kb
Host smart-9147a162-e55c-46f3-8d32-0f34a4ebcf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383835200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1383835200
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3714518181
Short name T82
Test name
Test status
Simulation time 4094382550 ps
CPU time 3.33 seconds
Started Aug 04 04:57:58 PM PDT 24
Finished Aug 04 04:58:02 PM PDT 24
Peak memory 217076 kb
Host smart-ab1a4d76-0978-4a74-9e68-f28446134280
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714518181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3714518181
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.807378035
Short name T782
Test name
Test status
Simulation time 5652927176 ps
CPU time 3.83 seconds
Started Aug 04 04:57:54 PM PDT 24
Finished Aug 04 04:57:58 PM PDT 24
Peak memory 201256 kb
Host smart-4ac18aaa-ba03-48fc-8165-a39ba1373220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807378035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.807378035
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1188928016
Short name T260
Test name
Test status
Simulation time 361126976543 ps
CPU time 206.05 seconds
Started Aug 04 04:57:57 PM PDT 24
Finished Aug 04 05:01:24 PM PDT 24
Peak memory 201348 kb
Host smart-ae7ba4ff-02e7-4410-b80d-55906f9ae3fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188928016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1188928016
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1446904086
Short name T93
Test name
Test status
Simulation time 219488967174 ps
CPU time 250.23 seconds
Started Aug 04 04:57:54 PM PDT 24
Finished Aug 04 05:02:05 PM PDT 24
Peak memory 209992 kb
Host smart-f2e42867-bb35-4027-bb82-8db3add7f65b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446904086 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1446904086
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.656888742
Short name T792
Test name
Test status
Simulation time 347343780 ps
CPU time 1.31 seconds
Started Aug 04 05:01:55 PM PDT 24
Finished Aug 04 05:01:57 PM PDT 24
Peak memory 201176 kb
Host smart-494b696a-46a5-4ba5-9b59-04eca0d5fa81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656888742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.656888742
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3256555610
Short name T138
Test name
Test status
Simulation time 546225743016 ps
CPU time 282 seconds
Started Aug 04 05:01:51 PM PDT 24
Finished Aug 04 05:06:34 PM PDT 24
Peak memory 201296 kb
Host smart-5b2f7578-e24c-4ec5-8acc-334ac732be63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256555610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3256555610
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.77538309
Short name T308
Test name
Test status
Simulation time 337511320225 ps
CPU time 206.58 seconds
Started Aug 04 05:01:51 PM PDT 24
Finished Aug 04 05:05:18 PM PDT 24
Peak memory 201384 kb
Host smart-f7b1a7a9-6cfa-4811-a38c-d684e9294865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77538309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.77538309
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1489117018
Short name T767
Test name
Test status
Simulation time 162682431633 ps
CPU time 371.73 seconds
Started Aug 04 05:01:48 PM PDT 24
Finished Aug 04 05:08:00 PM PDT 24
Peak memory 201380 kb
Host smart-d2c8125d-a30e-4e97-b576-27d3047487b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489117018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1489117018
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1519397995
Short name T425
Test name
Test status
Simulation time 160725518015 ps
CPU time 97.35 seconds
Started Aug 04 05:01:47 PM PDT 24
Finished Aug 04 05:03:25 PM PDT 24
Peak memory 201356 kb
Host smart-852387cf-d7ad-4716-aa54-eb77de2f80ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519397995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1519397995
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2860302573
Short name T169
Test name
Test status
Simulation time 490541991592 ps
CPU time 307.71 seconds
Started Aug 04 05:01:47 PM PDT 24
Finished Aug 04 05:06:55 PM PDT 24
Peak memory 201340 kb
Host smart-ecbec577-9638-421a-bd49-091cab6979d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860302573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2860302573
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1289677696
Short name T378
Test name
Test status
Simulation time 484271899594 ps
CPU time 292.1 seconds
Started Aug 04 05:01:48 PM PDT 24
Finished Aug 04 05:06:40 PM PDT 24
Peak memory 201352 kb
Host smart-424ea8a8-87cf-4317-8415-0758e323989c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289677696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1289677696
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.107826132
Short name T221
Test name
Test status
Simulation time 361832855724 ps
CPU time 778.94 seconds
Started Aug 04 05:01:47 PM PDT 24
Finished Aug 04 05:14:46 PM PDT 24
Peak memory 201392 kb
Host smart-07a49eeb-2a8e-47e8-9322-a85d5db8091b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107826132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.107826132
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1775527257
Short name T725
Test name
Test status
Simulation time 201612413177 ps
CPU time 55.57 seconds
Started Aug 04 05:01:47 PM PDT 24
Finished Aug 04 05:02:43 PM PDT 24
Peak memory 201444 kb
Host smart-ccf92e4c-2e3a-4a07-b390-a2523eafceeb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775527257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1775527257
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2252368564
Short name T52
Test name
Test status
Simulation time 119225874779 ps
CPU time 449.48 seconds
Started Aug 04 05:01:57 PM PDT 24
Finished Aug 04 05:09:26 PM PDT 24
Peak memory 201716 kb
Host smart-c4a5d541-13b6-4364-8f2e-14299a27e28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252368564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2252368564
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2893435296
Short name T644
Test name
Test status
Simulation time 35039895674 ps
CPU time 75.19 seconds
Started Aug 04 05:01:51 PM PDT 24
Finished Aug 04 05:03:06 PM PDT 24
Peak memory 201268 kb
Host smart-26f9515b-bcdb-4a12-a086-1fd5dde6e10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893435296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2893435296
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.4128689520
Short name T481
Test name
Test status
Simulation time 3963167210 ps
CPU time 2.74 seconds
Started Aug 04 05:01:52 PM PDT 24
Finished Aug 04 05:01:55 PM PDT 24
Peak memory 201212 kb
Host smart-bae1aae2-5f18-4751-8083-cad88721204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128689520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.4128689520
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1882646203
Short name T521
Test name
Test status
Simulation time 5771922903 ps
CPU time 13.04 seconds
Started Aug 04 05:01:43 PM PDT 24
Finished Aug 04 05:01:56 PM PDT 24
Peak memory 201308 kb
Host smart-b719296d-b1a0-4942-9886-a50f29a1ccd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882646203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1882646203
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3456702699
Short name T247
Test name
Test status
Simulation time 189418249822 ps
CPU time 127.28 seconds
Started Aug 04 05:01:57 PM PDT 24
Finished Aug 04 05:04:04 PM PDT 24
Peak memory 201356 kb
Host smart-1696c8da-0601-46d8-bb58-30e7a89d8207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456702699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3456702699
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1504971423
Short name T478
Test name
Test status
Simulation time 120881667100 ps
CPU time 227.37 seconds
Started Aug 04 05:01:55 PM PDT 24
Finished Aug 04 05:05:42 PM PDT 24
Peak memory 210104 kb
Host smart-c4577340-00ed-4b37-bc87-32ba19d8999d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504971423 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1504971423
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.264846514
Short name T37
Test name
Test status
Simulation time 425833107 ps
CPU time 1.51 seconds
Started Aug 04 05:02:06 PM PDT 24
Finished Aug 04 05:02:08 PM PDT 24
Peak memory 201120 kb
Host smart-ea3b4ff5-2743-4c50-9e31-c40481c6eecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264846514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.264846514
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1297104073
Short name T237
Test name
Test status
Simulation time 182158804998 ps
CPU time 64.96 seconds
Started Aug 04 05:02:00 PM PDT 24
Finished Aug 04 05:03:05 PM PDT 24
Peak memory 201348 kb
Host smart-06900f31-be65-416b-bef8-b25f86783d21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297104073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1297104073
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3471885829
Short name T325
Test name
Test status
Simulation time 444465924717 ps
CPU time 764.07 seconds
Started Aug 04 05:02:06 PM PDT 24
Finished Aug 04 05:14:50 PM PDT 24
Peak memory 201392 kb
Host smart-04720ced-ac49-4049-9707-3d8df239e808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471885829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3471885829
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2784561950
Short name T650
Test name
Test status
Simulation time 326102946254 ps
CPU time 198.06 seconds
Started Aug 04 05:02:00 PM PDT 24
Finished Aug 04 05:05:18 PM PDT 24
Peak memory 201376 kb
Host smart-a4dc97ea-1dc9-4021-8ebe-6b16cabfc5c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784561950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2784561950
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3040260888
Short name T432
Test name
Test status
Simulation time 489773024240 ps
CPU time 319.26 seconds
Started Aug 04 05:01:59 PM PDT 24
Finished Aug 04 05:07:18 PM PDT 24
Peak memory 201384 kb
Host smart-51d39af6-cbfc-449a-8643-800526886fba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040260888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3040260888
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2672049183
Short name T286
Test name
Test status
Simulation time 366827759167 ps
CPU time 799.27 seconds
Started Aug 04 05:02:01 PM PDT 24
Finished Aug 04 05:15:20 PM PDT 24
Peak memory 201344 kb
Host smart-10ecca39-9cfa-423e-af70-6f458f0fd861
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672049183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2672049183
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3092751867
Short name T361
Test name
Test status
Simulation time 388034136826 ps
CPU time 784.67 seconds
Started Aug 04 05:02:01 PM PDT 24
Finished Aug 04 05:15:06 PM PDT 24
Peak memory 201404 kb
Host smart-353fbad6-bab6-4d3f-bc05-a320b29d369b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092751867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3092751867
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2217468283
Short name T624
Test name
Test status
Simulation time 74216197259 ps
CPU time 391.69 seconds
Started Aug 04 05:02:06 PM PDT 24
Finished Aug 04 05:08:38 PM PDT 24
Peak memory 201836 kb
Host smart-8401048d-8be9-453d-88af-847225542e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217468283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2217468283
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.287645276
Short name T594
Test name
Test status
Simulation time 24936160483 ps
CPU time 58.95 seconds
Started Aug 04 05:02:05 PM PDT 24
Finished Aug 04 05:03:04 PM PDT 24
Peak memory 201284 kb
Host smart-92f31fed-4b40-4d30-966d-f4876ac6d823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287645276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.287645276
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.4055516723
Short name T470
Test name
Test status
Simulation time 3842310710 ps
CPU time 4.87 seconds
Started Aug 04 05:02:05 PM PDT 24
Finished Aug 04 05:02:10 PM PDT 24
Peak memory 201220 kb
Host smart-44bc49cb-ca67-424f-a176-af9bbccebbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055516723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.4055516723
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.4160627340
Short name T527
Test name
Test status
Simulation time 5571492440 ps
CPU time 11.14 seconds
Started Aug 04 05:01:57 PM PDT 24
Finished Aug 04 05:02:08 PM PDT 24
Peak memory 201288 kb
Host smart-fb788061-2699-4bc5-b2d2-c1d2db6f32f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160627340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.4160627340
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.933042091
Short name T164
Test name
Test status
Simulation time 174646064911 ps
CPU time 30.37 seconds
Started Aug 04 05:02:07 PM PDT 24
Finished Aug 04 05:02:38 PM PDT 24
Peak memory 201416 kb
Host smart-a9f57be4-8988-4b44-b587-ffd80a6f77f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933042091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
933042091
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3688085725
Short name T17
Test name
Test status
Simulation time 113300761305 ps
CPU time 72.95 seconds
Started Aug 04 05:02:07 PM PDT 24
Finished Aug 04 05:03:20 PM PDT 24
Peak memory 218248 kb
Host smart-1af1988f-1870-4be5-a8c5-1ab2ba4164dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688085725 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3688085725
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3656608854
Short name T104
Test name
Test status
Simulation time 397959798 ps
CPU time 0.79 seconds
Started Aug 04 05:02:19 PM PDT 24
Finished Aug 04 05:02:20 PM PDT 24
Peak memory 201092 kb
Host smart-181bf9c0-3219-4bc1-9652-da4b3e08115c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656608854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3656608854
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4187984556
Short name T266
Test name
Test status
Simulation time 350587254240 ps
CPU time 463.86 seconds
Started Aug 04 05:02:15 PM PDT 24
Finished Aug 04 05:09:59 PM PDT 24
Peak memory 201624 kb
Host smart-e03ef84e-0111-46b8-90ad-d29c35f783b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187984556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4187984556
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3203890694
Short name T216
Test name
Test status
Simulation time 331068110921 ps
CPU time 412.97 seconds
Started Aug 04 05:02:10 PM PDT 24
Finished Aug 04 05:09:03 PM PDT 24
Peak memory 201360 kb
Host smart-ba27c9cf-06c0-4ad1-87e6-5bcd9c3a0f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203890694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3203890694
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3622445372
Short name T785
Test name
Test status
Simulation time 326164866517 ps
CPU time 655.86 seconds
Started Aug 04 05:02:09 PM PDT 24
Finished Aug 04 05:13:05 PM PDT 24
Peak memory 201380 kb
Host smart-af74ab40-20cb-4d63-b44f-2c3171168929
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622445372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3622445372
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2373741778
Short name T226
Test name
Test status
Simulation time 494991475327 ps
CPU time 1235.06 seconds
Started Aug 04 05:02:10 PM PDT 24
Finished Aug 04 05:22:45 PM PDT 24
Peak memory 201348 kb
Host smart-a4dfb26c-e198-466c-8bef-c8cafdc008ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373741778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2373741778
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.470205791
Short name T441
Test name
Test status
Simulation time 492088929916 ps
CPU time 268.37 seconds
Started Aug 04 05:02:10 PM PDT 24
Finished Aug 04 05:06:39 PM PDT 24
Peak memory 201392 kb
Host smart-930113a5-2e4f-4a40-a571-137f15760ead
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=470205791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.470205791
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.4206735828
Short name T319
Test name
Test status
Simulation time 346271947258 ps
CPU time 195.87 seconds
Started Aug 04 05:02:10 PM PDT 24
Finished Aug 04 05:05:26 PM PDT 24
Peak memory 201300 kb
Host smart-31efa630-9c60-4b8a-a2fa-a19e90c94651
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206735828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.4206735828
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2924824029
Short name T433
Test name
Test status
Simulation time 603775606167 ps
CPU time 1367.06 seconds
Started Aug 04 05:02:15 PM PDT 24
Finished Aug 04 05:25:02 PM PDT 24
Peak memory 201408 kb
Host smart-e72973b2-c0d3-42fa-a3db-051925f7551f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924824029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2924824029
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.702869077
Short name T555
Test name
Test status
Simulation time 44265528477 ps
CPU time 102.21 seconds
Started Aug 04 05:02:22 PM PDT 24
Finished Aug 04 05:04:05 PM PDT 24
Peak memory 201316 kb
Host smart-0923cd52-dfb0-4167-8b74-915961477386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702869077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.702869077
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4147175255
Short name T403
Test name
Test status
Simulation time 3944660527 ps
CPU time 9.42 seconds
Started Aug 04 05:02:15 PM PDT 24
Finished Aug 04 05:02:25 PM PDT 24
Peak memory 201252 kb
Host smart-86829956-03eb-4187-90a6-194a1785bb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147175255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4147175255
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.605349157
Short name T646
Test name
Test status
Simulation time 5566240703 ps
CPU time 12.65 seconds
Started Aug 04 05:02:06 PM PDT 24
Finished Aug 04 05:02:19 PM PDT 24
Peak memory 201316 kb
Host smart-92314cea-b648-4409-8f95-c3055951488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605349157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.605349157
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3706873277
Short name T520
Test name
Test status
Simulation time 115779821935 ps
CPU time 151.7 seconds
Started Aug 04 05:02:20 PM PDT 24
Finished Aug 04 05:04:52 PM PDT 24
Peak memory 218320 kb
Host smart-50cfd60a-55b4-409c-924b-08291d564af3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706873277 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3706873277
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3206741791
Short name T744
Test name
Test status
Simulation time 459121130 ps
CPU time 1.65 seconds
Started Aug 04 05:02:35 PM PDT 24
Finished Aug 04 05:02:37 PM PDT 24
Peak memory 201120 kb
Host smart-fd5c290a-f1bc-4c09-a966-2d71e3457355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206741791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3206741791
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1096706694
Short name T503
Test name
Test status
Simulation time 323573322765 ps
CPU time 130.58 seconds
Started Aug 04 05:02:31 PM PDT 24
Finished Aug 04 05:04:41 PM PDT 24
Peak memory 201320 kb
Host smart-50536cdd-cfdd-4951-b2e1-1b83e97bc7af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096706694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1096706694
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1980650475
Short name T248
Test name
Test status
Simulation time 321145944562 ps
CPU time 189.84 seconds
Started Aug 04 05:02:33 PM PDT 24
Finished Aug 04 05:05:43 PM PDT 24
Peak memory 201416 kb
Host smart-80ab9351-ea5c-43ef-9baa-aff9c8d066af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980650475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1980650475
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4145045449
Short name T426
Test name
Test status
Simulation time 329678785408 ps
CPU time 723 seconds
Started Aug 04 05:02:31 PM PDT 24
Finished Aug 04 05:14:34 PM PDT 24
Peak memory 200800 kb
Host smart-f4ce3f2e-627d-4fbf-8aca-d6b403a10f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145045449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4145045449
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2341142229
Short name T599
Test name
Test status
Simulation time 490872618176 ps
CPU time 89.09 seconds
Started Aug 04 05:02:33 PM PDT 24
Finished Aug 04 05:04:02 PM PDT 24
Peak memory 201400 kb
Host smart-3ea0a83f-90d0-4f91-b1a2-48b5f31ae3af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341142229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2341142229
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1026546124
Short name T764
Test name
Test status
Simulation time 330435625940 ps
CPU time 798.56 seconds
Started Aug 04 05:02:24 PM PDT 24
Finished Aug 04 05:15:43 PM PDT 24
Peak memory 201364 kb
Host smart-7caee2be-16d6-4670-abb1-aac9af1aa5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026546124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1026546124
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3011568900
Short name T157
Test name
Test status
Simulation time 494411769057 ps
CPU time 317.84 seconds
Started Aug 04 05:02:26 PM PDT 24
Finished Aug 04 05:07:44 PM PDT 24
Peak memory 201340 kb
Host smart-1a06d6ec-85be-4c17-a09c-8be70d9b44a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011568900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3011568900
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3689571124
Short name T141
Test name
Test status
Simulation time 177955142780 ps
CPU time 61.06 seconds
Started Aug 04 05:02:32 PM PDT 24
Finished Aug 04 05:03:33 PM PDT 24
Peak memory 201404 kb
Host smart-9843cd34-0e39-4800-9113-3f90b290682f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689571124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3689571124
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3356687712
Short name T572
Test name
Test status
Simulation time 616214973563 ps
CPU time 178.09 seconds
Started Aug 04 05:02:30 PM PDT 24
Finished Aug 04 05:05:28 PM PDT 24
Peak memory 201376 kb
Host smart-06d17f95-8433-489e-8abb-9e623518c4e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356687712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3356687712
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.4269177292
Short name T617
Test name
Test status
Simulation time 79981661964 ps
CPU time 255.91 seconds
Started Aug 04 05:02:30 PM PDT 24
Finished Aug 04 05:06:46 PM PDT 24
Peak memory 201108 kb
Host smart-7b075587-c454-419f-9f60-13573915866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269177292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.4269177292
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4042905607
Short name T466
Test name
Test status
Simulation time 25636605994 ps
CPU time 31.12 seconds
Started Aug 04 05:02:30 PM PDT 24
Finished Aug 04 05:03:02 PM PDT 24
Peak memory 201268 kb
Host smart-a01c965d-b884-4e39-936d-bf5e7721a049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042905607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4042905607
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.939203122
Short name T714
Test name
Test status
Simulation time 5182520151 ps
CPU time 6.78 seconds
Started Aug 04 05:02:29 PM PDT 24
Finished Aug 04 05:02:36 PM PDT 24
Peak memory 201304 kb
Host smart-2f352f33-9afc-4ec4-8807-29335eb4a7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939203122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.939203122
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3013773544
Short name T657
Test name
Test status
Simulation time 6110610373 ps
CPU time 3.15 seconds
Started Aug 04 05:02:25 PM PDT 24
Finished Aug 04 05:02:29 PM PDT 24
Peak memory 201312 kb
Host smart-88f4b8aa-8063-441d-8aac-3c3ebc1b0335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013773544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3013773544
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2015935238
Short name T421
Test name
Test status
Simulation time 484060158 ps
CPU time 0.82 seconds
Started Aug 04 05:02:43 PM PDT 24
Finished Aug 04 05:02:44 PM PDT 24
Peak memory 201192 kb
Host smart-17a9e41d-9e71-4c9f-83ef-13aa229e8958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015935238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2015935238
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1310627687
Short name T533
Test name
Test status
Simulation time 335798035103 ps
CPU time 123.24 seconds
Started Aug 04 05:02:41 PM PDT 24
Finished Aug 04 05:04:44 PM PDT 24
Peak memory 201308 kb
Host smart-3bec429e-ef6e-44db-8668-d25d622908b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310627687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1310627687
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1917184437
Short name T262
Test name
Test status
Simulation time 560596258105 ps
CPU time 655.55 seconds
Started Aug 04 05:02:41 PM PDT 24
Finished Aug 04 05:13:37 PM PDT 24
Peak memory 201372 kb
Host smart-8779225f-4bf2-41f4-94e2-88ae8bb703a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917184437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1917184437
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1986979205
Short name T134
Test name
Test status
Simulation time 161446860595 ps
CPU time 90.42 seconds
Started Aug 04 05:02:34 PM PDT 24
Finished Aug 04 05:04:05 PM PDT 24
Peak memory 201476 kb
Host smart-4d0d3e63-8a02-42fb-84fa-125173c6883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986979205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1986979205
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2437700949
Short name T544
Test name
Test status
Simulation time 316758939855 ps
CPU time 181.3 seconds
Started Aug 04 05:02:35 PM PDT 24
Finished Aug 04 05:05:36 PM PDT 24
Peak memory 201372 kb
Host smart-3133e577-cb25-49b9-a81a-7ee23c910407
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437700949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2437700949
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3907734195
Short name T603
Test name
Test status
Simulation time 325183361020 ps
CPU time 708.94 seconds
Started Aug 04 05:02:36 PM PDT 24
Finished Aug 04 05:14:25 PM PDT 24
Peak memory 201416 kb
Host smart-410f928d-71b7-46e6-9f32-4b04a3cad8fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907734195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3907734195
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2486542122
Short name T654
Test name
Test status
Simulation time 366232654123 ps
CPU time 838.23 seconds
Started Aug 04 05:02:39 PM PDT 24
Finished Aug 04 05:16:38 PM PDT 24
Peak memory 201396 kb
Host smart-534ce58d-7634-485b-bc06-2daabccceb0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486542122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2486542122
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1318914924
Short name T458
Test name
Test status
Simulation time 415068971505 ps
CPU time 297.53 seconds
Started Aug 04 05:02:40 PM PDT 24
Finished Aug 04 05:07:38 PM PDT 24
Peak memory 201316 kb
Host smart-38407cac-b632-46fb-8b79-58572d460745
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318914924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1318914924
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4280966554
Short name T745
Test name
Test status
Simulation time 98250449832 ps
CPU time 337.71 seconds
Started Aug 04 05:02:49 PM PDT 24
Finished Aug 04 05:08:27 PM PDT 24
Peak memory 201736 kb
Host smart-06cd81ea-35ac-4a06-b3bd-d61c47aa2c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280966554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4280966554
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2524716794
Short name T537
Test name
Test status
Simulation time 32231702070 ps
CPU time 37.21 seconds
Started Aug 04 05:02:49 PM PDT 24
Finished Aug 04 05:03:27 PM PDT 24
Peak memory 201204 kb
Host smart-d703e9b9-e2f9-4bb8-9e21-2875d0b333e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524716794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2524716794
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2372878686
Short name T468
Test name
Test status
Simulation time 4358626130 ps
CPU time 6.18 seconds
Started Aug 04 05:02:39 PM PDT 24
Finished Aug 04 05:02:46 PM PDT 24
Peak memory 201196 kb
Host smart-6bfa0e64-5e76-4d16-b8b4-4739430112a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372878686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2372878686
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1716729152
Short name T614
Test name
Test status
Simulation time 6009801284 ps
CPU time 7.71 seconds
Started Aug 04 05:02:33 PM PDT 24
Finished Aug 04 05:02:41 PM PDT 24
Peak memory 201284 kb
Host smart-2ec2b1cf-af83-41cf-a805-db62258d3dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716729152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1716729152
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1530721823
Short name T236
Test name
Test status
Simulation time 331388752255 ps
CPU time 267.37 seconds
Started Aug 04 05:02:52 PM PDT 24
Finished Aug 04 05:07:19 PM PDT 24
Peak memory 201288 kb
Host smart-ea16c712-bbd6-4f17-bfcb-ccfe83f58815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530721823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1530721823
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.44913171
Short name T12
Test name
Test status
Simulation time 80242163352 ps
CPU time 146.42 seconds
Started Aug 04 05:02:49 PM PDT 24
Finished Aug 04 05:05:16 PM PDT 24
Peak memory 210132 kb
Host smart-409cad50-4d62-46e7-8405-9ae8fa134959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44913171 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.44913171
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1933781435
Short name T674
Test name
Test status
Simulation time 504020157 ps
CPU time 1.68 seconds
Started Aug 04 05:03:03 PM PDT 24
Finished Aug 04 05:03:04 PM PDT 24
Peak memory 201144 kb
Host smart-37c76f74-efff-4d0a-9eba-8dba3af9e1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933781435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1933781435
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.234270407
Short name T300
Test name
Test status
Simulation time 348663906496 ps
CPU time 800.72 seconds
Started Aug 04 05:02:54 PM PDT 24
Finished Aug 04 05:16:15 PM PDT 24
Peak memory 201292 kb
Host smart-15fa9d72-0efd-4824-9522-562976aa40b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234270407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.234270407
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.4167464602
Short name T288
Test name
Test status
Simulation time 491767859175 ps
CPU time 304.84 seconds
Started Aug 04 05:02:49 PM PDT 24
Finished Aug 04 05:07:54 PM PDT 24
Peak memory 201344 kb
Host smart-7c4f4e62-cec7-4eef-93ad-873a44324ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167464602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.4167464602
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.303298305
Short name T451
Test name
Test status
Simulation time 161528880143 ps
CPU time 192.72 seconds
Started Aug 04 05:02:49 PM PDT 24
Finished Aug 04 05:06:01 PM PDT 24
Peak memory 201328 kb
Host smart-c7bfb577-40f0-450f-8019-b7f4490a554e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=303298305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.303298305
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3495242376
Short name T283
Test name
Test status
Simulation time 495620050575 ps
CPU time 486.86 seconds
Started Aug 04 05:02:49 PM PDT 24
Finished Aug 04 05:10:56 PM PDT 24
Peak memory 201328 kb
Host smart-2f475b26-0052-4d7c-a00b-30ce7eb1d120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495242376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3495242376
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.887958466
Short name T568
Test name
Test status
Simulation time 164422680456 ps
CPU time 192.74 seconds
Started Aug 04 05:02:49 PM PDT 24
Finished Aug 04 05:06:01 PM PDT 24
Peak memory 201348 kb
Host smart-50913915-15a1-4fb4-8782-656a2a2bcd85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=887958466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.887958466
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.4219937445
Short name T238
Test name
Test status
Simulation time 211663046817 ps
CPU time 119.69 seconds
Started Aug 04 05:02:53 PM PDT 24
Finished Aug 04 05:04:53 PM PDT 24
Peak memory 201368 kb
Host smart-d8600892-bfba-420f-bea2-4f6acf8e200f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219937445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.4219937445
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1411365856
Short name T509
Test name
Test status
Simulation time 635893920293 ps
CPU time 744.77 seconds
Started Aug 04 05:02:55 PM PDT 24
Finished Aug 04 05:15:20 PM PDT 24
Peak memory 201344 kb
Host smart-46577ab5-f72e-4a0b-87e4-6dad808b1779
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411365856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1411365856
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1534320650
Short name T45
Test name
Test status
Simulation time 68957904498 ps
CPU time 393.07 seconds
Started Aug 04 05:02:54 PM PDT 24
Finished Aug 04 05:09:27 PM PDT 24
Peak memory 201784 kb
Host smart-22b1df15-d42b-44d7-923b-38ec9381ef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534320650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1534320650
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2551844685
Short name T472
Test name
Test status
Simulation time 30995936662 ps
CPU time 72.16 seconds
Started Aug 04 05:02:54 PM PDT 24
Finished Aug 04 05:04:07 PM PDT 24
Peak memory 201300 kb
Host smart-d3aebc07-81c0-4f9e-96a1-f829e82dc26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551844685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2551844685
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3243757354
Short name T672
Test name
Test status
Simulation time 2872297418 ps
CPU time 7.23 seconds
Started Aug 04 05:02:54 PM PDT 24
Finished Aug 04 05:03:02 PM PDT 24
Peak memory 201304 kb
Host smart-cbc82c35-9c95-4f6d-9504-ad3ada0e5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243757354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3243757354
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.292311611
Short name T492
Test name
Test status
Simulation time 5920325567 ps
CPU time 12.8 seconds
Started Aug 04 05:02:52 PM PDT 24
Finished Aug 04 05:03:05 PM PDT 24
Peak memory 201208 kb
Host smart-7d71f396-6547-40bf-beba-98ab9ac985b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292311611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.292311611
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2331731603
Short name T765
Test name
Test status
Simulation time 164317577884 ps
CPU time 347.03 seconds
Started Aug 04 05:02:53 PM PDT 24
Finished Aug 04 05:08:40 PM PDT 24
Peak memory 201480 kb
Host smart-6679d162-7151-476c-a702-0280a9253929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331731603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2331731603
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.4209142835
Short name T276
Test name
Test status
Simulation time 266073027725 ps
CPU time 228.65 seconds
Started Aug 04 05:02:56 PM PDT 24
Finished Aug 04 05:06:45 PM PDT 24
Peak memory 217444 kb
Host smart-3d50d0f4-46ca-4d50-b1f5-c195da72bc03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209142835 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.4209142835
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.844629100
Short name T471
Test name
Test status
Simulation time 464289744 ps
CPU time 1.16 seconds
Started Aug 04 05:03:08 PM PDT 24
Finished Aug 04 05:03:10 PM PDT 24
Peak memory 201072 kb
Host smart-cca9d1d1-8446-4988-92c0-dc819c2b60bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844629100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.844629100
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1288402378
Short name T305
Test name
Test status
Simulation time 593770721046 ps
CPU time 269.75 seconds
Started Aug 04 05:03:03 PM PDT 24
Finished Aug 04 05:07:33 PM PDT 24
Peak memory 201376 kb
Host smart-0725d6b6-8a65-43f5-8cce-8c41a2075778
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288402378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1288402378
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1119588381
Short name T101
Test name
Test status
Simulation time 500781362711 ps
CPU time 242.8 seconds
Started Aug 04 05:03:03 PM PDT 24
Finished Aug 04 05:07:06 PM PDT 24
Peak memory 201472 kb
Host smart-0f18a3d5-0bd5-4a1a-8af6-56eff003ad3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119588381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1119588381
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1101080129
Short name T626
Test name
Test status
Simulation time 163355301325 ps
CPU time 122.94 seconds
Started Aug 04 05:02:58 PM PDT 24
Finished Aug 04 05:05:01 PM PDT 24
Peak memory 201324 kb
Host smart-03b6188e-ed21-4cc8-bb23-38c144913294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101080129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1101080129
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4123829439
Short name T87
Test name
Test status
Simulation time 330724147790 ps
CPU time 147.96 seconds
Started Aug 04 05:02:57 PM PDT 24
Finished Aug 04 05:05:25 PM PDT 24
Peak memory 201384 kb
Host smart-42c5eaa8-6256-4935-86da-02108b3fa74e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123829439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4123829439
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1563414133
Short name T434
Test name
Test status
Simulation time 325760597195 ps
CPU time 157.94 seconds
Started Aug 04 05:02:58 PM PDT 24
Finished Aug 04 05:05:36 PM PDT 24
Peak memory 201396 kb
Host smart-f1225a9a-845b-4b18-8983-511c69a23a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563414133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1563414133
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1747119480
Short name T590
Test name
Test status
Simulation time 484863988813 ps
CPU time 558.74 seconds
Started Aug 04 05:02:57 PM PDT 24
Finished Aug 04 05:12:16 PM PDT 24
Peak memory 201396 kb
Host smart-be57c7c2-eeef-40ab-a12f-7ed816195693
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747119480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1747119480
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1214149596
Short name T699
Test name
Test status
Simulation time 592422082032 ps
CPU time 82.97 seconds
Started Aug 04 05:03:02 PM PDT 24
Finished Aug 04 05:04:25 PM PDT 24
Peak memory 201384 kb
Host smart-2f530c5a-31d3-4586-82b3-353598ece98c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214149596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1214149596
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3885352007
Short name T447
Test name
Test status
Simulation time 122915295823 ps
CPU time 660.1 seconds
Started Aug 04 05:03:01 PM PDT 24
Finished Aug 04 05:14:01 PM PDT 24
Peak memory 201840 kb
Host smart-08e43241-6246-4bbb-9e41-dd1247ad1197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885352007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3885352007
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3686332149
Short name T592
Test name
Test status
Simulation time 37870497306 ps
CPU time 41.74 seconds
Started Aug 04 05:03:03 PM PDT 24
Finished Aug 04 05:03:45 PM PDT 24
Peak memory 201204 kb
Host smart-2f220924-1a5b-447c-a00f-c9e4f8826aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686332149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3686332149
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.4060703697
Short name T685
Test name
Test status
Simulation time 4434157420 ps
CPU time 2.01 seconds
Started Aug 04 05:03:03 PM PDT 24
Finished Aug 04 05:03:05 PM PDT 24
Peak memory 201304 kb
Host smart-cf23fdcc-5a1f-42a6-93b2-f6b76344d03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060703697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.4060703697
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.861597237
Short name T383
Test name
Test status
Simulation time 5725825586 ps
CPU time 3.16 seconds
Started Aug 04 05:02:57 PM PDT 24
Finished Aug 04 05:03:01 PM PDT 24
Peak memory 201212 kb
Host smart-a072439f-f35e-4cca-a2aa-1ac02a3de808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861597237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.861597237
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.850901496
Short name T615
Test name
Test status
Simulation time 458926240 ps
CPU time 0.83 seconds
Started Aug 04 05:03:14 PM PDT 24
Finished Aug 04 05:03:15 PM PDT 24
Peak memory 201108 kb
Host smart-362ef2b8-444e-491d-845a-a96307d8ab91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850901496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.850901496
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2393550017
Short name T636
Test name
Test status
Simulation time 530690820053 ps
CPU time 113.66 seconds
Started Aug 04 05:03:10 PM PDT 24
Finished Aug 04 05:05:04 PM PDT 24
Peak memory 201332 kb
Host smart-d3611414-ccb8-4d0e-826d-6d46363c82a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393550017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2393550017
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.4274891957
Short name T215
Test name
Test status
Simulation time 493409990748 ps
CPU time 929.11 seconds
Started Aug 04 05:03:10 PM PDT 24
Finished Aug 04 05:18:39 PM PDT 24
Peak memory 201360 kb
Host smart-6759832b-9e96-4b18-b139-0fe0ac75f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274891957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.4274891957
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3860331975
Short name T604
Test name
Test status
Simulation time 328060363355 ps
CPU time 180.34 seconds
Started Aug 04 05:03:11 PM PDT 24
Finished Aug 04 05:06:11 PM PDT 24
Peak memory 201376 kb
Host smart-96a2e16a-4b58-401b-97b7-f32af76b9015
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860331975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3860331975
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2391428572
Short name T565
Test name
Test status
Simulation time 165984817375 ps
CPU time 102.49 seconds
Started Aug 04 05:03:10 PM PDT 24
Finished Aug 04 05:04:52 PM PDT 24
Peak memory 201388 kb
Host smart-f5272eef-3483-4aa0-9910-597c9956d6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391428572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2391428572
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3595339460
Short name T384
Test name
Test status
Simulation time 325279872238 ps
CPU time 205.58 seconds
Started Aug 04 05:03:10 PM PDT 24
Finished Aug 04 05:06:36 PM PDT 24
Peak memory 201340 kb
Host smart-665277e2-bf62-4e68-a21d-8046cb610491
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595339460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3595339460
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2478599268
Short name T328
Test name
Test status
Simulation time 191372606405 ps
CPU time 455.9 seconds
Started Aug 04 05:03:11 PM PDT 24
Finished Aug 04 05:10:47 PM PDT 24
Peak memory 201376 kb
Host smart-320a7488-3dda-4d39-9e79-b4742ea560a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478599268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2478599268
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1846426768
Short name T686
Test name
Test status
Simulation time 589729209253 ps
CPU time 326.07 seconds
Started Aug 04 05:03:10 PM PDT 24
Finished Aug 04 05:08:36 PM PDT 24
Peak memory 201300 kb
Host smart-2d074573-48c4-48e4-9990-cb10a85641a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846426768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1846426768
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.828503115
Short name T736
Test name
Test status
Simulation time 99701111724 ps
CPU time 373.9 seconds
Started Aug 04 05:03:13 PM PDT 24
Finished Aug 04 05:09:27 PM PDT 24
Peak memory 201796 kb
Host smart-b6612c97-8a45-4848-9d7c-66b29dabf3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828503115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.828503115
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.247596943
Short name T774
Test name
Test status
Simulation time 32805827507 ps
CPU time 37.95 seconds
Started Aug 04 05:03:11 PM PDT 24
Finished Aug 04 05:03:49 PM PDT 24
Peak memory 201244 kb
Host smart-5cbe229b-0ad2-43fe-b435-cd4750dee21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247596943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.247596943
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3716699872
Short name T649
Test name
Test status
Simulation time 3859180422 ps
CPU time 2.65 seconds
Started Aug 04 05:03:09 PM PDT 24
Finished Aug 04 05:03:12 PM PDT 24
Peak memory 201252 kb
Host smart-98ef4c9a-c199-418d-9f4c-0e960eef551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716699872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3716699872
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.4269830593
Short name T41
Test name
Test status
Simulation time 5994200311 ps
CPU time 1.9 seconds
Started Aug 04 05:03:07 PM PDT 24
Finished Aug 04 05:03:09 PM PDT 24
Peak memory 201312 kb
Host smart-d7a306aa-4e0d-45e0-8eed-6e075845ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269830593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.4269830593
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3294496091
Short name T694
Test name
Test status
Simulation time 370509860187 ps
CPU time 207.03 seconds
Started Aug 04 05:03:14 PM PDT 24
Finished Aug 04 05:06:41 PM PDT 24
Peak memory 201416 kb
Host smart-b6dbc798-b5d1-4008-b44c-7902a3fd505d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294496091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3294496091
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.233345123
Short name T14
Test name
Test status
Simulation time 40104986459 ps
CPU time 102.2 seconds
Started Aug 04 05:03:14 PM PDT 24
Finished Aug 04 05:04:57 PM PDT 24
Peak memory 210096 kb
Host smart-606ea83e-d5c6-45d2-8e65-1b9f4e6e3c4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233345123 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.233345123
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.415207080
Short name T656
Test name
Test status
Simulation time 388697730 ps
CPU time 0.82 seconds
Started Aug 04 05:03:24 PM PDT 24
Finished Aug 04 05:03:25 PM PDT 24
Peak memory 201100 kb
Host smart-41a247c9-098b-44b6-9c17-d014ea3d94bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415207080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.415207080
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1470834212
Short name T243
Test name
Test status
Simulation time 657325595332 ps
CPU time 1341.9 seconds
Started Aug 04 05:03:22 PM PDT 24
Finished Aug 04 05:25:44 PM PDT 24
Peak memory 201416 kb
Host smart-58f085c4-53d2-4624-9d2f-99fd3ad673d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470834212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1470834212
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1317168347
Short name T285
Test name
Test status
Simulation time 491773943723 ps
CPU time 1078.77 seconds
Started Aug 04 05:03:19 PM PDT 24
Finished Aug 04 05:21:18 PM PDT 24
Peak memory 201284 kb
Host smart-2eedfbe6-6349-4510-9489-e57cb725e95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317168347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1317168347
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3404079708
Short name T351
Test name
Test status
Simulation time 327783011997 ps
CPU time 106.11 seconds
Started Aug 04 05:03:19 PM PDT 24
Finished Aug 04 05:05:06 PM PDT 24
Peak memory 201272 kb
Host smart-b514aabc-522c-4e87-bc8b-e6924450d6bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404079708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3404079708
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.4203797304
Short name T86
Test name
Test status
Simulation time 484213984562 ps
CPU time 595.89 seconds
Started Aug 04 05:03:17 PM PDT 24
Finished Aug 04 05:13:13 PM PDT 24
Peak memory 201316 kb
Host smart-2595a277-4ac8-41f9-a7d2-22d5d81a908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203797304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4203797304
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3324783974
Short name T667
Test name
Test status
Simulation time 491498043855 ps
CPU time 1046.24 seconds
Started Aug 04 05:03:17 PM PDT 24
Finished Aug 04 05:20:44 PM PDT 24
Peak memory 201396 kb
Host smart-e9f6cbb0-f538-4c29-b7c4-0305e5b984e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324783974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3324783974
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1526383190
Short name T284
Test name
Test status
Simulation time 172047716324 ps
CPU time 92.29 seconds
Started Aug 04 05:03:21 PM PDT 24
Finished Aug 04 05:04:54 PM PDT 24
Peak memory 201344 kb
Host smart-a0685cc8-3185-44f7-9e2c-954620f8b456
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526383190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1526383190
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.799910272
Short name T705
Test name
Test status
Simulation time 203258244073 ps
CPU time 120.08 seconds
Started Aug 04 05:03:17 PM PDT 24
Finished Aug 04 05:05:17 PM PDT 24
Peak memory 201348 kb
Host smart-711ed677-f2db-441e-8fa3-8f9b294d9fe2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799910272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.799910272
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1914769340
Short name T184
Test name
Test status
Simulation time 108762976326 ps
CPU time 381.98 seconds
Started Aug 04 05:03:23 PM PDT 24
Finished Aug 04 05:09:45 PM PDT 24
Peak memory 201676 kb
Host smart-b7b2726a-cb86-4fe2-9f80-b20bcab6238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914769340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1914769340
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1941955897
Short name T651
Test name
Test status
Simulation time 39642753196 ps
CPU time 24.84 seconds
Started Aug 04 05:03:22 PM PDT 24
Finished Aug 04 05:03:47 PM PDT 24
Peak memory 201196 kb
Host smart-8ce38fd2-f4fd-44c9-a507-6a9ba66c8075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941955897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1941955897
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3075514360
Short name T358
Test name
Test status
Simulation time 4354146834 ps
CPU time 1.81 seconds
Started Aug 04 05:03:17 PM PDT 24
Finished Aug 04 05:03:19 PM PDT 24
Peak memory 201268 kb
Host smart-c05187e1-50cc-410c-bfba-7882e70ebbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075514360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3075514360
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2581963458
Short name T726
Test name
Test status
Simulation time 5540766434 ps
CPU time 7.48 seconds
Started Aug 04 05:03:13 PM PDT 24
Finished Aug 04 05:03:21 PM PDT 24
Peak memory 201308 kb
Host smart-9d3b4946-791d-4c87-a7cf-c674cf823498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581963458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2581963458
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.550299609
Short name T608
Test name
Test status
Simulation time 369542870914 ps
CPU time 223.79 seconds
Started Aug 04 05:03:21 PM PDT 24
Finished Aug 04 05:07:05 PM PDT 24
Peak memory 201456 kb
Host smart-05efc38b-f4e5-44e0-bdd8-45ed50791f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550299609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
550299609
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1146099499
Short name T723
Test name
Test status
Simulation time 260228035871 ps
CPU time 66.3 seconds
Started Aug 04 05:03:24 PM PDT 24
Finished Aug 04 05:04:30 PM PDT 24
Peak memory 217816 kb
Host smart-a0d21263-d934-474f-881f-1e637dbe0009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146099499 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1146099499
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3287023758
Short name T530
Test name
Test status
Simulation time 342161777 ps
CPU time 0.76 seconds
Started Aug 04 05:03:33 PM PDT 24
Finished Aug 04 05:03:34 PM PDT 24
Peak memory 201184 kb
Host smart-3e559127-5e96-4a73-8500-1c954af15a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287023758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3287023758
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3130480155
Short name T473
Test name
Test status
Simulation time 549534606014 ps
CPU time 321.96 seconds
Started Aug 04 05:03:25 PM PDT 24
Finished Aug 04 05:08:47 PM PDT 24
Peak memory 201316 kb
Host smart-e1988b5a-590b-474f-8d26-f9fdb84bc862
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130480155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3130480155
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1215275624
Short name T607
Test name
Test status
Simulation time 367092009249 ps
CPU time 810.6 seconds
Started Aug 04 05:03:29 PM PDT 24
Finished Aug 04 05:17:00 PM PDT 24
Peak memory 201368 kb
Host smart-1df88a18-7b83-4347-ae9e-ee5e523e3001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215275624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1215275624
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2443661915
Short name T213
Test name
Test status
Simulation time 318086599089 ps
CPU time 364.43 seconds
Started Aug 04 05:03:23 PM PDT 24
Finished Aug 04 05:09:28 PM PDT 24
Peak memory 201336 kb
Host smart-a3221207-8d27-4417-ae8d-43d499f526ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443661915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2443661915
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3885979304
Short name T242
Test name
Test status
Simulation time 497224739999 ps
CPU time 436.54 seconds
Started Aug 04 05:03:23 PM PDT 24
Finished Aug 04 05:10:40 PM PDT 24
Peak memory 201344 kb
Host smart-defabff4-ad85-448e-be62-af18d3bee1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885979304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3885979304
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2165049564
Short name T561
Test name
Test status
Simulation time 165552027241 ps
CPU time 387.74 seconds
Started Aug 04 05:03:26 PM PDT 24
Finished Aug 04 05:09:54 PM PDT 24
Peak memory 201380 kb
Host smart-27d97938-41ab-4944-88e4-2f1e45fd43e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165049564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2165049564
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1474678313
Short name T129
Test name
Test status
Simulation time 173347670552 ps
CPU time 99.94 seconds
Started Aug 04 05:03:26 PM PDT 24
Finished Aug 04 05:05:06 PM PDT 24
Peak memory 201356 kb
Host smart-3502f184-62c0-4b4f-bbfd-f318a499b51b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474678313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1474678313
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3924461301
Short name T676
Test name
Test status
Simulation time 396451932744 ps
CPU time 445.61 seconds
Started Aug 04 05:03:29 PM PDT 24
Finished Aug 04 05:10:54 PM PDT 24
Peak memory 201384 kb
Host smart-660c83a0-89c1-45ee-b2a5-9f42cb30e1f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924461301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3924461301
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3234086022
Short name T665
Test name
Test status
Simulation time 84366344137 ps
CPU time 348.09 seconds
Started Aug 04 05:03:32 PM PDT 24
Finished Aug 04 05:09:20 PM PDT 24
Peak memory 201732 kb
Host smart-cf32b800-5fe1-41f2-9955-2848a0ca30df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234086022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3234086022
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.35135809
Short name T346
Test name
Test status
Simulation time 24804774022 ps
CPU time 54.83 seconds
Started Aug 04 05:03:32 PM PDT 24
Finished Aug 04 05:04:27 PM PDT 24
Peak memory 201216 kb
Host smart-6370b675-df5b-4064-95de-cdc6c13477f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35135809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.35135809
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2914195329
Short name T499
Test name
Test status
Simulation time 4087766376 ps
CPU time 2.96 seconds
Started Aug 04 05:03:30 PM PDT 24
Finished Aug 04 05:03:33 PM PDT 24
Peak memory 201236 kb
Host smart-9636dc89-be8b-4d4c-9d2f-a361d042036d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914195329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2914195329
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1902571857
Short name T689
Test name
Test status
Simulation time 5856328879 ps
CPU time 3.97 seconds
Started Aug 04 05:03:20 PM PDT 24
Finished Aug 04 05:03:24 PM PDT 24
Peak memory 201272 kb
Host smart-c6b151b9-84c0-4209-8065-c5180956dd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902571857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1902571857
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3747091790
Short name T27
Test name
Test status
Simulation time 374408751 ps
CPU time 0.93 seconds
Started Aug 04 04:58:03 PM PDT 24
Finished Aug 04 04:58:04 PM PDT 24
Peak memory 201216 kb
Host smart-b42bba1f-9e61-4543-9b38-70866e28cd81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747091790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3747091790
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2777713487
Short name T605
Test name
Test status
Simulation time 493318674897 ps
CPU time 445.55 seconds
Started Aug 04 04:57:59 PM PDT 24
Finished Aug 04 05:05:25 PM PDT 24
Peak memory 201408 kb
Host smart-9e6f928a-b21d-40ad-a47b-64cfd413e607
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777713487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2777713487
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1658356453
Short name T400
Test name
Test status
Simulation time 237073590078 ps
CPU time 268.81 seconds
Started Aug 04 04:57:58 PM PDT 24
Finished Aug 04 05:02:27 PM PDT 24
Peak memory 201284 kb
Host smart-647f234d-e3d0-446a-8bbd-6c517fc7f3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658356453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1658356453
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3978717505
Short name T326
Test name
Test status
Simulation time 327731891943 ps
CPU time 191.46 seconds
Started Aug 04 04:57:57 PM PDT 24
Finished Aug 04 05:01:09 PM PDT 24
Peak memory 201428 kb
Host smart-11c9f834-1745-4894-b2af-62f5dbf4d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978717505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3978717505
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2824819958
Short name T539
Test name
Test status
Simulation time 494082067770 ps
CPU time 289.39 seconds
Started Aug 04 04:57:58 PM PDT 24
Finished Aug 04 05:02:48 PM PDT 24
Peak memory 201324 kb
Host smart-b9c1bb69-c2e8-4466-8924-fa75d01633d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824819958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2824819958
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3225588848
Short name T697
Test name
Test status
Simulation time 324612101221 ps
CPU time 404.81 seconds
Started Aug 04 04:57:57 PM PDT 24
Finished Aug 04 05:04:43 PM PDT 24
Peak memory 201340 kb
Host smart-dbf6651d-7cb5-4772-9d18-3a91f0cd13ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225588848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3225588848
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2915996030
Short name T131
Test name
Test status
Simulation time 390632153132 ps
CPU time 323.72 seconds
Started Aug 04 04:57:58 PM PDT 24
Finished Aug 04 05:03:22 PM PDT 24
Peak memory 201404 kb
Host smart-b5ffe63f-428d-40a4-b792-428e38d76ad0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915996030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2915996030
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3943783644
Short name T754
Test name
Test status
Simulation time 203910087709 ps
CPU time 116.84 seconds
Started Aug 04 04:57:57 PM PDT 24
Finished Aug 04 04:59:54 PM PDT 24
Peak memory 201428 kb
Host smart-5b7b0ce6-0217-4b6e-a8d3-002f0c25aff5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943783644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3943783644
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2702650720
Short name T337
Test name
Test status
Simulation time 88472230768 ps
CPU time 462.98 seconds
Started Aug 04 04:57:58 PM PDT 24
Finished Aug 04 05:05:41 PM PDT 24
Peak memory 201680 kb
Host smart-30c12b91-aacb-41a8-bf7c-6b797bc1199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702650720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2702650720
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2562586461
Short name T379
Test name
Test status
Simulation time 34166429922 ps
CPU time 82.33 seconds
Started Aug 04 04:57:59 PM PDT 24
Finished Aug 04 04:59:21 PM PDT 24
Peak memory 201264 kb
Host smart-8ba9042d-df55-47e8-88fe-e3df63bb4d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562586461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2562586461
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3292142492
Short name T569
Test name
Test status
Simulation time 5240103579 ps
CPU time 12.35 seconds
Started Aug 04 04:57:59 PM PDT 24
Finished Aug 04 04:58:12 PM PDT 24
Peak memory 201296 kb
Host smart-878b7e2c-d141-4357-a3ee-0aa66e4059e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292142492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3292142492
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2499655519
Short name T68
Test name
Test status
Simulation time 4197730524 ps
CPU time 1.46 seconds
Started Aug 04 04:58:02 PM PDT 24
Finished Aug 04 04:58:03 PM PDT 24
Peak memory 217236 kb
Host smart-74ebdb33-9e8e-4d98-aa9f-2a72de6f467b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499655519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2499655519
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.492645094
Short name T559
Test name
Test status
Simulation time 6043749745 ps
CPU time 13.57 seconds
Started Aug 04 04:58:00 PM PDT 24
Finished Aug 04 04:58:14 PM PDT 24
Peak memory 201220 kb
Host smart-25ea60b5-90f6-423e-bf4d-6cbcc6642761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492645094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.492645094
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2247053544
Short name T512
Test name
Test status
Simulation time 166326602480 ps
CPU time 318.11 seconds
Started Aug 04 04:58:01 PM PDT 24
Finished Aug 04 05:03:19 PM PDT 24
Peak memory 201348 kb
Host smart-a75d6ab0-1a65-420a-9187-9a1a64a72781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247053544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2247053544
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3148081315
Short name T789
Test name
Test status
Simulation time 836610469458 ps
CPU time 95.44 seconds
Started Aug 04 04:58:01 PM PDT 24
Finished Aug 04 04:59:36 PM PDT 24
Peak memory 209780 kb
Host smart-7889db2b-a502-45e2-916b-0b90874ce44f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148081315 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3148081315
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3450226424
Short name T613
Test name
Test status
Simulation time 423476864 ps
CPU time 0.8 seconds
Started Aug 04 05:03:43 PM PDT 24
Finished Aug 04 05:03:44 PM PDT 24
Peak memory 200620 kb
Host smart-94a04aee-cb17-4454-b7c3-b8cb6cbed3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450226424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3450226424
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2021558240
Short name T414
Test name
Test status
Simulation time 330040662979 ps
CPU time 207.93 seconds
Started Aug 04 05:03:37 PM PDT 24
Finished Aug 04 05:07:05 PM PDT 24
Peak memory 201320 kb
Host smart-109418bc-c52e-4622-a57b-30e7e20b5dc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021558240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2021558240
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3163231814
Short name T147
Test name
Test status
Simulation time 158134370005 ps
CPU time 346.64 seconds
Started Aug 04 05:03:37 PM PDT 24
Finished Aug 04 05:09:24 PM PDT 24
Peak memory 201292 kb
Host smart-d3339e5a-5a5d-4fe0-8b02-a184371a3248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163231814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3163231814
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.478607343
Short name T25
Test name
Test status
Simulation time 488343104519 ps
CPU time 1074.63 seconds
Started Aug 04 05:03:40 PM PDT 24
Finished Aug 04 05:21:35 PM PDT 24
Peak memory 201376 kb
Host smart-ddffa850-8e7b-444c-ac14-57d1a8ed7579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478607343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.478607343
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.4249552765
Short name T26
Test name
Test status
Simulation time 164614527041 ps
CPU time 334.38 seconds
Started Aug 04 05:03:39 PM PDT 24
Finished Aug 04 05:09:13 PM PDT 24
Peak memory 201408 kb
Host smart-0a3082f0-3f3e-4956-8e26-5adc996becd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249552765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.4249552765
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2889020975
Short name T681
Test name
Test status
Simulation time 169487632354 ps
CPU time 365.23 seconds
Started Aug 04 05:03:34 PM PDT 24
Finished Aug 04 05:09:40 PM PDT 24
Peak memory 201388 kb
Host smart-7411fc78-cd8d-42cc-8b6e-2be922a058cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889020975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2889020975
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.132016140
Short name T724
Test name
Test status
Simulation time 333139813839 ps
CPU time 693.03 seconds
Started Aug 04 05:03:37 PM PDT 24
Finished Aug 04 05:15:10 PM PDT 24
Peak memory 201364 kb
Host smart-28275362-827d-484a-92a2-991ff3ef01bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=132016140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.132016140
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3103768317
Short name T218
Test name
Test status
Simulation time 174307478157 ps
CPU time 24.99 seconds
Started Aug 04 05:03:36 PM PDT 24
Finished Aug 04 05:04:01 PM PDT 24
Peak memory 201384 kb
Host smart-7f99036b-6f9b-4f4f-a161-a4a18f2e36e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103768317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3103768317
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.805564135
Short name T698
Test name
Test status
Simulation time 399249821594 ps
CPU time 809.19 seconds
Started Aug 04 05:03:41 PM PDT 24
Finished Aug 04 05:17:11 PM PDT 24
Peak memory 201404 kb
Host smart-2f43489f-5c2a-4538-94c2-6362729370b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805564135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.805564135
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1524860731
Short name T368
Test name
Test status
Simulation time 89836690503 ps
CPU time 309.25 seconds
Started Aug 04 05:03:38 PM PDT 24
Finished Aug 04 05:08:47 PM PDT 24
Peak memory 201760 kb
Host smart-a6fd3bb7-353a-4cf8-a62a-65fe7f00151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524860731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1524860731
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2361607408
Short name T717
Test name
Test status
Simulation time 44051447698 ps
CPU time 93.68 seconds
Started Aug 04 05:03:39 PM PDT 24
Finished Aug 04 05:05:12 PM PDT 24
Peak memory 201252 kb
Host smart-a2a59028-1727-4239-a077-4f536e9cf0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361607408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2361607408
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.91712196
Short name T345
Test name
Test status
Simulation time 3509791071 ps
CPU time 4.66 seconds
Started Aug 04 05:03:36 PM PDT 24
Finished Aug 04 05:03:41 PM PDT 24
Peak memory 201196 kb
Host smart-9945c1cb-0c7a-43f7-a10a-39068c4730de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91712196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.91712196
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.294084658
Short name T582
Test name
Test status
Simulation time 5763912753 ps
CPU time 13.94 seconds
Started Aug 04 05:03:33 PM PDT 24
Finished Aug 04 05:03:47 PM PDT 24
Peak memory 201288 kb
Host smart-09749db0-8d40-4185-9e72-7bf1a2693a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294084658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.294084658
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3489930787
Short name T623
Test name
Test status
Simulation time 684454420287 ps
CPU time 704.08 seconds
Started Aug 04 05:03:44 PM PDT 24
Finished Aug 04 05:15:28 PM PDT 24
Peak memory 200804 kb
Host smart-d733273d-b001-498d-a391-360df2cab947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489930787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3489930787
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1652020792
Short name T448
Test name
Test status
Simulation time 93996493206 ps
CPU time 205.86 seconds
Started Aug 04 05:03:42 PM PDT 24
Finished Aug 04 05:07:08 PM PDT 24
Peak memory 211504 kb
Host smart-f7bdcaa9-de1b-4d0b-a87a-29221b7fa03f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652020792 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1652020792
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1719593608
Short name T506
Test name
Test status
Simulation time 448050489 ps
CPU time 1.16 seconds
Started Aug 04 05:03:58 PM PDT 24
Finished Aug 04 05:03:59 PM PDT 24
Peak memory 201140 kb
Host smart-35da63f7-c9b7-403a-bb99-1e75d269b287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719593608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1719593608
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1293209457
Short name T639
Test name
Test status
Simulation time 367505312439 ps
CPU time 716.18 seconds
Started Aug 04 05:03:52 PM PDT 24
Finished Aug 04 05:15:48 PM PDT 24
Peak memory 201288 kb
Host smart-6030b9b3-2c01-4d7e-b9ba-a83c3c8cd117
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293209457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1293209457
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.465752465
Short name T140
Test name
Test status
Simulation time 167968385769 ps
CPU time 212.99 seconds
Started Aug 04 05:03:42 PM PDT 24
Finished Aug 04 05:07:15 PM PDT 24
Peak memory 201360 kb
Host smart-32526cf6-c7a8-4651-b364-7ad59ea555fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465752465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.465752465
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1780685620
Short name T356
Test name
Test status
Simulation time 328020182286 ps
CPU time 191.9 seconds
Started Aug 04 05:03:42 PM PDT 24
Finished Aug 04 05:06:54 PM PDT 24
Peak memory 201344 kb
Host smart-7f203749-c2fb-4ac7-a03c-ea82afb277d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780685620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1780685620
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.4755938
Short name T146
Test name
Test status
Simulation time 490901747291 ps
CPU time 286.18 seconds
Started Aug 04 05:03:44 PM PDT 24
Finished Aug 04 05:08:31 PM PDT 24
Peak memory 201376 kb
Host smart-2f4d46c2-d191-4904-bf57-583e813a0059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4755938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.4755938
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1885064765
Short name T634
Test name
Test status
Simulation time 487595405499 ps
CPU time 256.11 seconds
Started Aug 04 05:03:42 PM PDT 24
Finished Aug 04 05:07:59 PM PDT 24
Peak memory 201412 kb
Host smart-62aaa4bf-41a3-4be1-9be8-a33727863b72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885064765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1885064765
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2635157313
Short name T217
Test name
Test status
Simulation time 553337677354 ps
CPU time 1202.65 seconds
Started Aug 04 05:03:47 PM PDT 24
Finished Aug 04 05:23:50 PM PDT 24
Peak memory 201312 kb
Host smart-99ee902d-201d-477f-a166-43962a71b3c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635157313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2635157313
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2548254301
Short name T364
Test name
Test status
Simulation time 207548074132 ps
CPU time 218.65 seconds
Started Aug 04 05:03:46 PM PDT 24
Finished Aug 04 05:07:25 PM PDT 24
Peak memory 201360 kb
Host smart-752733ee-351e-4455-b5b7-b5a5bff50702
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548254301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2548254301
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.785817174
Short name T495
Test name
Test status
Simulation time 23061411788 ps
CPU time 56.93 seconds
Started Aug 04 05:03:52 PM PDT 24
Finished Aug 04 05:04:49 PM PDT 24
Peak memory 201244 kb
Host smart-ad68e186-dcf5-479d-86b8-6e7cadcfa73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785817174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.785817174
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4103949233
Short name T347
Test name
Test status
Simulation time 4764421285 ps
CPU time 11.62 seconds
Started Aug 04 05:03:53 PM PDT 24
Finished Aug 04 05:04:05 PM PDT 24
Peak memory 201244 kb
Host smart-5dc87634-42ef-4bfb-838f-99f86c223020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103949233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4103949233
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2483331928
Short name T91
Test name
Test status
Simulation time 5875105265 ps
CPU time 3.92 seconds
Started Aug 04 05:03:44 PM PDT 24
Finished Aug 04 05:03:48 PM PDT 24
Peak memory 201292 kb
Host smart-ba340fc4-90a6-432c-a0af-d1c762617561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483331928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2483331928
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.108905717
Short name T35
Test name
Test status
Simulation time 167463896464 ps
CPU time 95.49 seconds
Started Aug 04 05:03:51 PM PDT 24
Finished Aug 04 05:05:27 PM PDT 24
Peak memory 209680 kb
Host smart-c2ec07f6-c24f-4ad5-b718-4d6b9d07aa94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108905717 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.108905717
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.4223071493
Short name T788
Test name
Test status
Simulation time 523505879 ps
CPU time 0.7 seconds
Started Aug 04 05:04:05 PM PDT 24
Finished Aug 04 05:04:06 PM PDT 24
Peak memory 201172 kb
Host smart-ce09836f-cda0-42d0-b4b4-c38a4c15398f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223071493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.4223071493
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3401171030
Short name T271
Test name
Test status
Simulation time 385003140458 ps
CPU time 412.69 seconds
Started Aug 04 05:04:02 PM PDT 24
Finished Aug 04 05:10:55 PM PDT 24
Peak memory 201368 kb
Host smart-10e5550d-5bb1-4e81-8cf6-5feb6f5c86fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401171030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3401171030
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3943164070
Short name T673
Test name
Test status
Simulation time 336319138147 ps
CPU time 694.72 seconds
Started Aug 04 05:03:56 PM PDT 24
Finished Aug 04 05:15:30 PM PDT 24
Peak memory 201440 kb
Host smart-0ec198e7-d78e-4c56-91d5-df2f95a5d025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943164070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3943164070
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2092461172
Short name T684
Test name
Test status
Simulation time 490084272499 ps
CPU time 1016.97 seconds
Started Aug 04 05:03:55 PM PDT 24
Finished Aug 04 05:20:53 PM PDT 24
Peak memory 201404 kb
Host smart-1514d5d2-1e9f-4209-a392-7427af09fa0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092461172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2092461172
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1813562758
Short name T602
Test name
Test status
Simulation time 163297073991 ps
CPU time 394.67 seconds
Started Aug 04 05:03:55 PM PDT 24
Finished Aug 04 05:10:30 PM PDT 24
Peak memory 201380 kb
Host smart-be4c72d7-c0be-47db-8a13-f34062ab4279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813562758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1813562758
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.860752327
Short name T493
Test name
Test status
Simulation time 328927064995 ps
CPU time 715.01 seconds
Started Aug 04 05:03:57 PM PDT 24
Finished Aug 04 05:15:52 PM PDT 24
Peak memory 201284 kb
Host smart-1b18cf88-cb3e-4e8f-9572-8f8107bfdb83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=860752327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.860752327
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1389147564
Short name T490
Test name
Test status
Simulation time 276068455911 ps
CPU time 159.67 seconds
Started Aug 04 05:03:55 PM PDT 24
Finished Aug 04 05:06:35 PM PDT 24
Peak memory 201328 kb
Host smart-68d64ddf-34b7-4c5d-aa00-403581df01ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389147564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1389147564
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1950729502
Short name T498
Test name
Test status
Simulation time 404744988684 ps
CPU time 249.34 seconds
Started Aug 04 05:04:04 PM PDT 24
Finished Aug 04 05:08:14 PM PDT 24
Peak memory 201292 kb
Host smart-7db02f84-46c1-454d-bb4a-34770100c693
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950729502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1950729502
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.323214869
Short name T183
Test name
Test status
Simulation time 103126818887 ps
CPU time 428.91 seconds
Started Aug 04 05:04:06 PM PDT 24
Finished Aug 04 05:11:15 PM PDT 24
Peak memory 201780 kb
Host smart-2c0097db-ca07-4680-b5e9-47bea69829af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323214869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.323214869
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3153550771
Short name T394
Test name
Test status
Simulation time 22651926162 ps
CPU time 9.69 seconds
Started Aug 04 05:04:06 PM PDT 24
Finished Aug 04 05:04:16 PM PDT 24
Peak memory 201272 kb
Host smart-6ab2e46c-8891-403f-86d2-877cc8cf8fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153550771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3153550771
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3658212370
Short name T633
Test name
Test status
Simulation time 5214776299 ps
CPU time 6.71 seconds
Started Aug 04 05:04:00 PM PDT 24
Finished Aug 04 05:04:07 PM PDT 24
Peak memory 201336 kb
Host smart-fe514fa5-6553-4378-a70b-5f2497be5ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658212370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3658212370
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1426263566
Short name T352
Test name
Test status
Simulation time 6028525976 ps
CPU time 7.81 seconds
Started Aug 04 05:03:56 PM PDT 24
Finished Aug 04 05:04:04 PM PDT 24
Peak memory 201280 kb
Host smart-815a93a9-9397-4e20-960c-082601973e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426263566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1426263566
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3855609941
Short name T192
Test name
Test status
Simulation time 1156759345190 ps
CPU time 3120.08 seconds
Started Aug 04 05:04:07 PM PDT 24
Finished Aug 04 05:56:07 PM PDT 24
Peak memory 218088 kb
Host smart-bfe80a51-2f86-4106-b3b5-c1906160d776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855609941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3855609941
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.564417418
Short name T688
Test name
Test status
Simulation time 94056679963 ps
CPU time 221.52 seconds
Started Aug 04 05:04:06 PM PDT 24
Finished Aug 04 05:07:48 PM PDT 24
Peak memory 210088 kb
Host smart-c7b0b288-010b-4bb3-9886-3b9c39158d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564417418 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.564417418
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3173091516
Short name T439
Test name
Test status
Simulation time 464347230 ps
CPU time 1.61 seconds
Started Aug 04 05:04:17 PM PDT 24
Finished Aug 04 05:04:18 PM PDT 24
Peak memory 201156 kb
Host smart-421153d2-e542-4e52-9463-deee5a3e21ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173091516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3173091516
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3463301202
Short name T790
Test name
Test status
Simulation time 507151060704 ps
CPU time 330.13 seconds
Started Aug 04 05:04:17 PM PDT 24
Finished Aug 04 05:09:47 PM PDT 24
Peak memory 201344 kb
Host smart-ca925fc7-498c-4260-96cc-d60378587ad1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463301202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3463301202
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.4118302932
Short name T703
Test name
Test status
Simulation time 332209143126 ps
CPU time 112.25 seconds
Started Aug 04 05:04:14 PM PDT 24
Finished Aug 04 05:06:07 PM PDT 24
Peak memory 201320 kb
Host smart-b876874e-c5c7-432b-9b78-e625b13a6691
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118302932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.4118302932
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3849419367
Short name T254
Test name
Test status
Simulation time 330987859674 ps
CPU time 790.85 seconds
Started Aug 04 05:04:05 PM PDT 24
Finished Aug 04 05:17:16 PM PDT 24
Peak memory 201348 kb
Host smart-95a15c60-dde8-4903-864e-37dba5edff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849419367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3849419367
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.200745534
Short name T1
Test name
Test status
Simulation time 165784238050 ps
CPU time 92.94 seconds
Started Aug 04 05:04:14 PM PDT 24
Finished Aug 04 05:05:47 PM PDT 24
Peak memory 201352 kb
Host smart-3672d69f-51db-49f4-b199-ba317007e9a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=200745534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.200745534
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3673219843
Short name T198
Test name
Test status
Simulation time 357651960246 ps
CPU time 322.37 seconds
Started Aug 04 05:04:13 PM PDT 24
Finished Aug 04 05:09:36 PM PDT 24
Peak memory 201364 kb
Host smart-0019c433-8cc8-448f-80a5-d55ac982d122
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673219843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3673219843
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3789612455
Short name T783
Test name
Test status
Simulation time 592705557446 ps
CPU time 1394.02 seconds
Started Aug 04 05:04:12 PM PDT 24
Finished Aug 04 05:27:27 PM PDT 24
Peak memory 201400 kb
Host smart-cbaae2d4-67a1-4d41-b9fb-df5fc30958d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789612455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3789612455
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1804139065
Short name T566
Test name
Test status
Simulation time 72502842582 ps
CPU time 386.33 seconds
Started Aug 04 05:04:17 PM PDT 24
Finished Aug 04 05:10:44 PM PDT 24
Peak memory 201680 kb
Host smart-e9dcc461-8025-4bba-82d0-b8846573743a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804139065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1804139065
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1119787604
Short name T348
Test name
Test status
Simulation time 34013724455 ps
CPU time 4.65 seconds
Started Aug 04 05:04:15 PM PDT 24
Finished Aug 04 05:04:20 PM PDT 24
Peak memory 201312 kb
Host smart-7089b84e-fb02-4a80-b5ab-6c7892d6d5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119787604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1119787604
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2854872558
Short name T396
Test name
Test status
Simulation time 4525709302 ps
CPU time 3.18 seconds
Started Aug 04 05:04:28 PM PDT 24
Finished Aug 04 05:04:31 PM PDT 24
Peak memory 201276 kb
Host smart-71621cae-f13b-464f-841d-a5a1e9e2eb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854872558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2854872558
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2006361591
Short name T445
Test name
Test status
Simulation time 6050449845 ps
CPU time 1.71 seconds
Started Aug 04 05:04:07 PM PDT 24
Finished Aug 04 05:04:09 PM PDT 24
Peak memory 201276 kb
Host smart-452f2c22-a182-4164-8c1b-bced7348e3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006361591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2006361591
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3445579323
Short name T660
Test name
Test status
Simulation time 7299327145 ps
CPU time 2.58 seconds
Started Aug 04 05:04:16 PM PDT 24
Finished Aug 04 05:04:18 PM PDT 24
Peak memory 201316 kb
Host smart-48b51d5d-bc67-47c9-9356-bda07894748e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445579323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3445579323
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3588827355
Short name T538
Test name
Test status
Simulation time 29904679462 ps
CPU time 76.51 seconds
Started Aug 04 05:04:16 PM PDT 24
Finished Aug 04 05:05:33 PM PDT 24
Peak memory 215052 kb
Host smart-1dd25421-ae42-4097-9bf7-1d481d15603b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588827355 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3588827355
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.357417817
Short name T669
Test name
Test status
Simulation time 492913750 ps
CPU time 0.92 seconds
Started Aug 04 05:04:28 PM PDT 24
Finished Aug 04 05:04:29 PM PDT 24
Peak memory 201108 kb
Host smart-7e2ac227-56e7-42ac-8c69-2c906bd9c58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357417817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.357417817
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3633492068
Short name T502
Test name
Test status
Simulation time 356797054266 ps
CPU time 219.01 seconds
Started Aug 04 05:04:21 PM PDT 24
Finished Aug 04 05:08:00 PM PDT 24
Peak memory 201300 kb
Host smart-7cfe4c29-c518-4723-b1d2-77f68cbf1fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633492068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3633492068
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2035388277
Short name T291
Test name
Test status
Simulation time 487838325094 ps
CPU time 1118.35 seconds
Started Aug 04 05:04:20 PM PDT 24
Finished Aug 04 05:22:58 PM PDT 24
Peak memory 201352 kb
Host smart-afcdbc6c-6320-4c6b-a0f0-8e9cd9db6049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035388277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2035388277
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2185003154
Short name T372
Test name
Test status
Simulation time 327597911575 ps
CPU time 386.19 seconds
Started Aug 04 05:04:23 PM PDT 24
Finished Aug 04 05:10:49 PM PDT 24
Peak memory 201328 kb
Host smart-9b0522e2-af35-42e8-9e00-82c45cf0e856
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185003154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2185003154
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.577460141
Short name T573
Test name
Test status
Simulation time 162951394748 ps
CPU time 380.99 seconds
Started Aug 04 05:04:16 PM PDT 24
Finished Aug 04 05:10:37 PM PDT 24
Peak memory 201316 kb
Host smart-4b905522-8f52-46ca-b102-c9b70c79fe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577460141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.577460141
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4163887470
Short name T542
Test name
Test status
Simulation time 163842795330 ps
CPU time 41.42 seconds
Started Aug 04 05:04:16 PM PDT 24
Finished Aug 04 05:04:57 PM PDT 24
Peak memory 201324 kb
Host smart-8dbd1f43-bd3c-4ca3-8595-a79fa1e20a69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163887470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4163887470
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.4147614704
Short name T532
Test name
Test status
Simulation time 374204689736 ps
CPU time 228.48 seconds
Started Aug 04 05:04:21 PM PDT 24
Finished Aug 04 05:08:10 PM PDT 24
Peak memory 201344 kb
Host smart-0f4d27ef-c813-4ba3-b220-10af31f22c68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147614704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.4147614704
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2341862303
Short name T479
Test name
Test status
Simulation time 204631017146 ps
CPU time 121.41 seconds
Started Aug 04 05:04:20 PM PDT 24
Finished Aug 04 05:06:22 PM PDT 24
Peak memory 201312 kb
Host smart-08aef935-9aa9-48f5-b08c-c77fb765e3e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341862303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2341862303
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3570771888
Short name T193
Test name
Test status
Simulation time 122214689704 ps
CPU time 446.23 seconds
Started Aug 04 05:04:25 PM PDT 24
Finished Aug 04 05:11:51 PM PDT 24
Peak memory 201664 kb
Host smart-7e85375a-b29c-469e-a9fe-5b315f3aa295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570771888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3570771888
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1814952290
Short name T465
Test name
Test status
Simulation time 38149678555 ps
CPU time 77.77 seconds
Started Aug 04 05:04:20 PM PDT 24
Finished Aug 04 05:05:38 PM PDT 24
Peak memory 201304 kb
Host smart-e184b2bd-f888-4dba-8dad-06fe2c0ee3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814952290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1814952290
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3315544465
Short name T747
Test name
Test status
Simulation time 4166170680 ps
CPU time 5.29 seconds
Started Aug 04 05:04:20 PM PDT 24
Finished Aug 04 05:04:25 PM PDT 24
Peak memory 201324 kb
Host smart-fab8cf09-b8a9-4e9e-8892-77868f36511a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315544465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3315544465
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2805156908
Short name T360
Test name
Test status
Simulation time 5672830738 ps
CPU time 10.78 seconds
Started Aug 04 05:04:17 PM PDT 24
Finished Aug 04 05:04:28 PM PDT 24
Peak memory 201268 kb
Host smart-169451f8-addd-4ed4-a190-ab3f6a0d9462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805156908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2805156908
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2164722757
Short name T314
Test name
Test status
Simulation time 493598467957 ps
CPU time 1183.74 seconds
Started Aug 04 05:04:24 PM PDT 24
Finished Aug 04 05:24:08 PM PDT 24
Peak memory 201336 kb
Host smart-6bb760e5-b873-4dac-98c0-7809f1b91c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164722757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2164722757
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3067935003
Short name T168
Test name
Test status
Simulation time 43306674156 ps
CPU time 84.52 seconds
Started Aug 04 05:04:23 PM PDT 24
Finished Aug 04 05:05:48 PM PDT 24
Peak memory 210164 kb
Host smart-de6def2c-17e2-4e30-8237-61906525cf69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067935003 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3067935003
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.296370525
Short name T365
Test name
Test status
Simulation time 534336783 ps
CPU time 0.92 seconds
Started Aug 04 05:04:38 PM PDT 24
Finished Aug 04 05:04:39 PM PDT 24
Peak memory 201156 kb
Host smart-9daaa477-bf6d-4dda-bc01-bf60d89df41c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296370525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.296370525
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1393974188
Short name T404
Test name
Test status
Simulation time 166850899886 ps
CPU time 394 seconds
Started Aug 04 05:04:34 PM PDT 24
Finished Aug 04 05:11:08 PM PDT 24
Peak memory 201372 kb
Host smart-cb259f73-4768-4c98-a1a0-7f974f3a8976
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393974188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1393974188
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.54682840
Short name T299
Test name
Test status
Simulation time 158965482152 ps
CPU time 93.85 seconds
Started Aug 04 05:04:37 PM PDT 24
Finished Aug 04 05:06:11 PM PDT 24
Peak memory 201464 kb
Host smart-1eae0ec4-858e-463f-808e-83116a444c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54682840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.54682840
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.103743526
Short name T156
Test name
Test status
Simulation time 175654010151 ps
CPU time 191.48 seconds
Started Aug 04 05:04:34 PM PDT 24
Finished Aug 04 05:07:45 PM PDT 24
Peak memory 201388 kb
Host smart-fe5255ae-4cbf-48fd-9c25-6e1c90e0c1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103743526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.103743526
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2986814084
Short name T519
Test name
Test status
Simulation time 173368452395 ps
CPU time 89.58 seconds
Started Aug 04 05:04:36 PM PDT 24
Finished Aug 04 05:06:06 PM PDT 24
Peak memory 201276 kb
Host smart-5bc9aab9-25af-4466-be06-b3a6c7284747
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986814084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2986814084
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2758871214
Short name T306
Test name
Test status
Simulation time 332614319437 ps
CPU time 730.04 seconds
Started Aug 04 05:04:27 PM PDT 24
Finished Aug 04 05:16:37 PM PDT 24
Peak memory 201376 kb
Host smart-ee51900f-9d54-40e1-ae9c-6ee9dc707e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758871214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2758871214
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1564035345
Short name T641
Test name
Test status
Simulation time 163976526080 ps
CPU time 383.13 seconds
Started Aug 04 05:04:28 PM PDT 24
Finished Aug 04 05:10:51 PM PDT 24
Peak memory 201616 kb
Host smart-f2f77ffa-faab-4e57-826a-5c252eaf80f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564035345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1564035345
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.600873755
Short name T303
Test name
Test status
Simulation time 436406587925 ps
CPU time 244.48 seconds
Started Aug 04 05:04:32 PM PDT 24
Finished Aug 04 05:08:37 PM PDT 24
Peak memory 201332 kb
Host smart-e06c012f-d8fa-4da5-b568-24fbf654fc17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600873755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.600873755
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3111686365
Short name T443
Test name
Test status
Simulation time 199193934997 ps
CPU time 463.49 seconds
Started Aug 04 05:04:33 PM PDT 24
Finished Aug 04 05:12:17 PM PDT 24
Peak memory 201316 kb
Host smart-d3b30ba2-462c-499a-b779-134e834e1abd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111686365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3111686365
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.339260225
Short name T629
Test name
Test status
Simulation time 108408324419 ps
CPU time 394.03 seconds
Started Aug 04 05:04:37 PM PDT 24
Finished Aug 04 05:11:11 PM PDT 24
Peak memory 201772 kb
Host smart-999f15aa-9567-4c4e-a820-ae751f82c3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339260225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.339260225
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2289812304
Short name T395
Test name
Test status
Simulation time 35220575350 ps
CPU time 47.19 seconds
Started Aug 04 05:04:40 PM PDT 24
Finished Aug 04 05:05:27 PM PDT 24
Peak memory 201312 kb
Host smart-333f402e-b777-4799-bcd9-81572237cb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289812304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2289812304
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3292146553
Short name T761
Test name
Test status
Simulation time 3736328597 ps
CPU time 9.32 seconds
Started Aug 04 05:04:39 PM PDT 24
Finished Aug 04 05:04:49 PM PDT 24
Peak memory 201212 kb
Host smart-02674be2-40ff-4c8f-866e-3b7e660f8aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292146553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3292146553
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.600121391
Short name T501
Test name
Test status
Simulation time 5865322529 ps
CPU time 14.02 seconds
Started Aug 04 05:04:30 PM PDT 24
Finished Aug 04 05:04:44 PM PDT 24
Peak memory 201264 kb
Host smart-3def3419-9266-45f4-be88-c279a210fb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600121391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.600121391
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1119306993
Short name T732
Test name
Test status
Simulation time 493070597 ps
CPU time 1.65 seconds
Started Aug 04 05:04:48 PM PDT 24
Finished Aug 04 05:04:50 PM PDT 24
Peak memory 201128 kb
Host smart-04e1efd3-63e6-4faa-b125-60979d5e73d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119306993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1119306993
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4193964496
Short name T256
Test name
Test status
Simulation time 171829208750 ps
CPU time 414.52 seconds
Started Aug 04 05:04:37 PM PDT 24
Finished Aug 04 05:11:32 PM PDT 24
Peak memory 201344 kb
Host smart-49f29400-1cc9-4df5-8062-1ac73bdf00f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193964496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4193964496
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3273127008
Short name T484
Test name
Test status
Simulation time 493317585591 ps
CPU time 517.16 seconds
Started Aug 04 05:04:38 PM PDT 24
Finished Aug 04 05:13:16 PM PDT 24
Peak memory 201340 kb
Host smart-de62ca78-0085-4dab-917d-e4787011a018
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273127008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3273127008
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2929605078
Short name T632
Test name
Test status
Simulation time 492977741117 ps
CPU time 699.74 seconds
Started Aug 04 05:04:38 PM PDT 24
Finished Aug 04 05:16:17 PM PDT 24
Peak memory 201296 kb
Host smart-554b2de6-e5c8-49d7-8202-6e4030cb5e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929605078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2929605078
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1867530006
Short name T362
Test name
Test status
Simulation time 162788914635 ps
CPU time 192.33 seconds
Started Aug 04 05:04:37 PM PDT 24
Finished Aug 04 05:07:49 PM PDT 24
Peak memory 201328 kb
Host smart-8ee14994-f953-441c-8ccd-b73d2a44b11f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867530006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1867530006
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.735970678
Short name T315
Test name
Test status
Simulation time 545263308073 ps
CPU time 681.26 seconds
Started Aug 04 05:04:43 PM PDT 24
Finished Aug 04 05:16:04 PM PDT 24
Peak memory 201420 kb
Host smart-646410b6-c5f7-4f9c-a6c4-c069c4f87ae9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735970678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.735970678
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3545544123
Short name T692
Test name
Test status
Simulation time 197264076943 ps
CPU time 468.18 seconds
Started Aug 04 05:04:42 PM PDT 24
Finished Aug 04 05:12:30 PM PDT 24
Peak memory 201424 kb
Host smart-8827baa0-735d-4e1e-9b1b-6411a768913c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545544123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3545544123
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1288085293
Short name T516
Test name
Test status
Simulation time 76838550633 ps
CPU time 266.34 seconds
Started Aug 04 05:04:41 PM PDT 24
Finished Aug 04 05:09:07 PM PDT 24
Peak memory 201824 kb
Host smart-5ca2146c-fe52-4c85-956e-8d8aa0345c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288085293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1288085293
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3826293219
Short name T652
Test name
Test status
Simulation time 28635698228 ps
CPU time 27.97 seconds
Started Aug 04 05:04:42 PM PDT 24
Finished Aug 04 05:05:10 PM PDT 24
Peak memory 201216 kb
Host smart-60110f39-19c5-4859-a84e-d50df316eff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826293219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3826293219
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3072857140
Short name T580
Test name
Test status
Simulation time 4765172756 ps
CPU time 3.33 seconds
Started Aug 04 05:04:42 PM PDT 24
Finished Aug 04 05:04:46 PM PDT 24
Peak memory 201308 kb
Host smart-3e8c0cce-209a-4438-bdce-874542df1e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072857140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3072857140
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.527881804
Short name T375
Test name
Test status
Simulation time 5922027270 ps
CPU time 15.47 seconds
Started Aug 04 05:04:39 PM PDT 24
Finished Aug 04 05:04:55 PM PDT 24
Peak memory 201212 kb
Host smart-824dcae0-d85a-4bbf-b55f-6d3a12b62c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527881804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.527881804
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1224392162
Short name T88
Test name
Test status
Simulation time 172795795312 ps
CPU time 214.9 seconds
Started Aug 04 05:04:47 PM PDT 24
Finished Aug 04 05:08:22 PM PDT 24
Peak memory 201396 kb
Host smart-ba21d1d8-14cc-4912-a0fc-b3ccd3881860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224392162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1224392162
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.923881091
Short name T762
Test name
Test status
Simulation time 332772002 ps
CPU time 0.92 seconds
Started Aug 04 05:05:00 PM PDT 24
Finished Aug 04 05:05:01 PM PDT 24
Peak memory 201216 kb
Host smart-c24e7644-9f49-4f54-b6a3-96c2a53eb4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923881091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.923881091
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.4250491681
Short name T317
Test name
Test status
Simulation time 503708376110 ps
CPU time 119.12 seconds
Started Aug 04 05:04:51 PM PDT 24
Finished Aug 04 05:06:50 PM PDT 24
Peak memory 201364 kb
Host smart-31846d64-b239-49f8-a5cf-dcc28542add4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250491681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.4250491681
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2665628485
Short name T759
Test name
Test status
Simulation time 165227180879 ps
CPU time 108.89 seconds
Started Aug 04 05:04:51 PM PDT 24
Finished Aug 04 05:06:40 PM PDT 24
Peak memory 201316 kb
Host smart-ef9cd6f7-bbb4-4ad9-89df-7b6b51c28ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665628485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2665628485
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3912451250
Short name T270
Test name
Test status
Simulation time 485205983632 ps
CPU time 1095.74 seconds
Started Aug 04 05:04:51 PM PDT 24
Finished Aug 04 05:23:07 PM PDT 24
Peak memory 201384 kb
Host smart-991ee461-c93f-4c14-9b63-ccc0c9c1b2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912451250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3912451250
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1867558579
Short name T102
Test name
Test status
Simulation time 334480954102 ps
CPU time 152.27 seconds
Started Aug 04 05:04:53 PM PDT 24
Finished Aug 04 05:07:25 PM PDT 24
Peak memory 201284 kb
Host smart-fbeb3c5e-2bd2-43f7-8d98-ccfaa94c3074
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867558579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1867558579
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2643404577
Short name T562
Test name
Test status
Simulation time 341021618742 ps
CPU time 395.2 seconds
Started Aug 04 05:04:52 PM PDT 24
Finished Aug 04 05:11:27 PM PDT 24
Peak memory 201372 kb
Host smart-4d5f377f-7d59-416b-9c15-2e65665dbb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643404577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2643404577
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3107394348
Short name T151
Test name
Test status
Simulation time 334967891693 ps
CPU time 780 seconds
Started Aug 04 05:04:51 PM PDT 24
Finished Aug 04 05:17:51 PM PDT 24
Peak memory 201304 kb
Host smart-bd3c059b-cf53-4aa4-b99d-1175b43731ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107394348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3107394348
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1303103950
Short name T222
Test name
Test status
Simulation time 449569073729 ps
CPU time 207.49 seconds
Started Aug 04 05:04:51 PM PDT 24
Finished Aug 04 05:08:18 PM PDT 24
Peak memory 201344 kb
Host smart-d93f98b6-aa14-448e-b07f-caa74d9c0151
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303103950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1303103950
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2604683052
Short name T511
Test name
Test status
Simulation time 589153681870 ps
CPU time 171.2 seconds
Started Aug 04 05:04:51 PM PDT 24
Finished Aug 04 05:07:42 PM PDT 24
Peak memory 201380 kb
Host smart-4054afd6-0094-4e06-918b-db71b06decba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604683052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2604683052
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1986904589
Short name T190
Test name
Test status
Simulation time 131466545148 ps
CPU time 597.23 seconds
Started Aug 04 05:04:56 PM PDT 24
Finished Aug 04 05:14:53 PM PDT 24
Peak memory 201716 kb
Host smart-0be2f597-a426-4c20-b75a-8350d2f5f80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986904589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1986904589
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.199452364
Short name T150
Test name
Test status
Simulation time 31666190686 ps
CPU time 35.82 seconds
Started Aug 04 05:04:56 PM PDT 24
Finished Aug 04 05:05:32 PM PDT 24
Peak memory 201280 kb
Host smart-6e44643d-3a4c-485e-ae04-8d749584b0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199452364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.199452364
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1736699226
Short name T737
Test name
Test status
Simulation time 3452058836 ps
CPU time 2.49 seconds
Started Aug 04 05:04:56 PM PDT 24
Finished Aug 04 05:04:59 PM PDT 24
Peak memory 201320 kb
Host smart-afaee9e3-81b2-4e1a-a4d0-f7d909c56b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736699226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1736699226
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.952380308
Short name T658
Test name
Test status
Simulation time 5996733902 ps
CPU time 15.76 seconds
Started Aug 04 05:04:46 PM PDT 24
Finished Aug 04 05:05:01 PM PDT 24
Peak memory 201340 kb
Host smart-8241a4af-40bd-4011-a83b-fb7e7d73b656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952380308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.952380308
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3289651676
Short name T407
Test name
Test status
Simulation time 187418021739 ps
CPU time 219.33 seconds
Started Aug 04 05:04:58 PM PDT 24
Finished Aug 04 05:08:38 PM PDT 24
Peak memory 201436 kb
Host smart-89d2b244-e22e-4f97-bfc4-52be1dfe63a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289651676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3289651676
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.467806019
Short name T770
Test name
Test status
Simulation time 109531343753 ps
CPU time 140.99 seconds
Started Aug 04 05:04:59 PM PDT 24
Finished Aug 04 05:07:20 PM PDT 24
Peak memory 217736 kb
Host smart-860213d3-394f-4f5b-819c-0d9a4516949d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467806019 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.467806019
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.745315736
Short name T756
Test name
Test status
Simulation time 332614500 ps
CPU time 1.35 seconds
Started Aug 04 05:05:08 PM PDT 24
Finished Aug 04 05:05:09 PM PDT 24
Peak memory 201132 kb
Host smart-294dabb6-4673-4af6-851a-aeade8bf347f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745315736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.745315736
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2962362362
Short name T10
Test name
Test status
Simulation time 363721429013 ps
CPU time 56.92 seconds
Started Aug 04 05:05:05 PM PDT 24
Finished Aug 04 05:06:02 PM PDT 24
Peak memory 201292 kb
Host smart-e9a6b597-8791-4565-bccc-02815a4f19ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962362362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2962362362
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1278929725
Short name T374
Test name
Test status
Simulation time 485711611064 ps
CPU time 1062.77 seconds
Started Aug 04 05:04:59 PM PDT 24
Finished Aug 04 05:22:42 PM PDT 24
Peak memory 201376 kb
Host smart-500e76ae-0f54-43b9-9213-b69ace3873a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278929725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1278929725
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1928704681
Short name T796
Test name
Test status
Simulation time 484495611199 ps
CPU time 1080.44 seconds
Started Aug 04 05:05:00 PM PDT 24
Finished Aug 04 05:23:01 PM PDT 24
Peak memory 201400 kb
Host smart-1484a34b-3d8f-4d7d-a786-dbe3cfeef736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928704681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1928704681
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3546959274
Short name T570
Test name
Test status
Simulation time 489933678250 ps
CPU time 770.45 seconds
Started Aug 04 05:05:00 PM PDT 24
Finished Aug 04 05:17:51 PM PDT 24
Peak memory 201372 kb
Host smart-dad725ef-8913-48d4-a062-535e03225fef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546959274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3546959274
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1144946322
Short name T235
Test name
Test status
Simulation time 182647909083 ps
CPU time 98.29 seconds
Started Aug 04 05:04:59 PM PDT 24
Finished Aug 04 05:06:37 PM PDT 24
Peak memory 201384 kb
Host smart-736b168c-b440-43c9-adae-e04c82fb2202
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144946322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1144946322
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1571859202
Short name T795
Test name
Test status
Simulation time 392139193798 ps
CPU time 957.19 seconds
Started Aug 04 05:04:59 PM PDT 24
Finished Aug 04 05:20:56 PM PDT 24
Peak memory 201360 kb
Host smart-5c89feb4-da9c-42cb-8311-79bf587aaa95
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571859202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1571859202
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.283636099
Short name T181
Test name
Test status
Simulation time 103858803886 ps
CPU time 363.45 seconds
Started Aug 04 05:05:04 PM PDT 24
Finished Aug 04 05:11:08 PM PDT 24
Peak memory 201812 kb
Host smart-240f1936-ee9f-4038-ba99-25171baf013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283636099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.283636099
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.488590787
Short name T791
Test name
Test status
Simulation time 45574193280 ps
CPU time 115.22 seconds
Started Aug 04 05:05:05 PM PDT 24
Finished Aug 04 05:07:00 PM PDT 24
Peak memory 201296 kb
Host smart-15e7fdce-127e-491e-b885-3aac8398c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488590787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.488590787
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3488670350
Short name T709
Test name
Test status
Simulation time 4570474732 ps
CPU time 2.26 seconds
Started Aug 04 05:05:05 PM PDT 24
Finished Aug 04 05:05:07 PM PDT 24
Peak memory 201304 kb
Host smart-d3c35048-456d-44a7-a057-75c203de0d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488670350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3488670350
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3454844450
Short name T513
Test name
Test status
Simulation time 5709737128 ps
CPU time 14.59 seconds
Started Aug 04 05:04:59 PM PDT 24
Finished Aug 04 05:05:14 PM PDT 24
Peak memory 201320 kb
Host smart-f3f973f3-5200-4814-8bff-aa697f64166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454844450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3454844450
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.433385077
Short name T628
Test name
Test status
Simulation time 328175585162 ps
CPU time 799.09 seconds
Started Aug 04 05:05:05 PM PDT 24
Finished Aug 04 05:18:24 PM PDT 24
Peak memory 201344 kb
Host smart-9df38aae-2ea9-442d-bfc6-a7478d913a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433385077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
433385077
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.484481255
Short name T54
Test name
Test status
Simulation time 121310635818 ps
CPU time 171.71 seconds
Started Aug 04 05:05:04 PM PDT 24
Finished Aug 04 05:07:55 PM PDT 24
Peak memory 216488 kb
Host smart-eaed51f5-fa62-4a1e-a559-50e91be13f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484481255 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.484481255
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.21837315
Short name T563
Test name
Test status
Simulation time 298807329 ps
CPU time 1.3 seconds
Started Aug 04 05:05:19 PM PDT 24
Finished Aug 04 05:05:21 PM PDT 24
Peak memory 201156 kb
Host smart-13cdac2e-1041-4db7-b1c4-cb0908fa4d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.21837315
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1158926564
Short name T316
Test name
Test status
Simulation time 188719615263 ps
CPU time 448.26 seconds
Started Aug 04 05:05:12 PM PDT 24
Finished Aug 04 05:12:40 PM PDT 24
Peak memory 201308 kb
Host smart-326d3abe-67b9-4750-b812-3b8580c1693a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158926564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1158926564
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2341710381
Short name T301
Test name
Test status
Simulation time 156787830305 ps
CPU time 335.5 seconds
Started Aug 04 05:05:13 PM PDT 24
Finished Aug 04 05:10:49 PM PDT 24
Peak memory 201316 kb
Host smart-f3606d72-d03f-46b9-96d8-e49bd748cbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341710381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2341710381
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2775232112
Short name T206
Test name
Test status
Simulation time 157604969233 ps
CPU time 384.26 seconds
Started Aug 04 05:05:13 PM PDT 24
Finished Aug 04 05:11:38 PM PDT 24
Peak memory 201368 kb
Host smart-f8fdefd9-4cf4-4798-9776-006917d1ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775232112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2775232112
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2951339412
Short name T740
Test name
Test status
Simulation time 489213916357 ps
CPU time 537.49 seconds
Started Aug 04 05:05:11 PM PDT 24
Finished Aug 04 05:14:08 PM PDT 24
Peak memory 201360 kb
Host smart-8d4b94f1-bc0c-416b-bae8-682257040e81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951339412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2951339412
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.968335375
Short name T132
Test name
Test status
Simulation time 162207403053 ps
CPU time 345.98 seconds
Started Aug 04 05:05:13 PM PDT 24
Finished Aug 04 05:10:59 PM PDT 24
Peak memory 201328 kb
Host smart-831d216a-2c01-4b71-8ca0-1c6f0c89253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968335375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.968335375
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3120216677
Short name T529
Test name
Test status
Simulation time 159710959856 ps
CPU time 384.13 seconds
Started Aug 04 05:05:11 PM PDT 24
Finished Aug 04 05:11:36 PM PDT 24
Peak memory 201384 kb
Host smart-585984da-b9ba-466e-bf51-19673e80289c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120216677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3120216677
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2035203961
Short name T47
Test name
Test status
Simulation time 345987271746 ps
CPU time 184.23 seconds
Started Aug 04 05:05:12 PM PDT 24
Finished Aug 04 05:08:16 PM PDT 24
Peak memory 201328 kb
Host smart-74af1ebc-b980-42b7-9392-57b25f4cf03c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035203961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2035203961
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2358816837
Short name T531
Test name
Test status
Simulation time 205460661768 ps
CPU time 465.76 seconds
Started Aug 04 05:05:14 PM PDT 24
Finished Aug 04 05:13:00 PM PDT 24
Peak memory 201332 kb
Host smart-186060fa-96dd-4402-b7fe-e1dc0c7a2858
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358816837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2358816837
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4161807240
Short name T677
Test name
Test status
Simulation time 83250522204 ps
CPU time 285.79 seconds
Started Aug 04 05:05:16 PM PDT 24
Finished Aug 04 05:10:02 PM PDT 24
Peak memory 201704 kb
Host smart-1a1a11a5-10f1-4fb5-86fc-7df793260a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161807240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4161807240
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3246583129
Short name T371
Test name
Test status
Simulation time 38243140347 ps
CPU time 23.66 seconds
Started Aug 04 05:05:16 PM PDT 24
Finished Aug 04 05:05:40 PM PDT 24
Peak memory 201272 kb
Host smart-ed9038f5-4886-4773-80a5-215c6789a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246583129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3246583129
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.995133838
Short name T438
Test name
Test status
Simulation time 3116258538 ps
CPU time 2.29 seconds
Started Aug 04 05:05:19 PM PDT 24
Finished Aug 04 05:05:22 PM PDT 24
Peak memory 201256 kb
Host smart-434dfd1d-0356-4794-afa2-21cdef883976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995133838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.995133838
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3371933034
Short name T108
Test name
Test status
Simulation time 5918407687 ps
CPU time 7.25 seconds
Started Aug 04 05:05:08 PM PDT 24
Finished Aug 04 05:05:16 PM PDT 24
Peak memory 201236 kb
Host smart-c5c8c78c-a484-43fb-a3f7-f9bd9dfc8403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371933034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3371933034
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2100972895
Short name T277
Test name
Test status
Simulation time 492110130029 ps
CPU time 1056.09 seconds
Started Aug 04 05:05:16 PM PDT 24
Finished Aug 04 05:22:52 PM PDT 24
Peak memory 201408 kb
Host smart-74087052-7dc2-42f1-bfaf-8b8134de2f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100972895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2100972895
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2773956706
Short name T290
Test name
Test status
Simulation time 69336091708 ps
CPU time 102.47 seconds
Started Aug 04 05:05:19 PM PDT 24
Finished Aug 04 05:07:02 PM PDT 24
Peak memory 210068 kb
Host smart-fa4b3904-569d-401c-a003-82524f62aa22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773956706 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2773956706
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4023688054
Short name T89
Test name
Test status
Simulation time 491338234 ps
CPU time 0.85 seconds
Started Aug 04 04:58:04 PM PDT 24
Finished Aug 04 04:58:05 PM PDT 24
Peak memory 201176 kb
Host smart-157ec954-71e3-4908-97e5-eca3ffece52e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023688054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4023688054
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1468232071
Short name T246
Test name
Test status
Simulation time 515539499214 ps
CPU time 411.3 seconds
Started Aug 04 04:58:05 PM PDT 24
Finished Aug 04 05:04:57 PM PDT 24
Peak memory 201432 kb
Host smart-85c2463e-743b-4009-a548-4958d0acf5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468232071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1468232071
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3516545002
Short name T682
Test name
Test status
Simulation time 163834932486 ps
CPU time 374.29 seconds
Started Aug 04 04:58:04 PM PDT 24
Finished Aug 04 05:04:18 PM PDT 24
Peak memory 201416 kb
Host smart-e3e7fb98-187e-4fbf-90a6-8723517d2dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516545002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3516545002
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1554341757
Short name T663
Test name
Test status
Simulation time 322516141198 ps
CPU time 201.54 seconds
Started Aug 04 04:58:01 PM PDT 24
Finished Aug 04 05:01:22 PM PDT 24
Peak memory 201368 kb
Host smart-be414e13-ad2e-415e-b265-19d2f0fdc1fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554341757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1554341757
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.876889077
Short name T130
Test name
Test status
Simulation time 328003721157 ps
CPU time 386.22 seconds
Started Aug 04 04:58:01 PM PDT 24
Finished Aug 04 05:04:27 PM PDT 24
Peak memory 201404 kb
Host smart-f5231814-e473-4eb3-b73a-dff56e1a5360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876889077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.876889077
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2574108833
Short name T731
Test name
Test status
Simulation time 318919973772 ps
CPU time 614.62 seconds
Started Aug 04 04:58:00 PM PDT 24
Finished Aug 04 05:08:15 PM PDT 24
Peak memory 201308 kb
Host smart-e7c2a3e7-8555-4d0c-af56-3ce681349dd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574108833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2574108833
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2554267587
Short name T174
Test name
Test status
Simulation time 564267119013 ps
CPU time 284.3 seconds
Started Aug 04 04:58:02 PM PDT 24
Finished Aug 04 05:02:47 PM PDT 24
Peak memory 201356 kb
Host smart-0fb4ff4e-107c-41fd-85eb-ca3a9f24dee8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554267587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2554267587
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.127609152
Short name T367
Test name
Test status
Simulation time 198465934154 ps
CPU time 101.32 seconds
Started Aug 04 04:58:00 PM PDT 24
Finished Aug 04 04:59:41 PM PDT 24
Peak memory 201400 kb
Host smart-d0e95f23-2595-45e3-afae-72b614ed22c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127609152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.127609152
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.559546895
Short name T182
Test name
Test status
Simulation time 116284705495 ps
CPU time 372.44 seconds
Started Aug 04 04:58:05 PM PDT 24
Finished Aug 04 05:04:17 PM PDT 24
Peak memory 201804 kb
Host smart-f0a28102-8998-4028-b11d-ba0da7bec720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559546895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.559546895
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2455452381
Short name T23
Test name
Test status
Simulation time 35667902141 ps
CPU time 78.73 seconds
Started Aug 04 04:58:05 PM PDT 24
Finished Aug 04 04:59:24 PM PDT 24
Peak memory 201228 kb
Host smart-fae4bf39-d2df-41e7-9053-0bf51dcdf943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455452381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2455452381
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1176826995
Short name T461
Test name
Test status
Simulation time 3146057734 ps
CPU time 4.39 seconds
Started Aug 04 04:58:03 PM PDT 24
Finished Aug 04 04:58:08 PM PDT 24
Peak memory 201316 kb
Host smart-a7deecc7-55f3-4a7f-b512-121c5ad46edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176826995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1176826995
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.4288592738
Short name T678
Test name
Test status
Simulation time 5681042143 ps
CPU time 14.21 seconds
Started Aug 04 04:58:07 PM PDT 24
Finished Aug 04 04:58:21 PM PDT 24
Peak memory 201276 kb
Host smart-bc859986-1174-4b69-b63b-8e53dc4ff590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288592738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4288592738
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.251598536
Short name T324
Test name
Test status
Simulation time 530991908778 ps
CPU time 1167.72 seconds
Started Aug 04 04:58:06 PM PDT 24
Finished Aug 04 05:17:34 PM PDT 24
Peak memory 201416 kb
Host smart-797b32ba-6106-49a6-8634-5962c07c80dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251598536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.251598536
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2940078313
Short name T32
Test name
Test status
Simulation time 101799695986 ps
CPU time 61.68 seconds
Started Aug 04 04:58:04 PM PDT 24
Finished Aug 04 04:59:06 PM PDT 24
Peak memory 209712 kb
Host smart-ffdc8c25-4274-4ff2-ad70-cd39138daff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940078313 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2940078313
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1158248286
Short name T464
Test name
Test status
Simulation time 525723217 ps
CPU time 1.78 seconds
Started Aug 04 04:58:09 PM PDT 24
Finished Aug 04 04:58:11 PM PDT 24
Peak memory 201144 kb
Host smart-7da1fcca-1961-4538-9236-9acdc3e121ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158248286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1158248286
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2829069450
Short name T289
Test name
Test status
Simulation time 165937394411 ps
CPU time 396.48 seconds
Started Aug 04 04:58:03 PM PDT 24
Finished Aug 04 05:04:40 PM PDT 24
Peak memory 201444 kb
Host smart-2e28c4f5-9cfe-4db6-b77f-4dc43c665b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829069450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2829069450
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3060077179
Short name T431
Test name
Test status
Simulation time 165947135467 ps
CPU time 356.16 seconds
Started Aug 04 04:58:08 PM PDT 24
Finished Aug 04 05:04:04 PM PDT 24
Peak memory 201380 kb
Host smart-8ac7e9bb-5e03-4c0f-b1ab-8e1b4b2f46e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060077179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3060077179
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.4128097374
Short name T664
Test name
Test status
Simulation time 167476800543 ps
CPU time 90.34 seconds
Started Aug 04 04:58:05 PM PDT 24
Finished Aug 04 04:59:36 PM PDT 24
Peak memory 201392 kb
Host smart-17b25843-71fa-4d56-8fa8-19356ecdf3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128097374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.4128097374
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3116764881
Short name T620
Test name
Test status
Simulation time 335284641445 ps
CPU time 187.24 seconds
Started Aug 04 04:58:06 PM PDT 24
Finished Aug 04 05:01:13 PM PDT 24
Peak memory 201376 kb
Host smart-6066ef0a-de22-4168-a7da-a22b14e6ccdc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116764881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3116764881
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3714499863
Short name T576
Test name
Test status
Simulation time 178201001056 ps
CPU time 105.24 seconds
Started Aug 04 04:58:07 PM PDT 24
Finished Aug 04 04:59:53 PM PDT 24
Peak memory 201336 kb
Host smart-b8a572c8-c249-4d18-a754-1dfba37db2af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714499863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3714499863
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2565270804
Short name T598
Test name
Test status
Simulation time 207447505146 ps
CPU time 132.88 seconds
Started Aug 04 04:58:08 PM PDT 24
Finished Aug 04 05:00:21 PM PDT 24
Peak memory 201144 kb
Host smart-78b562e2-dbd8-4e8c-8d8f-20785f7a93aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565270804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2565270804
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3567576295
Short name T655
Test name
Test status
Simulation time 117798317996 ps
CPU time 630.26 seconds
Started Aug 04 04:58:08 PM PDT 24
Finished Aug 04 05:08:38 PM PDT 24
Peak memory 201808 kb
Host smart-ba920308-ee4d-4a26-a8b2-2cbb04e25197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567576295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3567576295
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1198243018
Short name T437
Test name
Test status
Simulation time 24868497072 ps
CPU time 55.54 seconds
Started Aug 04 04:58:07 PM PDT 24
Finished Aug 04 04:59:03 PM PDT 24
Peak memory 201288 kb
Host smart-939a531a-cec7-4318-ba5c-d431796868e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198243018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1198243018
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2145884906
Short name T406
Test name
Test status
Simulation time 3321366530 ps
CPU time 1.55 seconds
Started Aug 04 04:58:08 PM PDT 24
Finished Aug 04 04:58:09 PM PDT 24
Peak memory 201188 kb
Host smart-21dff86b-49ef-4f6b-a965-5ba56e0cb085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145884906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2145884906
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1748741595
Short name T485
Test name
Test status
Simulation time 5836418100 ps
CPU time 5.03 seconds
Started Aug 04 04:58:08 PM PDT 24
Finished Aug 04 04:58:13 PM PDT 24
Peak memory 201288 kb
Host smart-002b4f2e-3d4c-4072-bc94-a1e36589945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748741595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1748741595
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.314124217
Short name T496
Test name
Test status
Simulation time 175696503938 ps
CPU time 107.48 seconds
Started Aug 04 04:58:08 PM PDT 24
Finished Aug 04 04:59:56 PM PDT 24
Peak memory 201144 kb
Host smart-16fc8d4c-bfc9-4d06-956d-5f28072e9de2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314124217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.314124217
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3158066677
Short name T746
Test name
Test status
Simulation time 416237367 ps
CPU time 0.89 seconds
Started Aug 04 04:58:23 PM PDT 24
Finished Aug 04 04:58:24 PM PDT 24
Peak memory 201200 kb
Host smart-e8cc7b63-86bb-46f7-a3e9-bcfdef12378a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158066677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3158066677
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.4228090705
Short name T11
Test name
Test status
Simulation time 325293920830 ps
CPU time 700.15 seconds
Started Aug 04 04:58:10 PM PDT 24
Finished Aug 04 05:09:50 PM PDT 24
Peak memory 201352 kb
Host smart-59f3bbbb-1058-4a78-9044-8f2a2cd039ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228090705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.4228090705
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2837683091
Short name T556
Test name
Test status
Simulation time 324431429947 ps
CPU time 393.85 seconds
Started Aug 04 04:58:11 PM PDT 24
Finished Aug 04 05:04:45 PM PDT 24
Peak memory 201404 kb
Host smart-5f1e4be8-e39a-4605-ac41-00ecede69977
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837683091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2837683091
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.906064440
Short name T255
Test name
Test status
Simulation time 163171325630 ps
CPU time 360.23 seconds
Started Aug 04 04:58:12 PM PDT 24
Finished Aug 04 05:04:12 PM PDT 24
Peak memory 201324 kb
Host smart-644ad53f-544e-4d3c-bcd7-450b39f896d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906064440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.906064440
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.4139845211
Short name T85
Test name
Test status
Simulation time 169645555827 ps
CPU time 40.74 seconds
Started Aug 04 04:58:14 PM PDT 24
Finished Aug 04 04:58:55 PM PDT 24
Peak memory 201364 kb
Host smart-c65f2480-9996-473b-ae34-f4416d138c25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139845211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.4139845211
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2065365594
Short name T43
Test name
Test status
Simulation time 206239160449 ps
CPU time 421.59 seconds
Started Aug 04 04:58:10 PM PDT 24
Finished Aug 04 05:05:11 PM PDT 24
Peak memory 201292 kb
Host smart-1c4cf1f2-832f-45a9-bf1e-54adda76dc08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065365594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2065365594
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1762701936
Short name T341
Test name
Test status
Simulation time 410251727778 ps
CPU time 74.33 seconds
Started Aug 04 04:58:17 PM PDT 24
Finished Aug 04 04:59:32 PM PDT 24
Peak memory 201352 kb
Host smart-08e49a6b-4c75-4114-a9c1-94670713bdc3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762701936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1762701936
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3423628508
Short name T591
Test name
Test status
Simulation time 102422401689 ps
CPU time 526.92 seconds
Started Aug 04 04:58:13 PM PDT 24
Finished Aug 04 05:07:00 PM PDT 24
Peak memory 201744 kb
Host smart-4d8ef165-b597-475e-9855-e7120c5b7971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423628508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3423628508
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3803455324
Short name T460
Test name
Test status
Simulation time 41886393726 ps
CPU time 94.45 seconds
Started Aug 04 04:58:10 PM PDT 24
Finished Aug 04 04:59:45 PM PDT 24
Peak memory 201284 kb
Host smart-f0ed0407-72ff-4cfc-9285-03f0c5eab7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803455324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3803455324
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1381797925
Short name T794
Test name
Test status
Simulation time 4782682082 ps
CPU time 3.57 seconds
Started Aug 04 04:58:13 PM PDT 24
Finished Aug 04 04:58:17 PM PDT 24
Peak memory 201284 kb
Host smart-334f8a51-4067-4606-8d83-ea8f9fb23b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381797925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1381797925
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.204019000
Short name T525
Test name
Test status
Simulation time 5838714553 ps
CPU time 3.94 seconds
Started Aug 04 04:58:11 PM PDT 24
Finished Aug 04 04:58:15 PM PDT 24
Peak memory 201228 kb
Host smart-c711a848-6ed3-4e60-8d93-599d7b7e16d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204019000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.204019000
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.4020060684
Short name T504
Test name
Test status
Simulation time 484603089900 ps
CPU time 1487.06 seconds
Started Aug 04 04:58:18 PM PDT 24
Finished Aug 04 05:23:06 PM PDT 24
Peak memory 201860 kb
Host smart-e3eb982a-fe7d-46dd-ba07-a13c4c73a5a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020060684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
4020060684
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.593087889
Short name T264
Test name
Test status
Simulation time 28094245044 ps
CPU time 83.04 seconds
Started Aug 04 04:58:18 PM PDT 24
Finished Aug 04 04:59:41 PM PDT 24
Peak memory 210064 kb
Host smart-ba7a14fd-2a8b-4283-b9f7-773e80b39c5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593087889 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.593087889
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1861840496
Short name T683
Test name
Test status
Simulation time 524605113 ps
CPU time 1.49 seconds
Started Aug 04 04:58:23 PM PDT 24
Finished Aug 04 04:58:25 PM PDT 24
Peak memory 201200 kb
Host smart-504c3066-bb28-4840-8aa5-ebb9185f2d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861840496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1861840496
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.753765320
Short name T642
Test name
Test status
Simulation time 495250863299 ps
CPU time 500.26 seconds
Started Aug 04 04:58:18 PM PDT 24
Finished Aug 04 05:06:39 PM PDT 24
Peak memory 201364 kb
Host smart-d123f3d8-1c36-42c8-96d8-a16a24d92753
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753765320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.753765320
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.32846979
Short name T720
Test name
Test status
Simulation time 559026512104 ps
CPU time 1373.65 seconds
Started Aug 04 04:58:17 PM PDT 24
Finished Aug 04 05:21:11 PM PDT 24
Peak memory 201392 kb
Host smart-d440dba8-9192-490a-8bc7-71406256ef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32846979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.32846979
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1555989904
Short name T638
Test name
Test status
Simulation time 163066426520 ps
CPU time 88 seconds
Started Aug 04 04:58:17 PM PDT 24
Finished Aug 04 04:59:45 PM PDT 24
Peak memory 201420 kb
Host smart-f058ed69-f0c0-4c8a-ad09-4a6212dc46ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555989904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1555989904
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.455542872
Short name T595
Test name
Test status
Simulation time 487140363595 ps
CPU time 205.48 seconds
Started Aug 04 04:58:17 PM PDT 24
Finished Aug 04 05:01:43 PM PDT 24
Peak memory 201352 kb
Host smart-31a089de-dcd9-4a69-b8a6-46cbdaaf74ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=455542872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.455542872
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.4038913497
Short name T165
Test name
Test status
Simulation time 495999780357 ps
CPU time 586.98 seconds
Started Aug 04 04:58:15 PM PDT 24
Finished Aug 04 05:08:02 PM PDT 24
Peak memory 201384 kb
Host smart-a327fe18-486b-49e1-a14d-c730832b79f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038913497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.4038913497
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.139052475
Short name T349
Test name
Test status
Simulation time 495946155037 ps
CPU time 1066.6 seconds
Started Aug 04 04:58:18 PM PDT 24
Finished Aug 04 05:16:05 PM PDT 24
Peak memory 201400 kb
Host smart-768e973c-02f1-4daa-86e5-0ae37502895c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=139052475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.139052475
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1841521141
Short name T564
Test name
Test status
Simulation time 529708912934 ps
CPU time 555.38 seconds
Started Aug 04 04:58:20 PM PDT 24
Finished Aug 04 05:07:35 PM PDT 24
Peak memory 201412 kb
Host smart-14b9c97c-8738-4684-a638-059628d2b839
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841521141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1841521141
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.760154222
Short name T399
Test name
Test status
Simulation time 601348009306 ps
CPU time 1267.25 seconds
Started Aug 04 04:58:19 PM PDT 24
Finished Aug 04 05:19:26 PM PDT 24
Peak memory 201348 kb
Host smart-4de09e53-759e-4b85-a152-f13593369e94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760154222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.760154222
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3662710844
Short name T749
Test name
Test status
Simulation time 123345537651 ps
CPU time 404.22 seconds
Started Aug 04 04:58:19 PM PDT 24
Finished Aug 04 05:05:03 PM PDT 24
Peak memory 201768 kb
Host smart-583c9113-16b8-47c7-8987-e1faca93f330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662710844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3662710844
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3250447680
Short name T587
Test name
Test status
Simulation time 31314769425 ps
CPU time 35.83 seconds
Started Aug 04 04:58:21 PM PDT 24
Finished Aug 04 04:58:57 PM PDT 24
Peak memory 201212 kb
Host smart-70ae6cac-4dbd-423e-ac0c-1dff5ce2eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250447680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3250447680
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.854536379
Short name T616
Test name
Test status
Simulation time 3301251084 ps
CPU time 1.71 seconds
Started Aug 04 04:58:17 PM PDT 24
Finished Aug 04 04:58:19 PM PDT 24
Peak memory 201264 kb
Host smart-65dc13d7-2fce-4486-a03c-80cc225a9047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854536379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.854536379
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.26826115
Short name T376
Test name
Test status
Simulation time 5869085990 ps
CPU time 3.16 seconds
Started Aug 04 04:58:21 PM PDT 24
Finished Aug 04 04:58:24 PM PDT 24
Peak memory 201232 kb
Host smart-40b28ae3-65c5-404c-b40d-0630bd3492c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26826115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.26826115
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3101911873
Short name T424
Test name
Test status
Simulation time 489042961 ps
CPU time 1.64 seconds
Started Aug 04 04:58:25 PM PDT 24
Finished Aug 04 04:58:27 PM PDT 24
Peak memory 201152 kb
Host smart-aa39f60d-977c-4da9-94bd-19807192d514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101911873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3101911873
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3989078281
Short name T541
Test name
Test status
Simulation time 527769555771 ps
CPU time 887.77 seconds
Started Aug 04 04:58:25 PM PDT 24
Finished Aug 04 05:13:13 PM PDT 24
Peak memory 201432 kb
Host smart-ccf23559-0dbf-41b9-a920-ed014df512f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989078281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3989078281
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3570111816
Short name T312
Test name
Test status
Simulation time 570226503352 ps
CPU time 651.94 seconds
Started Aug 04 04:58:23 PM PDT 24
Finished Aug 04 05:09:15 PM PDT 24
Peak memory 201424 kb
Host smart-f573d6c2-9b8f-43e9-9af6-f2e660a90167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570111816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3570111816
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2019637087
Short name T387
Test name
Test status
Simulation time 323883771585 ps
CPU time 375.81 seconds
Started Aug 04 04:58:20 PM PDT 24
Finished Aug 04 05:04:36 PM PDT 24
Peak memory 201320 kb
Host smart-31ac2b44-08f7-45ac-9565-7ae89bf138ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019637087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2019637087
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.440972798
Short name T171
Test name
Test status
Simulation time 324039925478 ps
CPU time 174.45 seconds
Started Aug 04 04:58:21 PM PDT 24
Finished Aug 04 05:01:15 PM PDT 24
Peak memory 201324 kb
Host smart-d992edd0-e740-4174-9339-1d82aef30ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440972798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.440972798
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.802909451
Short name T524
Test name
Test status
Simulation time 499023291081 ps
CPU time 300.87 seconds
Started Aug 04 04:58:20 PM PDT 24
Finished Aug 04 05:03:21 PM PDT 24
Peak memory 201380 kb
Host smart-75423349-d491-4d13-8ded-1c9e3e995609
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=802909451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.802909451
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1428724092
Short name T199
Test name
Test status
Simulation time 394243811697 ps
CPU time 469.43 seconds
Started Aug 04 04:58:21 PM PDT 24
Finished Aug 04 05:06:11 PM PDT 24
Peak memory 201372 kb
Host smart-1e216fd7-dbc2-4a7e-87d7-d8994bb65219
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428724092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1428724092
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2055048973
Short name T462
Test name
Test status
Simulation time 414835005927 ps
CPU time 514.07 seconds
Started Aug 04 04:58:23 PM PDT 24
Finished Aug 04 05:06:57 PM PDT 24
Peak memory 201280 kb
Host smart-458e12e3-39c4-4ff4-9c6d-1485c25ad07d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055048973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2055048973
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3065133123
Short name T742
Test name
Test status
Simulation time 88206267748 ps
CPU time 417.61 seconds
Started Aug 04 04:58:23 PM PDT 24
Finished Aug 04 05:05:21 PM PDT 24
Peak memory 201736 kb
Host smart-38c8fc0c-6345-405d-be4d-a254e065e840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065133123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3065133123
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.895771698
Short name T344
Test name
Test status
Simulation time 33949508973 ps
CPU time 17.51 seconds
Started Aug 04 04:58:25 PM PDT 24
Finished Aug 04 04:58:43 PM PDT 24
Peak memory 201208 kb
Host smart-049747bf-966d-4ba2-94bf-ed8961100ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895771698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.895771698
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2759591862
Short name T483
Test name
Test status
Simulation time 4793263839 ps
CPU time 9.84 seconds
Started Aug 04 04:58:24 PM PDT 24
Finished Aug 04 04:58:34 PM PDT 24
Peak memory 201256 kb
Host smart-d554753b-9e56-4c26-a6cb-5fa0f95e9d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759591862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2759591862
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1596096703
Short name T428
Test name
Test status
Simulation time 5746959297 ps
CPU time 2.14 seconds
Started Aug 04 04:58:20 PM PDT 24
Finished Aug 04 04:58:22 PM PDT 24
Peak memory 201320 kb
Host smart-04b9b8f3-00b0-4e7c-ac2c-e1e1ccec6e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596096703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1596096703
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1262145121
Short name T793
Test name
Test status
Simulation time 517967432026 ps
CPU time 306.4 seconds
Started Aug 04 04:58:26 PM PDT 24
Finished Aug 04 05:03:32 PM PDT 24
Peak memory 201328 kb
Host smart-abfd1804-9dc0-4813-9695-a48fe1ee847f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262145121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1262145121
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1444184208
Short name T738
Test name
Test status
Simulation time 24226880198 ps
CPU time 62.19 seconds
Started Aug 04 04:58:24 PM PDT 24
Finished Aug 04 04:59:27 PM PDT 24
Peak memory 210084 kb
Host smart-c9a5abc8-a807-44f1-b255-775756d73478
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444184208 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1444184208
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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