Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6881	1			T6	20		T7	47		T11	50
testmodes[AdcCtrlTestmodeNormal]	5099	1			T2	2		T7	53		T11	29
testmodes[AdcCtrlTestmodeLowpower]	5389	1			T1	1		T3	3		T4	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3926	1			T6	19		T7	14		T11	33
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1609	1			T7	14		T11	13		T26	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1238	1			T7	18		T11	4		T29	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1608	1			T7	15		T11	13		T26	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1901	1			T2	1		T7	21		T11	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1242	1			T7	17		T11	1		T60	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1225	1			T7	17		T11	4		T29	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1257	1			T7	18		T60	1		T202	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2664	1			T3	2		T7	19		T8	15