Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21606

1

T1

10

T3

37

T4

24

auto[ADC_CTRL_FILTER_COND_OUT]

3648

1

T2

10

T11

20

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19518

1

T2

10

T3

37

T6

20

auto[1]

5736

1

T1

10

T4

24

T5

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	40	1			T222	30		T223	10		-	-
values[0]	40	1			T135	1		T224	19		T225	16
values[1]	540	1			T3	37		T4	24		T128	3
values[2]	559	1			T149	3		T153	25		T154	1
values[3]	702	1			T128	5		T127	31		T60	2
values[4]	583	1			T13	1		T14	1		T60	2
values[5]	2962	1			T1	10		T10	14		T12	3
values[6]	829	1			T11	20		T47	1		T125	17
values[7]	642	1			T11	8		T31	10		T135	1
values[8]	740	1			T2	1		T5	5		T13	1
values[9]	1195	1			T2	9		T11	12		T127	8
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	765	1			T3	37		T4	24		T128	3
values[1]	564	1			T60	2		T149	3		T172	1
values[2]	718	1			T128	5		T127	31		T39	1
values[3]	2633	1			T1	10		T10	14		T12	3
values[4]	974	1			T14	1		T30	28		T125	21
values[5]	643	1			T11	20		T47	1		T129	22
values[6]	662	1			T11	8		T31	10		T226	11
values[7]	818	1			T2	10		T5	5		T13	1
values[8]	741	1			T11	12		T127	8		T60	31
values[9]	312	1			T79	3		T227	9		T228	3
minimum	16424	1			T6	20		T7	154		T8	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	37		T4	13		T128	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T47	8		T135	2		T153	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T60	1		T149	1		T159	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T172	1		T229	9		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T175	9		T162	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T128	1		T127	17		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T1	10		T10	14		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T60	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T14	1		T92	16		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T30	12		T125	9		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	1		T202	4		T231	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	13		T129	14		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	4		T226	1		T37	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T31	1		T172	1		T160	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	5		T136	4		T131	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	2		T13	1		T29	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	7		T172	1		T133	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T127	4		T60	15		T133	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T227	9		T228	3		T176	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T79	1		T232	1		T233	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16273	1			T6	20		T7	154		T8	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	11		T128	2		T129	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T153	5		T132	10		T41	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T60	1		T149	2		T42	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T229	11		T230	1		T219	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T207	6		T234	12		T176	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T128	4		T127	14		T142	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T150	23		T151	11		T226	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T60	1		T180	5		T235	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T236	14		T44	6		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T30	16		T125	12		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T202	10		T38	3		T142	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	7		T129	8		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	4		T226	10		T37	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T31	9		T160	11		T42	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T136	6		T131	9		T132	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	8		T29	13		T235	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	5		T133	9		T175	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T127	4		T60	16		T133	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T176	4		T237	14		T238	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T79	2		T233	13		T239	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T223	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T222	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T135	1		T224	12		T225	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	37		T4	13		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	8		T135	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T149	1		T154	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T153	20		T172	1		T41	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T60	1		T159	2		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T128	1		T127	17		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	1		T137	1		T175	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T60	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T1	10		T10	14		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T30	12		T125	1		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T47	1		T231	17		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	13		T125	8		T129	31
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	4		T202	4		T136	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	1		T135	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	5		T226	1		T131	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T13	1		T29	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T11	7		T172	1		T133	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T2	1		T127	4		T60	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T223	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T222	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T224	7		T225	6		T240	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T4	11		T128	2		T129	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T132	10		T241	12		T237	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T149	2		T132	9		T42	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T153	5		T41	2		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T60	1		T234	12		T126	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T128	4		T127	14		T142	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T207	6		T176	8		T242	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T60	1		T235	9		T33	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T150	23		T151	11		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T30	16		T125	3		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T38	3		T142	1		T45	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	7		T125	9		T129	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	4		T202	10		T136	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T31	9		T160	11		T42	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T226	10		T131	9		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T29	13		T207	8		T238	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	5		T133	9		T175	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	8		T127	4		T60	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	3		T4	12		T128	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T47	1		T135	2		T153	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T60	2		T149	3		T159	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T172	1		T229	12		T230	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T175	1		T162	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T128	5		T127	15		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T1	1		T10	1		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T60	2		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	1		T92	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T30	17		T125	14		T151	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T47	1		T202	11		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	10		T129	9		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	5		T226	11		T37	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T31	10		T172	1		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	1		T136	7		T131	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	10		T13	1		T29	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	8		T172	1		T133	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T127	5		T60	17		T133	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T227	1		T228	1		T176	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T79	3		T232	1		T233	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16424	1			T6	20		T7	154		T8	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	34		T4	12		T129	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T47	7		T153	19		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T42	2		T230	3		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T229	8		T219	3		T243	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T175	8		T234	11		T176	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T127	16		T142	18		T244	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T1	9		T10	13		T27	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T245	2		T228	3		T235	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T92	15		T227	2		T236	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T30	11		T125	7		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T202	3		T231	16		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	10		T129	13		T131	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	3		T37	8		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T160	12		T42	2		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	4		T136	3		T131	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	17		T138	9		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	4		T133	8		T175	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T127	3		T60	14		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T227	8		T228	2		T176	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T233	12		T239	7		T99	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T223	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T222	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T135	1		T224	8		T225	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T3	3		T4	12		T128	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T47	1		T135	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T149	3		T154	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T153	6		T172	1		T41	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T60	2		T159	2		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T128	5		T127	15		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	1		T137	1		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T60	2		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T1	1		T10	1		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T30	17		T125	4		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T47	1		T231	1		T38	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	10		T125	10		T129	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	5		T202	11		T136	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T31	10		T135	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	1		T226	11		T131	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	1		T13	1		T29	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T11	8		T172	1		T133	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T2	9		T127	5		T60	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T223	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T222	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T224	11		T225	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T3	34		T4	12		T129	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T47	7		T241	13		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T42	2		T143	8		T46	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T153	19		T41	1		T229	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T234	11		T126	8		T93	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	16		T142	18		T244	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T175	8		T176	10		T247	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T245	2		T228	3		T235	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T1	9		T10	13		T27	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	11		T151	11		T48	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T231	16		T38	2		T227	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	10		T125	7		T129	29
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	3		T202	3		T136	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T131	13		T160	12		T161	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	4		T131	13		T163	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T29	17		T138	9		T245	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T11	4		T133	8		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T127	3		T60	14		T133	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21705

1

T1

10

T3

14

T6

20

auto[ADC_CTRL_FILTER_COND_OUT]

3549

1

T2

10

T3

23

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19233

1

T2

1

T6

20

T7

154

auto[1]

6021

1

T1

10

T2

9

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T248	1		T249	1		T250	5
values[0]	8	1			T60	2		T140	1		T251	1
values[1]	560	1			T3	24		T14	1		T128	5
values[2]	693	1			T29	13		T47	1		T60	31
values[3]	788	1			T11	12		T60	2		T125	17
values[4]	569	1			T2	10		T226	11		T172	1
values[5]	641	1			T135	1		T48	25		T136	10
values[6]	757	1			T5	5		T13	1		T29	19
values[7]	801	1			T4	24		T127	31		T202	22
values[8]	2690	1			T1	10		T10	14		T11	20
values[9]	1318	1			T3	13		T11	8		T13	1
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	671	1			T3	24		T14	1		T60	2
values[1]	778	1			T29	13		T128	5		T60	31
values[2]	822	1			T11	12		T47	1		T60	2
values[3]	420	1			T2	10		T48	25		T159	1
values[4]	718	1			T13	1		T135	1		T136	10
values[5]	915	1			T4	24		T5	5		T29	19
values[6]	2671	1			T1	10		T10	14		T11	20
values[7]	681	1			T13	1		T127	8		T135	1
values[8]	974	1			T3	13		T11	8		T30	28
values[9]	155	1			T236	21		T44	17		T252	11
minimum	16449	1			T6	20		T7	154		T8	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	14		T60	1		T253	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	10		T14	1		T172	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T29	9		T60	15		T138	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T128	1		T153	20		T227	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T47	1		T60	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	7		T125	8		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	14		T245	3		T175	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T2	2		T159	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T13	1		T135	1		T136	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T254	1		T42	8		T144	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	10		T127	17		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T4	13		T5	5		T151	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T1	10		T10	14		T11	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T31	1		T149	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	1		T127	4		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T125	1		T37	13		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T128	1		T135	1		T202	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T3	13		T11	4		T30	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T44	11		T247	3		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T236	13		T252	1		T256	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16273	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T162	1		T205	1		T257	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T60	1		T175	5		T233	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T132	9		T207	8		T237	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T29	4		T60	16		T144	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T128	4		T153	5		T258	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T60	1		T38	3		T131	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	5		T125	9		T226	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T48	11		T175	4		T259	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T2	8		T180	5		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T136	6		T79	2		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T42	4		T144	2		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T29	9		T127	14		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T4	11		T151	11		T202	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T11	7		T150	23		T260	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T31	9		T149	2		T132	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T127	4		T129	34		T259	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T125	3		T37	10		T131	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T128	2		T202	10		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	4		T30	16		T160	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T44	6		T261	7		T262	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T236	8		T252	10		T256	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	3		T29	1		T48	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T248	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	1		T250	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T60	1		T140	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	14		T253	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	10		T14	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T29	9		T47	1		T60	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T153	20		T164	1		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	1		T154	1		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T11	7		T125	8		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T172	1		T175	3		T228	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T2	2		T226	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T135	1		T48	14		T136	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T159	1		T42	8		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	1		T29	10		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	5		T151	4		T226	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T127	17		T134	1		T41	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T4	13		T202	13		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T1	10		T10	14		T11	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T31	1		T149	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T13	1		T128	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T3	13		T11	4		T30	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T250	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T60	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T175	5		T233	8		T264	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T128	4		T132	9		T207	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T29	4		T60	16		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T153	5		T126	14		T258	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T60	1		T38	3		T131	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	5		T125	9		T236	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T175	4		T17	1		T265	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T2	8		T226	10		T180	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	11		T136	6		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T42	4		T142	8		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T29	9		T151	14		T79	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T151	11		T226	11		T43	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T127	14		T41	2		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	11		T202	9		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T11	7		T127	4		T150	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T31	9		T149	2		T125	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T128	2		T129	13		T202	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T11	4		T30	16		T37	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1