Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21538

1

T1

10

T2

1

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3716

1

T2

9

T3

14

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19572

1

T2

10

T3

24

T4

24

auto[1]

5682

1

T1

10

T3

13

T5

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	259	1			T135	1		T137	1		T38	8
values[0]	16	1			T278	16		-	-		-	-
values[1]	714	1			T2	9		T14	1		T29	13
values[2]	632	1			T4	24		T11	8		T30	28
values[3]	727	1			T127	8		T129	22		T226	8
values[4]	746	1			T11	12		T13	1		T153	25
values[5]	2829	1			T1	10		T10	14		T12	3
values[6]	548	1			T2	1		T31	10		T226	16
values[7]	867	1			T3	13		T11	20		T47	8
values[8]	615	1			T3	14		T29	19		T60	2
values[9]	879	1			T3	10		T5	5		T13	1
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	655	1			T2	9		T14	1		T29	13
values[1]	669	1			T4	24		T11	8		T60	33
values[2]	866	1			T11	12		T127	8		T153	25
values[3]	2728	1			T1	10		T10	14		T12	3
values[4]	660	1			T202	14		T37	23		T172	1
values[5]	668	1			T2	1		T151	15		T226	16
values[6]	822	1			T3	27		T11	20		T29	19
values[7]	540	1			T3	10		T60	2		T125	4
values[8]	884	1			T5	5		T13	1		T128	3
values[9]	157	1			T137	1		T227	9		T99	26
minimum	16605	1			T6	20		T7	154		T8	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	1		T30	12		T151	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T29	9		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T202	13		T39	1		T138	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	13		T11	4		T60	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T172	1		T42	4		T175	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T11	7		T127	4		T153	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T1	10		T10	14		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T154	1		T227	17		T245	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T202	4		T172	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T37	13		T132	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	1		T151	4		T226	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T160	13		T41	3		T266	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	13		T31	1		T47	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T3	14		T11	13		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	10		T48	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T60	1		T125	1		T92	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	5		T128	1		T125	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T13	1		T135	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T137	1		T227	9		T99	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T272	5		T273	11		T274	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16287	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T128	1		T129	17		T79	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T30	16		T151	14		T48	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	8		T29	4		T144	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T202	9		T133	9		T42	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	11		T11	4		T60	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T42	3		T175	5		T246	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	5		T127	4		T153	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T150	23		T260	5		T275	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	1		T230	3		T281	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T202	10		T148	6		T144	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	10		T132	12		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T151	11		T226	14		T180	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T160	11		T41	2		T229	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T31	9		T149	2		T131	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	7		T29	9		T127	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T133	7		T160	9		T236	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T60	1		T125	3		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T128	2		T125	9		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T180	2		T241	12		T167	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T99	12		T19	1		T276	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T273	13		T274	1		T277	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	3		T29	1		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T128	4		T129	13		T79	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T137	1		T38	5		T43	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T135	1		T245	3		T180	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T278	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	1		T151	12		T48	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T29	9		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T30	12		T202	13		T136	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	13		T11	4		T60	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T172	1		T42	8		T175	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T127	4		T129	14		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	1		T172	1		T41	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	7		T153	20		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T1	10		T10	14		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T132	1		T141	1		T228	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	1		T31	1		T226	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T37	13		T159	1		T41	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	13		T47	8		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	13		T127	17		T231	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T48	1		T159	1		T133	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T3	14		T29	10		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	10		T5	5		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T13	1		T138	10		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T38	3		T43	4		T237	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T180	2		T169	11		T323	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T278	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T151	14		T48	11		T132	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	8		T29	4		T128	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T30	16		T202	9		T136	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	11		T11	4		T60	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T42	4		T175	5		T246	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T127	4		T129	8		T226	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T42	3		T238	16		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	5		T153	5		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T150	23		T202	10		T260	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T132	12		T141	2		T259	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T31	9		T226	14		T44	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	10		T41	2		T175	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T149	2		T151	11		T131	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	7		T127	14		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T133	7		T160	9		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T29	9		T60	1		T125	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T128	2		T125	9		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T132	9		T241	12		T167	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	1		T30	17		T151	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	9		T29	5		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T202	10		T39	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	12		T11	5		T60	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T172	1		T42	5		T175	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	8		T127	5		T153	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T1	1		T10	1		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T154	1		T227	2		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T202	11		T172	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T37	15		T132	13		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	1		T151	12		T226	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T160	12		T41	4		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T31	10		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	1		T11	10		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	1		T48	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T60	2		T125	4		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	1		T128	3		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T13	1		T135	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T137	1		T227	1		T99	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T272	1		T273	14		T274	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T128	5		T129	14		T79	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T30	11		T151	11		T48	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T29	8		T161	3		T143	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T202	12		T138	8		T133	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	12		T11	3		T60	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T42	2		T175	8		T246	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	4		T127	3		T153	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T1	9		T10	13		T27	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T227	15		T245	1		T228	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T202	3		T148	7		T143	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T37	8		T259	2		T279	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T151	3		T175	8		T44	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T160	12		T41	1		T266	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	12		T47	7		T279	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	13		T11	10		T29	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	9		T133	9		T160	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T92	15		T138	9		T266	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	4		T125	7		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T245	2		T241	13		T167	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T227	8		T99	13		T19	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T272	4		T273	10		T274	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T324	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T129	16		T270	8		T278	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T137	1		T38	6		T43	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T135	1		T245	1		T180	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T278	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	1		T151	15		T48	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	9		T29	5		T128	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T30	17		T202	10		T136	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	12		T11	5		T60	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T172	1		T42	10		T175	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	5		T129	9		T226	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	1		T172	1		T41	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	8		T153	6		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T1	1		T10	1		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T132	13		T141	3		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	1		T31	10		T226	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	15		T159	1		T41	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T47	1		T149	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	10		T127	15		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T159	1		T133	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	1		T29	10		T60	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T5	1		T128	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	1		T138	1		T132	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T38	2		T43	1		T237	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T245	2		T272	4		T323	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T278	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T151	11		T48	13		T163	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T29	8		T129	16		T143	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T30	11		T202	12		T136	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	12		T11	3		T60	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T42	2		T175	8		T246	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T127	3		T129	13		T131	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	2		T228	3		T238	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	4		T153	19		T245	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1151	1			T1	9		T10	13		T27	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T228	8		T259	2		T279	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T175	8		T44	5		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T37	8		T41	1		T175	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	12		T47	7		T151	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	10		T127	16		T231	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T133	9		T160	2		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	13		T29	9		T92	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	9		T5	4		T125	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T138	9		T241	13		T167	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12