Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21623

1

T1

10

T3

14

T6

20

auto[ADC_CTRL_FILTER_COND_OUT]

3631

1

T2

10

T3

23

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19187

1

T2

1

T6

20

T7

154

auto[1]

6067

1

T1

10

T2

9

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	218	1			T202	14		T159	1		T160	24
values[0]	3	1			T14	1		T60	2		-	-
values[1]	561	1			T3	24		T128	5		T172	2
values[2]	739	1			T29	13		T60	31		T153	25
values[3]	710	1			T11	12		T47	1		T60	2
values[4]	605	1			T2	10		T226	11		T172	1
values[5]	619	1			T135	1		T48	25		T136	10
values[6]	802	1			T5	5		T13	1		T29	19
values[7]	738	1			T4	24		T127	31		T202	22
values[8]	2803	1			T1	10		T10	14		T11	20
values[9]	1034	1			T3	13		T11	8		T13	1
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	488	1			T3	24		T128	5		T60	2
values[1]	786	1			T29	13		T60	31		T153	25
values[2]	844	1			T11	12		T47	1		T60	2
values[3]	413	1			T2	10		T48	25		T159	1
values[4]	702	1			T13	1		T135	1		T136	10
values[5]	939	1			T4	24		T5	5		T29	19
values[6]	2712	1			T1	10		T10	14		T12	3
values[7]	663	1			T11	20		T13	1		T127	8
values[8]	968	1			T3	13		T11	8		T30	28
values[9]	127	1			T236	21		T180	3		T44	17
minimum	16612	1			T6	20		T7	154		T8	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T3	14		T60	1		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	10		T128	1		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	9		T60	15		T131	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T153	20		T227	9		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T47	1		T60	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	7		T125	8		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T245	3		T175	3		T259	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T2	2		T48	14		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	1		T135	1		T136	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T254	1		T42	8		T144	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T29	10		T127	17		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T4	13		T5	5		T151	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T1	10		T10	14		T12	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T31	1		T149	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	13		T13	1		T127	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T125	1		T37	13		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T128	1		T135	1		T202	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T3	13		T11	4		T30	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T180	1		T44	11		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T236	13		T252	1		T325	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16316	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T14	1		T279	12		T232	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T60	1		T264	8		T258	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T128	4		T132	9		T207	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	4		T60	16		T169	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T153	5		T126	14		T258	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T60	1		T38	3		T131	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	5		T125	9		T226	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T175	4		T259	2		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T2	8		T48	11		T180	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T136	6		T79	2		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T42	4		T144	2		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T29	9		T127	14		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T4	11		T151	11		T202	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T150	23		T260	5		T275	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T31	9		T149	2		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	7		T127	4		T129	34
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T125	3		T37	10		T131	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T128	2		T202	10		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	4		T30	16		T160	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T180	2		T44	6		T261	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T236	8		T252	10		T325	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	3		T29	1		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T100	10		T252	6		T293	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T202	4		T159	1		T326	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T160	13		T203	1		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T60	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T14	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	14		T172	1		T253	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	10		T128	1		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T29	9		T60	15		T138	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T153	20		T164	1		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	1		T60	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	7		T125	8		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T172	1		T175	3		T228	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	2		T226	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T135	1		T136	4		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T48	14		T159	1		T42	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	1		T29	10		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	5		T151	4		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T127	17		T41	3		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T4	13		T202	13		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T1	10		T10	14		T11	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T31	1		T149	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	1		T128	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T3	13		T11	4		T30	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T202	10		T44	6		T237	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T160	11		T252	10		T327	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T60	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T175	5		T233	8		T264	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T128	4		T132	9		T207	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T29	4		T60	16		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T153	5		T258	7		T283	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T60	1		T38	3		T131	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	5		T125	9		T236	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T175	4		T17	1		T265	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	8		T226	10		T180	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T136	6		T148	6		T144	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T48	11		T42	4		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	9		T151	14		T79	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T151	11		T226	4		T160	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T127	14		T41	2		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	11		T202	9		T226	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T11	7		T127	4		T150	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	9		T149	2		T125	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T128	2		T129	13		T133	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	4		T30	16		T236	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	1		T60	2		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	1		T128	5		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	5		T60	17		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T153	6		T227	1		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	1		T60	2		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T11	8		T125	10		T226	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T245	1		T175	5		T259	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T2	10		T48	12		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	1		T135	1		T136	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T254	1		T42	10		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T29	10		T127	15		T151	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T4	12		T5	1		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T1	1		T10	1		T12	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T31	10		T149	3		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	10		T13	1		T127	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T125	4		T37	15		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T128	3		T135	1		T202	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	1		T11	5		T30	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T180	3		T44	12		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T236	9		T252	11		T325	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16486	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T14	1		T279	1		T232	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T3	13		T168	6		T258	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	9		T145	12		T207	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	8		T60	14		T131	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T153	19		T227	8		T266	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T38	2		T92	15		T161	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	4		T125	7		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T245	2		T175	2		T259	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T48	13		T142	10		T176	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T136	3		T245	1		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T42	2		T144	13		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T29	9		T127	16		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T4	12		T5	4		T151	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T1	9		T10	13		T27	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T138	9		T133	8		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	10		T127	3		T129	46
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T37	8		T131	13		T266	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T202	3		T133	9		T145	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	12		T11	3		T30	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T44	5		T261	16		T296	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T236	12		T328	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T175	8		T233	8		T267	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T279	11		T293	2		T329	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T202	11		T159	1		T326	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T160	12		T203	1		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T60	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T14	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	1		T172	1		T253	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	1		T128	5		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T29	5		T60	17		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T153	6		T164	1		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	1		T60	2		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	8		T125	10		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T172	1		T175	5		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	10		T226	11		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T135	1		T136	7		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	12		T159	1		T42	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	1		T29	10		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T5	1		T151	12		T226	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T127	15		T41	4		T141	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	12		T202	10		T226	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T1	1		T10	1		T11	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T31	10		T149	3		T125	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T13	1		T128	3		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	1		T11	5		T30	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T202	3		T44	5		T237	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T160	12		T330	15		T328	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T3	13		T175	8		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	9		T145	12		T207	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T29	8		T60	14		T138	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T153	19		T266	13		T228	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T38	2		T92	15		T131	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	4		T125	7		T227	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T175	2		T228	3		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T176	9		T235	8		T238	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T136	3		T245	3		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T48	13		T42	2		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T29	9		T151	11		T175	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	4		T151	3		T160	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T127	16		T41	1		T247	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	12		T202	12		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T1	9		T10	13		T11	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T37	8		T131	13		T266	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T129	17		T231	16		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	12		T11	3		T30	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12