CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 25254 | 1 | T1 | 10 | T2 | 10 | T3 | 37 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 21843 | 1 | T1 | 10 | T2 | 1 | T3 | 14 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3411 | 1 | T2 | 9 | T3 | 23 | T5 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19717 | 1 | T2 | 9 | T3 | 10 | T4 | 24 | ||||
auto[1] | 5537 | 1 | T1 | 10 | T2 | 1 | T3 | 27 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21283 | 1 | T1 | 10 | T2 | 2 | T3 | 37 | ||||
auto[1] | 3971 | 1 | T2 | 8 | T4 | 11 | T11 | 19 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 30 | 1 | T134 | 1 | T42 | 12 | T320 | 7 | ||||
values[0] | 94 | 1 | T29 | 13 | T47 | 8 | T326 | 1 | ||||
values[1] | 439 | 1 | T13 | 1 | T135 | 1 | T151 | 15 | ||||
values[2] | 2850 | 1 | T1 | 10 | T10 | 14 | T12 | 3 | ||||
values[3] | 672 | 1 | T2 | 1 | T128 | 5 | T60 | 2 | ||||
values[4] | 804 | 1 | T4 | 24 | T13 | 1 | T14 | 1 | ||||
values[5] | 725 | 1 | T5 | 5 | T129 | 31 | T202 | 22 | ||||
values[6] | 724 | 1 | T11 | 40 | T29 | 19 | T47 | 1 | ||||
values[7] | 585 | 1 | T3 | 13 | T127 | 39 | T135 | 2 | ||||
values[8] | 589 | 1 | T3 | 14 | T60 | 2 | T125 | 4 | ||||
values[9] | 1320 | 1 | T2 | 9 | T3 | 10 | T149 | 3 | ||||
minimum | 16422 | 1 | T6 | 20 | T7 | 154 | T8 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 722 | 1 | T13 | 1 | T29 | 13 | T31 | 10 | ||||
values[1] | 2852 | 1 | T1 | 10 | T10 | 14 | T12 | 3 | ||||
values[2] | 655 | 1 | T2 | 1 | T13 | 1 | T128 | 5 | ||||
values[3] | 899 | 1 | T4 | 24 | T129 | 31 | T226 | 11 | ||||
values[4] | 593 | 1 | T5 | 5 | T11 | 8 | T14 | 1 | ||||
values[5] | 632 | 1 | T3 | 13 | T11 | 32 | T47 | 1 | ||||
values[6] | 698 | 1 | T3 | 14 | T127 | 39 | T60 | 2 | ||||
values[7] | 698 | 1 | T125 | 4 | T129 | 52 | T92 | 16 | ||||
values[8] | 1018 | 1 | T2 | 9 | T3 | 10 | T48 | 25 | ||||
values[9] | 55 | 1 | T149 | 3 | T298 | 1 | T331 | 1 | ||||
minimum | 16432 | 1 | T6 | 20 | T7 | 154 | T8 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21340 | 1 | T1 | 1 | T2 | 10 | T3 | 3 | ||||
auto[1] | 3914 | 1 | T1 | 9 | T3 | 34 | T4 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 264 | 1 | T29 | 9 | T31 | 1 | T135 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 169 | 1 | T13 | 1 | T47 | 8 | T137 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 1475 | 1 | T1 | 10 | T10 | 14 | T12 | 3 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 240 | 1 | T60 | 1 | T153 | 20 | T37 | 13 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 208 | 1 | T2 | 1 | T128 | 1 | T125 | 8 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 156 | 1 | T13 | 1 | T130 | 1 | T164 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 229 | 1 | T4 | 13 | T226 | 1 | T130 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 237 | 1 | T129 | 18 | T38 | 5 | T40 | 2 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 129 | 1 | T14 | 1 | T226 | 1 | T138 | 9 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 208 | 1 | T5 | 5 | T11 | 4 | T29 | 10 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 207 | 1 | T47 | 1 | T60 | 15 | T48 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 171 | 1 | T3 | 13 | T11 | 20 | T134 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 156 | 1 | T3 | 14 | T135 | 2 | T139 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 189 | 1 | T127 | 21 | T60 | 1 | T226 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 197 | 1 | T125 | 1 | T131 | 14 | T253 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 168 | 1 | T129 | 31 | T92 | 16 | T132 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 242 | 1 | T48 | 14 | T137 | 1 | T160 | 16 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 330 | 1 | T2 | 1 | T3 | 10 | T172 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 16 | 1 | T331 | 1 | T267 | 3 | T332 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 19 | 1 | T149 | 1 | T298 | 1 | T333 | 14 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16271 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 2 | 1 | T167 | 2 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 155 | 1 | T29 | 4 | T31 | 9 | T151 | 11 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 134 | 1 | T132 | 12 | T141 | 7 | T237 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 996 | 1 | T30 | 16 | T150 | 23 | T202 | 10 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 141 | 1 | T60 | 1 | T153 | 5 | T37 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 130 | 1 | T128 | 4 | T125 | 9 | T180 | 5 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 161 | 1 | T241 | 12 | T234 | 12 | T17 | 1 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 258 | 1 | T4 | 11 | T226 | 10 | T131 | 9 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T129 | 13 | T38 | 3 | T237 | 14 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 99 | 1 | T226 | 4 | T229 | 4 | T230 | 3 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 157 | 1 | T11 | 4 | T29 | 9 | T128 | 2 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 109 | 1 | T60 | 16 | T144 | 2 | T238 | 9 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 145 | 1 | T11 | 12 | T236 | 8 | T42 | 3 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 121 | 1 | T141 | 13 | T46 | 1 | T334 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 232 | 1 | T127 | 18 | T60 | 1 | T226 | 7 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 199 | 1 | T125 | 3 | T175 | 5 | T142 | 8 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 134 | 1 | T129 | 21 | T132 | 9 | T41 | 2 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 227 | 1 | T48 | 11 | T160 | 20 | T42 | 4 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 219 | 1 | T2 | 8 | T132 | 10 | T43 | 4 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 4 | 1 | T332 | 1 | T320 | 2 | T335 | 1 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 16 | 1 | T149 | 2 | T285 | 14 | - | - | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T11 | 3 | T29 | 1 | T48 | 1 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 8 | 1 | T167 | 8 | - | - | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 3 | 45 | 93.75 | 3 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 23 | 1 | T42 | 8 | T320 | 5 | T324 | 10 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T134 | 1 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 24 | 1 | T29 | 9 | T326 | 1 | T203 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 30 | 1 | T47 | 8 | T141 | 1 | T233 | 9 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 178 | 1 | T135 | 1 | T151 | 4 | T172 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 68 | 1 | T13 | 1 | T137 | 1 | T172 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 1475 | 1 | T1 | 10 | T10 | 14 | T12 | 3 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 242 | 1 | T153 | 20 | T37 | 13 | T138 | 10 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 218 | 1 | T2 | 1 | T128 | 1 | T125 | 8 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 174 | 1 | T60 | 1 | T173 | 1 | T142 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 237 | 1 | T4 | 13 | T14 | 1 | T226 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 193 | 1 | T13 | 1 | T128 | 1 | T38 | 5 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 141 | 1 | T226 | 1 | T131 | 14 | T164 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 255 | 1 | T5 | 5 | T129 | 18 | T202 | 13 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 222 | 1 | T47 | 1 | T60 | 15 | T48 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 187 | 1 | T11 | 24 | T29 | 10 | T151 | 12 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 144 | 1 | T135 | 2 | T159 | 1 | T139 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 174 | 1 | T3 | 13 | T127 | 21 | T133 | 10 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 141 | 1 | T3 | 14 | T125 | 1 | T131 | 14 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 176 | 1 | T60 | 1 | T129 | 17 | T226 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 320 | 1 | T48 | 14 | T137 | 1 | T160 | 16 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 389 | 1 | T2 | 1 | T3 | 10 | T149 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16271 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 6 | 1 | T42 | 4 | T320 | 2 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T29 | 4 | T250 | 9 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 27 | 1 | T141 | 7 | T233 | 8 | T336 | 12 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 96 | 1 | T151 | 11 | T180 | 2 | T163 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 97 | 1 | T132 | 12 | T167 | 8 | T252 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 1013 | 1 | T30 | 16 | T31 | 9 | T150 | 23 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 120 | 1 | T153 | 5 | T37 | 10 | T176 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 119 | 1 | T128 | 4 | T125 | 9 | T292 | 10 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 161 | 1 | T60 | 1 | T142 | 1 | T241 | 12 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 245 | 1 | T4 | 11 | T226 | 10 | T180 | 5 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 129 | 1 | T128 | 2 | T38 | 3 | T237 | 14 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 125 | 1 | T226 | 4 | T131 | 9 | T233 | 13 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 204 | 1 | T129 | 13 | T202 | 9 | T131 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 138 | 1 | T60 | 16 | T144 | 2 | T238 | 9 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T11 | 16 | T29 | 9 | T151 | 14 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 103 | 1 | T141 | 13 | T46 | 1 | T256 | 10 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 164 | 1 | T127 | 18 | T133 | 7 | T236 | 6 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 110 | 1 | T125 | 3 | T175 | 5 | T142 | 8 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 162 | 1 | T60 | 1 | T129 | 13 | T226 | 7 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 330 | 1 | T48 | 11 | T160 | 20 | T246 | 6 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 281 | 1 | T2 | 8 | T149 | 2 | T129 | 8 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T11 | 3 | T29 | 1 | T48 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 5 | 43 | 89.58 | 5 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [maximum] | * | -- | -- | 2 | |
[auto[1]] | [maximum] | * | -- | -- | 2 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_IN]] | 0 | 1 | 1 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 225 | 1 | T29 | 5 | T31 | 10 | T135 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 171 | 1 | T13 | 1 | T47 | 1 | T137 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 1331 | 1 | T1 | 1 | T10 | 1 | T12 | 3 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 178 | 1 | T60 | 2 | T153 | 6 | T37 | 15 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 169 | 1 | T2 | 1 | T128 | 5 | T125 | 10 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 193 | 1 | T13 | 1 | T130 | 1 | T164 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 296 | 1 | T4 | 12 | T226 | 11 | T130 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 214 | 1 | T129 | 14 | T38 | 6 | T40 | 2 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 132 | 1 | T14 | 1 | T226 | 5 | T138 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 201 | 1 | T5 | 1 | T11 | 5 | T29 | 10 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 146 | 1 | T47 | 1 | T60 | 17 | T48 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 186 | 1 | T3 | 1 | T11 | 18 | T134 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 158 | 1 | T3 | 1 | T135 | 2 | T139 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 285 | 1 | T127 | 20 | T60 | 2 | T226 | 8 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 237 | 1 | T125 | 4 | T131 | 1 | T253 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 178 | 1 | T129 | 23 | T92 | 1 | T132 | 10 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 290 | 1 | T48 | 12 | T137 | 1 | T160 | 22 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 285 | 1 | T2 | 9 | T3 | 1 | T172 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 12 | 1 | T331 | 1 | T267 | 1 | T332 | 2 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 22 | 1 | T149 | 3 | T298 | 1 | T333 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16422 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 9 | 1 | T167 | 9 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 194 | 1 | T29 | 8 | T151 | 3 | T136 | 3 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 132 | 1 | T47 | 7 | T175 | 8 | T266 | 13 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 1140 | 1 | T1 | 9 | T10 | 13 | T27 | 7 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 203 | 1 | T153 | 19 | T37 | 8 | T138 | 9 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 169 | 1 | T125 | 7 | T245 | 2 | T168 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 124 | 1 | T241 | 13 | T234 | 11 | T17 | 2 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 191 | 1 | T4 | 12 | T131 | 13 | T229 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 198 | 1 | T129 | 17 | T38 | 2 | T237 | 16 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 96 | 1 | T138 | 8 | T229 | 2 | T230 | 3 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 164 | 1 | T5 | 4 | T11 | 3 | T29 | 9 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 170 | 1 | T60 | 14 | T266 | 11 | T144 | 13 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 130 | 1 | T3 | 12 | T11 | 14 | T236 | 12 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 119 | 1 | T3 | 13 | T46 | 2 | T334 | 3 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 136 | 1 | T127 | 19 | T133 | 9 | T236 | 10 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 159 | 1 | T131 | 13 | T175 | 8 | T142 | 10 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 124 | 1 | T129 | 29 | T92 | 15 | T41 | 1 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 179 | 1 | T48 | 13 | T160 | 14 | T42 | 2 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 264 | 1 | T3 | 9 | T227 | 13 | T43 | 1 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 8 | 1 | T267 | 2 | T320 | 4 | T335 | 2 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 13 | 1 | T333 | 13 | - | - | - | - | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T167 | 1 | - | - | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 14 | 1 | T42 | 10 | T320 | 3 | T324 | 1 | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T134 | 1 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 18 | 1 | T29 | 5 | T326 | 1 | T203 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 31 | 1 | T47 | 1 | T141 | 8 | T233 | 9 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 142 | 1 | T135 | 1 | T151 | 12 | T172 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 120 | 1 | T13 | 1 | T137 | 1 | T172 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 1359 | 1 | T1 | 1 | T10 | 1 | T12 | 3 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 157 | 1 | T153 | 6 | T37 | 15 | T138 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 156 | 1 | T2 | 1 | T128 | 5 | T125 | 10 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T60 | 2 | T173 | 1 | T142 | 2 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 290 | 1 | T4 | 12 | T14 | 1 | T226 | 11 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 169 | 1 | T13 | 1 | T128 | 3 | T38 | 6 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T226 | 5 | T131 | 10 | T164 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 245 | 1 | T5 | 1 | T129 | 14 | T202 | 10 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 181 | 1 | T47 | 1 | T60 | 17 | T48 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 222 | 1 | T11 | 23 | T29 | 10 | T151 | 15 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 137 | 1 | T135 | 2 | T159 | 1 | T139 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 202 | 1 | T3 | 1 | T127 | 20 | T133 | 8 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 142 | 1 | T3 | 1 | T125 | 4 | T131 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 214 | 1 | T60 | 2 | T129 | 14 | T226 | 8 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 405 | 1 | T48 | 12 | T137 | 1 | T160 | 22 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 366 | 1 | T2 | 9 | T3 | 1 | T149 | 3 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16422 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 15 | 1 | T42 | 2 | T320 | 4 | T324 | 9 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 19 | 1 | T29 | 8 | T337 | 11 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 26 | 1 | T47 | 7 | T233 | 8 | T336 | 11 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 132 | 1 | T151 | 3 | T227 | 2 | T163 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 45 | 1 | T228 | 2 | T167 | 1 | T204 | 10 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 1129 | 1 | T1 | 9 | T10 | 13 | T27 | 7 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 205 | 1 | T153 | 19 | T37 | 8 | T138 | 9 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 181 | 1 | T125 | 7 | T231 | 16 | T143 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 140 | 1 | T241 | 13 | T145 | 21 | T234 | 11 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 192 | 1 | T4 | 12 | T245 | 2 | T229 | 10 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 153 | 1 | T38 | 2 | T237 | 16 | T322 | 9 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 114 | 1 | T131 | 13 | T233 | 12 | T338 | 4 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 214 | 1 | T5 | 4 | T129 | 17 | T202 | 12 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 179 | 1 | T60 | 14 | T138 | 8 | T266 | 11 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 142 | 1 | T11 | 17 | T29 | 9 | T151 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 110 | 1 | T46 | 2 | T256 | 11 | T323 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 136 | 1 | T3 | 12 | T127 | 19 | T133 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 109 | 1 | T3 | 13 | T131 | 13 | T175 | 8 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 124 | 1 | T129 | 16 | T92 | 15 | T41 | 1 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 245 | 1 | T48 | 13 | T160 | 14 | T266 | 2 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 304 | 1 | T3 | 9 | T129 | 13 | T227 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 21340 | 1 | T1 | 1 | T2 | 10 | T3 | 3 | ||||
auto[1] | auto[0] | 3914 | 1 | T1 | 9 | T3 | 34 | T4 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |